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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t, n; string s; cin >> t; while (t--) { cin >> n >> s; vector<int> szs; char prev = s.front(); int sz = 0; for (char c : s) { if (c != prev) { szs.push_back(sz); sz = 1; } else sz++; prev = c; } szs.push_back(sz); int cnt = 0, id = 1; for (int i : szs) { if (i > 1) cnt += min(i - 1, id - cnt); id++; } cout << cnt + (szs.size() - cnt + 1) / 2 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200010; int nowarn; int n, m; namespace Tree { int head[MAXN], nxt[MAXN], to[MAXN], eidx; void init() { eidx = 0; memset(head, -1, sizeof(head)); } void adde(int u, int v) { to[eidx] = v, nxt[eidx] = head[u], head[u] = eidx++; } } // namespace Tree namespace DFN { int dfn[MAXN], dfn_cnt, son[MAXN], dep[MAXN], top[MAXN], size[MAXN], pa[MAXN]; void dfs1(int u, int fa, int d) { using namespace Tree; pa[u] = fa, dep[u] = d, son[u] = 0, size[u] = 1; for (int i = head[u]; ~i; i = nxt[i]) { int v = to[i]; dfs1(v, u, d + 1); size[u] += size[v]; if (size[v] > size[son[u]]) son[u] = v; } } void dfs2(int u, int tp) { using namespace Tree; top[u] = tp, dfn[u] = ++dfn_cnt; if (son[u]) dfs2(son[u], tp); for (int i = head[u]; ~i; i = nxt[i]) { int v = to[i]; if (v == son[u]) continue; dfs2(v, v); } } void prelude() { size[0] = dfn_cnt = 0; dfs1(1, 0, 1); dfs2(1, 1); } int lca(int u, int v) { while (top[u] != top[v]) { if (dep[top[u]] < dep[top[v]]) swap(u, v); u = pa[top[u]]; } return min(u, v); } } // namespace DFN int lowbit(int x) { return x & (-x); } struct BIT { long long c[MAXN]; void init() { memset(c, 0, sizeof(c)); } void add(int p, long long v) { for (; p <= n; p += lowbit(p)) c[p] += v; } long long sum(int p) const { long long s = 0; for (; p; p -= lowbit(p)) s += c[p]; return s; } long long sum(int l, int r) const { return sum(r) - sum(l - 1); } }; struct Triple { int first, second, val; Triple() {} Triple(int a, int b, int c) : first(a), second(b), val(c) {} }; vector<Triple> chain[MAXN]; BIT sf, sg; long long query(int u, int v, const BIT &bit) { using namespace DFN; long long s = 0; while (top[u] != top[v]) { s += bit.sum(dfn[top[v]], dfn[v]); v = pa[top[v]]; } s += bit.sum(dfn[u], dfn[v]); return s; } long long f[MAXN], g[MAXN]; void dp(int u) { using namespace Tree; using namespace DFN; g[u] = 0; for (int i = head[u]; ~i; i = nxt[i]) dp(to[i]), g[u] += f[to[i]]; sg.add(dfn[u], g[u]); f[u] = g[u]; for (int i = 0; i < (int)chain[u].size(); ++i) { Triple tp = chain[u][i]; int s = tp.first, t = tp.second, w = tp.val; if (t == u) swap(s, t); if (s == u) { f[u] = max(f[u], query(u, t, sg) - query(u, t, sf) + w); } else { f[u] = max(f[u], query(u, s, sg) + query(u, t, sg) - g[u] - query(u, s, sf) - query(u, t, sf) + w); } } sf.add(dfn[u], f[u]); } int main() { nowarn = scanf( %d%d , &n, &m); Tree::init(); for (int i = 2; i <= n; ++i) { int p; nowarn = scanf( %d , &p); Tree::adde(p, i); } DFN::prelude(); while (m--) { int u, v, w; nowarn = scanf( %d%d%d , &u, &v, &w); int lca = DFN::lca(u, v); chain[lca].push_back(Triple(u, v, w)); } sf.init(), sg.init(); dp(1); printf( %lld n , f[1]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000007; int n, m; int fa[200010]; struct Line { int u, v, c; } l[200010]; int p[200010]; bool cmp(int x, int y) { return l[x].c < l[y].c; } bool intree[200010]; struct Edge { int v, id, nxt; } e[400010]; int tot; int first[200010]; void build(int u, int v, int id) { e[++tot] = (Edge){v, id, first[u]}; first[u] = tot; return; } int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } bool merge(int u, int v) { u = find(u); v = find(v); if (u == v) return false; fa[u] = v; return true; } void init() { for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= m; i++) p[i] = i; sort(p + 1, p + m + 1, cmp); for (int i = 1; i <= m; i++) { int x = p[i]; if (merge(l[x].u, l[x].v)) { intree[x] = true; build(l[x].u, l[x].v, x); build(l[x].v, l[x].u, x); } } return; } const int M = 20; int f[200010][20]; int g[200010][20]; int h[200010][20]; int dep[200010]; int Id[200010]; void dfs(int u, int lst, int lste) { Id[u] = lste; dep[u] = dep[lst] + 1; f[u][0] = lst; g[u][0] = l[lste].c; h[u][0] = INF; for (int i = 1; i < M; i++) { f[u][i] = f[f[u][i - 1]][i - 1]; g[u][i] = max(g[u][i - 1], g[f[u][i - 1]][i - 1]); h[u][i] = INF; } for (int i = first[u]; i; i = e[i].nxt) if (e[i].v != lst) dfs(e[i].v, u, e[i].id); return; } int ans[200010]; void solve(int x) { int u = l[x].u; int v = l[x].v; int c = l[x].c; ans[x] = 0; if (dep[u] < dep[v]) swap(u, v); int need = dep[u] - dep[v], cur = 0; while (need) { if (need & 1) { ans[x] = max(ans[x], g[u][cur]); h[u][cur] = min(h[u][cur], c); u = f[u][cur]; } need >>= 1; cur++; } if (u == v) return; for (int i = M - 1; i >= 0; i--) if (f[u][i] != f[v][i]) { ans[x] = max(ans[x], g[u][i]); ans[x] = max(ans[x], g[v][i]); h[u][i] = min(h[u][i], c); h[v][i] = min(h[v][i], c); u = f[u][i]; v = f[v][i]; } ans[x] = max(ans[x], g[u][0]); ans[x] = max(ans[x], g[v][0]); h[u][0] = min(h[u][0], c); h[v][0] = min(h[v][0], c); return; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d %d %d , &l[i].u, &l[i].v, &l[i].c); init(); dfs(1, 0, 0); for (int i = 1; i <= m; i++) if (!intree[i]) solve(i); for (int i = M - 1; i > 0; i--) for (int u = 1; u <= n; u++) { h[u][i - 1] = min(h[u][i - 1], h[u][i]); h[f[u][i - 1]][i - 1] = min(h[f[u][i - 1]][i - 1], h[u][i]); } for (int u = 2; u <= n; u++) ans[Id[u]] = h[u][0]; for (int i = 1; i <= m; i++) if (ans[i] != INF) printf( %d , ans[i] - 1); else printf( -1 ); printf( n ); return 0; } |
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: reg_grp.v
// Project: NetFPGA
// Description: Generic register group
//
// Muxes the registers for a group
//
// Note: The downstream modules should respect the rules for the number of
// cycles to hold ack high.
//
///////////////////////////////////////////////////////////////////////////////
module reg_grp #(parameter
REG_ADDR_BITS = 10,
NUM_OUTPUTS = 4
)
(
// Upstream register interface
input reg_req,
input reg_rd_wr_L,
input [REG_ADDR_BITS -1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH -1:0] reg_wr_data,
output reg reg_ack,
output reg [`CPCI_NF2_DATA_WIDTH -1:0] reg_rd_data,
// Downstream register interface
output [NUM_OUTPUTS - 1 : 0] local_reg_req,
output [NUM_OUTPUTS - 1 : 0] local_reg_rd_wr_L,
output [NUM_OUTPUTS * (REG_ADDR_BITS - log2(NUM_OUTPUTS)) -1:0] local_reg_addr,
output [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_wr_data,
input [NUM_OUTPUTS - 1 : 0] local_reg_ack,
input [NUM_OUTPUTS * `CPCI_NF2_DATA_WIDTH -1:0] local_reg_rd_data,
//-- misc
input clk,
input reset
);
// Log base 2 function
//
// Returns ceil(log2(X))
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// Register addresses
localparam SWITCH_ADDR_BITS = log2(NUM_OUTPUTS);
// ===========================================
// Local variables
wire [SWITCH_ADDR_BITS - 1 : 0] sel;
integer i;
// Internal register interface signals
reg int_reg_req[NUM_OUTPUTS - 1 : 0];
reg int_reg_rd_wr_L[NUM_OUTPUTS - 1 : 0];
reg [REG_ADDR_BITS -1:0] int_reg_addr[NUM_OUTPUTS - 1 : 0];
reg [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_wr_data[NUM_OUTPUTS - 1 : 0];
wire int_reg_ack[NUM_OUTPUTS - 1 : 0];
wire [`CPCI_NF2_DATA_WIDTH -1:0] int_reg_rd_data[NUM_OUTPUTS - 1 : 0];
assign sel = reg_addr[REG_ADDR_BITS - 1 : REG_ADDR_BITS - SWITCH_ADDR_BITS];
// =====================================================
// Process register requests
always @(posedge clk)
begin
for (i = 0; i < NUM_OUTPUTS ; i = i + 1) begin
if (reset || sel != i) begin
int_reg_req[i] <= 1'b0;
int_reg_rd_wr_L[i] <= 1'b0;
int_reg_addr[i] <= 'h0;
int_reg_wr_data[i] <= 'h0;
end
else begin
int_reg_req[i] <= reg_req;
int_reg_rd_wr_L[i] <= reg_rd_wr_L;
int_reg_addr[i] <= reg_addr;
int_reg_wr_data[i] <= reg_wr_data;
end
end // for
end
always @(posedge clk)
begin
if (reset || sel >= NUM_OUTPUTS) begin
// Reset the outputs
reg_ack <= 1'b0;
reg_rd_data <= reset ? 'h0 : 'h dead_beef;
end
else begin
reg_ack <= int_reg_ack[sel];
reg_rd_data <= int_reg_rd_data[sel];
end
end
// =====================================================
// Logic to split/join inputs/outputs
genvar j;
generate
for (j = 0; j < NUM_OUTPUTS ; j = j + 1) begin : flatten
assign local_reg_req[j] = int_reg_req[j];
assign local_reg_rd_wr_L[j] = int_reg_rd_wr_L[j];
assign local_reg_addr[j * (REG_ADDR_BITS - SWITCH_ADDR_BITS) +: (REG_ADDR_BITS - SWITCH_ADDR_BITS)] = int_reg_addr[j];
assign local_reg_wr_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH] = int_reg_wr_data[j];
assign int_reg_ack[j] = local_reg_ack[j];
assign int_reg_rd_data[j] = local_reg_rd_data[j * `CPCI_NF2_DATA_WIDTH +: `CPCI_NF2_DATA_WIDTH];
end
endgenerate
// =====================================================
// Verify that ack is never high when the request signal is low
// synthesis translate_off
integer k;
always @(posedge clk) begin
if (reg_req === 1'b0)
for (k = 0; k < NUM_OUTPUTS ; k = k + 1)
if (int_reg_ack[k] === 1'b1)
$display($time, " %m: ERROR: int_reg_ack[%1d] is high when reg_req is low", k);
end
// synthesis translate_on
endmodule // reg_grp
|
#include <bits/stdc++.h> using namespace std; struct Problem { long long as, at, bs, bt; double pr; } a[2000]; const long long P = (long long)1e6; int n, m; long long fail[1001]; long long f[1001][1600]; double g[1001][1600]; bool cmp(Problem u, Problem v) { return u.bt * u.pr * (1 - v.pr) < v.bt * v.pr * (1 - u.pr); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %I64d%I64d%I64d%I64d%lf , &a[i].as, &a[i].bs, &a[i].at, &a[i].bt, &a[i].pr); sort(a + 1, a + n + 1, cmp); for (int i = 1; i <= n; i++) fail[i] = (long long)(a[i].pr * P + 0.5); for (int i = 0; i <= n; i++) for (int j = 0; j <= m; j++) f[i][j] = -1; f[0][0] = 0; for (int i = 0; i < n; i++) for (int j = 0; j <= m; j++) if (f[i][j] != -1) { int t = i + 1; if (f[i + 1][j] < f[i][j] || (f[i + 1][j] == f[i][j] && g[i + 1][j] > g[i][j])) { f[i + 1][j] = f[i][j]; g[i + 1][j] = g[i][j]; } if (j + a[t].at <= m) { long long t1 = f[i][j] + a[t].as * P; double p1 = g[i][j] + a[t].at; int j1 = j + a[t].at; if (f[i + 1][j1] < t1 || (f[i + 1][j1] == t1 && g[i + 1][j1] > p1)) { f[i + 1][j1] = t1; g[i + 1][j1] = p1; } } if (j + a[t].at + a[t].bt <= m) { long long t1 = f[i][j] + a[t].as * P + a[t].bs * (P - fail[t]); double p1 = g[i][j] * a[t].pr + a[t].at + (j + a[t].bt) * (1 - a[t].pr); int j1 = j + a[t].at + a[t].bt; if (f[i + 1][j1] < t1 || (f[i + 1][j1] == t1 && g[i + 1][j1] > p1)) { f[i + 1][j1] = t1; g[i + 1][j1] = p1; } } } long long ans1 = -1; double ans2 = 0; for (int i = 0; i <= m; i++) if (ans1 < f[n][i] || (ans1 == f[n][i] && g[n][i] < ans2)) ans1 = f[n][i], ans2 = g[n][i]; printf( %.9lf %.9lf n , (double)ans1 / (double)P, ans2); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_2_V
`define SKY130_FD_SC_HD__A221OI_2_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a221oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_2_V
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[3][3], b[3][3]; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cin >> a[i][j]; a[i][j] %= 2; b[i][j] = 0; } } pair<int, int> f[] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}, {0, 0}}; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { for (auto m : f) { if (i + m.first < 3 && i + m.first > -1) { if (j + m.second < 3 && j + m.second > -1) { if (a[i + m.first][j + m.second] % 2) { b[i][j]++; b[i][j] %= 2; } } } } } } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cout << (b[i][j] ^ 1); } cout << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/27 21:57:27
// Design Name:
// Module Name: Datapath_with_mux_adder_register_memory
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Datapath_with_mux_adder_register_memory
#(parameter DATA_WIDTH = 8)
(
input Clk,
input reset,
input [(DATA_WIDTH - 1):0] reset_value,
input a_sel,
input next_sel,
input sum_sel,
output [(DATA_WIDTH - 1):0] a_o,
output [(DATA_WIDTH - 1):0] next_o,
output [(DATA_WIDTH - 1):0] sum_o,
output [(DATA_WIDTH - 1):0] ld_next_o,
output [(DATA_WIDTH - 1):0] ld_sum_o,
output [(DATA_WIDTH - 1):0] add1_o,
output [(DATA_WIDTH - 1):0] add2_o,
output [(DATA_WIDTH - 1):0] mem_o,
output next_zero
);
assign next_zero = (next_o == 0);
mux_8bit_2to1_behavior #(DATA_WIDTH) A (.x(ld_next_o), .y(add2_o), .s(a_sel), .m(a_o));
mux_8bit_2to1_behavior #(DATA_WIDTH) NEXT (.x(0), .y(mem_o), .s(next_sel), .m(next_o));
mux_8bit_2to1_behavior #(DATA_WIDTH) SUM (.x(0), .y(add1_o), .s(sum_sel), .m(sum_o));
Register_behavior #(DATA_WIDTH) LD_NEXT (.Clk(Clk), .D(next_o), .reset(reset), .reset_value(reset_value), .Q(ld_next_o));
Register_behavior #(DATA_WIDTH) LD_SUM (.Clk(Clk), .D(sum_o), .reset(reset), .reset_value(reset_value), .Q(ld_sum_o));
Adder_dataflow #(DATA_WIDTH) ADD1 (.a(ld_sum_o), .b(mem_o), .s(add1_o));
Adder_dataflow #(DATA_WIDTH) ADD2 (.a(ld_next_o), .b(1), .s(add2_o));
memory #(DATA_WIDTH) MEM (.address(a_o), .data(mem_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 1; void solve() { long long int n, x, ans = 1, p = -1, q = -1, c; cin >> n; set<long long int> s; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i], s.insert(a[i]); for (long long int i = 0; i < n; i++) { for (long long int j = 0; j < 32; j++) { c = 1; if (s.find(a[i] - (1 << j)) != s.end()) { q = a[i] - (1 << j); c++; } if (s.find(a[i] + (1 << j)) != s.end()) { q = a[i] + (1 << j); c++; } if (c == 3) { cout << 3 << n ; cout << a[i] - (1 << j) << << a[i] << << a[i] + (1 << j); return; } if (c == 2) p = a[i]; ans = max(ans, c); } } cout << ans << n ; if (ans == 2) cout << p << << q; if (ans == 1) cout << a[0]; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; } |
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 4
*/
// Testbench for behavioral model for the register file
// Import the modules that will be tested for in this testbench
`include "regfile.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f regfile.f +gui
module tb_regfile();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & out_valid output signals
wire [WIDTH-1:0] d_out;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren
reg clock,wr_en;
// data_in
reg [WIDTH-1:0] d_in;
// wraddr, rdaddr
reg [DEPTH-1:0] w_addr,r_addr ;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
regfile rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,d_in,w_addr,r_addr,wr_en,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/seq_detect.sdf",rg,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
d_in=8'd6;
w_addr=3'd0;
r_addr=3'd0;
wr_en=1;
#10
d_in=8'd7;
w_addr=3'd0;
r_addr=3'd0;
wr_en=0;
// Write...
#10
d_in=8'd6;
w_addr=3'd2;
r_addr=3'd0;
wr_en=1;
#10
d_in=8'd5;
w_addr=3'd3;
r_addr=3'd1;
wr_en=1;
#10
d_in=8'd100;
w_addr=3'd4;
r_addr=3'd7;
wr_en=1;
#10
d_in=8'd200;
w_addr=3'd5;
r_addr=3'd6;
wr_en=1;
// Read...
#10
d_in=8'd3;
w_addr=3'd4;
r_addr=3'd2;
wr_en=0;
#10
d_in=8'd2;
w_addr=3'd5;
r_addr=3'd3;
wr_en=0;
#10
d_in=8'd1;
w_addr=3'd6;
r_addr=3'd4;
wr_en=0;
#10
d_in=8'd0;
w_addr=3'd7;
r_addr=3'd5;
wr_en=0;
#10
d_in=8'd5;
w_addr=3'd7;
r_addr=3'd1;
wr_en=1;
#10
d_in=8'd0;
w_addr=3'd2;
r_addr=3'd7;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long add(long long x, long long y) { x += y; while (x >= 998244353) x -= 998244353; while (x < 0) x += 998244353; return x; } long long mul(long long x, long long y) { return (x * 1ll * y) % 998244353; } long long binpow(long long x, long long y) { long long z = 1; while (y > 0) { if (y % 2 == 1) z = mul(z, x); x = mul(x, x); y /= 2; } return z; } long long inv(long long x) { return binpow(x, 998244353 - 2); } long long divide(long long x, long long y) { return mul(x, inv(y)); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, k; cin >> n >> k; vector<long long> a(k); for (long long i = 0; i < (long long)k; ++i) cin >> a[i]; vector<long long> last(n + 1, -1), fst(n + 1, k); for (long long i = 1; i <= k; i++) { last[a[i - 1]] = i; } for (long long i = k; i >= 1; i--) { fst[a[i - 1]] = i; } long long ans = 0; for (long long i = 1; i <= n; i++) { for (long long j = max(1ll, i - 1); j <= min(i + 1, n); j++) { if (j == i) { if (last[i] == -1) ans += 1; } else ans += (last[i] <= fst[j]); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename S, typename T> inline bool smin(S &l, T r) { return r < l ? l = r, 1 : 0; } template <typename S, typename T> inline bool smax(S &l, T r) { return l < r ? l = r, 1 : 0; } constexpr int MOD = 1e9 + 7; template <typename S> inline S mod(S &l) { return l = (l % MOD + MOD) % MOD; } template <typename S, typename T> inline S add(S &l, T r) { return mod(l += r); } void fileIO(string s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } constexpr int N = 1e5 + 10; constexpr int SQ = 780; int n, k; vector<int> vec[N]; int bias, dp[2][SQ], pd[2]; inline void input() { cin >> n >> k; for (int i = 0; i < k; i++) { int x, y; cin >> x >> y; vec[y].push_back(n - x + 1); } } inline void faze_0() { for (int i = 1; i < n + 1; i++) { sort(vec[i].begin(), vec[i].end()); while (vec[i].size() && vec[i].back() >= SQ - 2) { bias++; vec[i].pop_back(); } } } inline void faze_1() { memset(dp[0], 63, sizeof(dp)); dp[0][0] = 0; for (int i = 1; i < n + 1; i++) { int me = i & 1, num = 0; pd[me] = 1e9; for (int j = min(n - i + 1, SQ - 2); ~j; j--) { dp[me][j] = num * 3 + min(dp[me ^ 1][j + 1], pd[me ^ 1] + (j ? 2 : 0) + j * (j + 1) / 2); smin(pd[me], dp[me][j]); if (vec[i].size() && vec[i].back() == j) { num++; vec[i].pop_back(); } } } } int main() { input(); faze_0(); faze_1(); cout << 3 * bias + pd[n & 1] << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<int> e[200005], E[200005], v; int vis[200005]; inline void dfs(int u) { if (vis[u]) return; vis[u] = 1; v.push_back(u); int x = E[u][0], y = E[u][1]; if (e[x][0] == e[u][0] || e[x][0] == e[u][1] || e[x][1] == e[u][1] || e[x][1] == e[u][0]) dfs(x); dfs(y); } int main(int argc, char** argv) { int n; cin >> n; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; e[i].push_back(y); e[i].push_back(x); E[x].push_back(i); E[y].push_back(i); } dfs(1); for (int i = v.size() - 1; i >= 0; i--) cout << v[i] << ; return 0; } |
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 3
*/
// Testbench for behavioral model for the SIPO convertor
// Import the modules that will be tested for in this testbench
`include "sipo.v"
// IMPORTANT: To run this, try: ncverilog -f sipo.f +gui
module tb_sipo();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the SIPO convertor
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & out_valid output signals
wire [7:0] d_out;
wire valid_op;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// in_valid, clk, reset_b, & serial_in
reg ip_valid,clock,reset_low,serial_ip;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
SIPO sipo_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,valid_op,serial_ip,ip_valid,reset_low,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
reset_low=1'd0; // Reset
ip_valid=1'd1;
serial_ip=1'd1;
#9
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10 // Reset
reset_low=1'd0;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#8
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd0;
#10
reset_low=1'd1;
ip_valid=1'd0;
serial_ip=1'd1;
// New sequence...
#10
reset_low=1'd1;
ip_valid=1'd1;
serial_ip=1'd1;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2011-2012 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module ztex_ufm1_15d3 (fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1, wr_start_b2, reset_buf;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [351:0] inbuf, inbuf_tmp;
reg [95:0] outbuf;
reg [7:0] read_buf, write_buf;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce, nonce2, hash2;
miner253 m (
.clk(clk),
.reset(reset_buf),
.midstate(inbuf[351:96]),
.data(inbuf[95:0]),
.golden_nonce(golden_nonce),
.nonce2(nonce2),
.hash2(hash2)
);
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(4.0),
.CLKFX_MULTIPLY(32),
.CLKFXDV_DIVIDE(2),
.CLKIN_PERIOD(20.8333)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = write_buf;
assign pll_reset = pll_stop | ~dcm_locked | clk_reset | dcm_status[2];
always @ (posedge clk)
begin
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) )
begin
inbuf_tmp[351:344] <= read_buf;
inbuf_tmp[343:0] <= inbuf_tmp[351:8];
end;
inbuf <= inbuf_tmp; // due to TIG's
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { hash2, nonce2, golden_nonce };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[87:0] <= outbuf[95:8];
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
reset_buf <= reset;
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, t[100005]; int l1, l2; int dp[100005]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &t[i]); l1 = 1; l2 = 1; for (int i = 1; i <= n; ++i) { while (t[i] - t[l1] > 89) ++l1; while (t[i] - t[l2] > 1439) ++l2; dp[i] = 1e9; dp[i] = min(dp[i], dp[i - 1] + 20); dp[i] = min(dp[i], dp[l1 - 1] + 50); dp[i] = min(dp[i], dp[l2 - 1] + 120); } for (int i = 1; i <= n; ++i) printf( %d n , dp[i] - dp[i - 1]); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,sse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( fast-math ) using namespace std; const int INF = 1e9 + 9; const long long MAXN = 5e5 + 7; const long long MAXN1 = 21; const long long MAXN2 = 1e6 + 7; const long long MOD = 998244353; const long long PW = 31; const long long BLOCK = 447; void solve(); mt19937 mt(1e9 + 7); signed main() { srand( a + l + e + x + X + 5 + 1 + 2 ); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int q = 1; if (0) cin >> q; while (q--) solve(); } long long cnt[100]; struct Segment { long long sum, _sum, sum_, _sum_; int first, last, len; Segment() : sum(1), _sum(1), sum_(1), _sum_(1), first(0), last(0), len(1) {} Segment operator+(const Segment& other) const { Segment now; now.last = other.last; now.first = first; now.len = len + other.len; now.sum = (sum * other.sum % MOD + (last == 1 ? 1 : 0) * sum_ * cnt[last * 10 + other.first] % MOD * other._sum) % MOD; now._sum = (_sum * other.sum % MOD + (last == 1 && len > 1 ? 1 : 0) * _sum_ * cnt[last * 10 + other.first] % MOD * other._sum) % MOD; now.sum_ = (sum * other.sum_ % MOD + (last == 1 && other.len > 1 ? 1 : 0) * sum_ * cnt[last * 10 + other.first] % MOD * other._sum_) % MOD; now._sum_ = (_sum * other.sum_ % MOD + (last == 1 && other.len > 1 && len > 1 ? 1 : 0) * _sum_ * cnt[last * 10 + other.first] % MOD * other._sum_) % MOD; return now; } }; Segment v[4 * MAXN]; void upd(int vert, int tl, int tr, int id, int now) { if (tl == tr) { v[vert].sum = cnt[now]; v[vert].last = v[vert].first = now; return; } int tm = (tl + tr) / 2; if (id <= tm) upd(vert << 1, tl, tm, id, now); else upd(vert << 1 | 1, tm + 1, tr, id, now); v[vert] = v[vert << 1] + v[vert << 1 | 1]; } int get() { return v[1].sum; } void solve() { for (int i = 0; i < 10; ++i) { for (int j = 0; j < 10; ++j) { ++cnt[i + j]; } } int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) { char ch; cin >> ch; upd(1, 0, n - 1, i, ch - 0 ); } for (int i = 0; i < m; ++i) { int x, d; cin >> x >> d; upd(1, 0, n - 1, x - 1, d); cout << get() << n ; } } |
#include <bits/stdc++.h> using namespace std; int dist[2005][2005]; char f[2005][2005]; int n, m, r, c, x, y; int main() { scanf( %d%d%d%d%d%d , &n, &m, &r, &c, &x, &y); x = min(x, 10000000); y = min(y, 10000000); r--; c--; for (int i = 0; i < n; i++) scanf( %s , &f[i]); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) dist[i][j] = 1000000000; dist[r][c] = 0; deque<pair<int, pair<int, int> > > que; que.push_back(make_pair(0, make_pair(r, c))); while (!que.empty()) { pair<int, pair<int, int> > p = que.front(); que.pop_front(); if (p.first != dist[p.second.first][p.second.second]) continue; int X = p.second.first, Y = p.second.second; int dx[4] = {0, 1, 0, -1}; int dy[4] = {1, 0, -1, 0}; for (int k = 0; k < 4; k++) { int nx = X + dx[k], ny = Y + dy[k]; if (!(0 <= nx && nx < n && 0 <= ny && ny < m)) continue; if (f[nx][ny] == * ) continue; int add = (k == 2); if (dist[nx][ny] > p.first + add) { dist[nx][ny] = p.first + add; if (add == 0) que.push_front(make_pair(p.first + add, make_pair(nx, ny))); else que.push_back(make_pair(p.first + add, make_pair(nx, ny))); } } } int ans = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int mnx = dist[i][j]; int mny = j + dist[i][j] - c; if (mnx <= x && mny <= y) ans++; } cout << ans << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_2_V
`define SKY130_FD_SC_MS__O32AI_2_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32ai_2 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2005, M = 200005; struct node { int x, y; } d[N]; int h, w, n, mod = 1e9 + 7; long long c[M] = {1, 1}, inv[M] = {1, 1}, ni[M] = {1, 1}, f[N]; long long quick_mod(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % mod; b >>= 1; a = a * a % mod; } return ans; } void init() { for (int i = 2; i < M; i++) { c[i] = c[i - 1] * i % mod; ni[i] = (mod - mod / i) * ni[mod % i] % mod; inv[i] = ni[i] * inv[i - 1] % mod; } } long long C(int n, int m) { if (n < m) return 0; if (n == m || m == 0) return 1; return c[n] * inv[m] % mod * inv[n - m] % mod; } bool cmp(node a, node b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } int main() { init(); scanf( %d%d%d , &h, &w, &n); for (int i = 0; i < n; i++) scanf( %d%d , &d[i].x, &d[i].y); sort(d, d + n, cmp); d[n].x = h; d[n].y = w; for (int i = 0; i <= n; i++) { f[i] = C(d[i].x + d[i].y - 2, d[i].x - 1); for (int j = 0; j < i; j++) { if (d[j].x > d[i].x || d[j].y > d[i].y) continue; f[i] = (f[i] - f[j] * C(d[i].x - d[j].x + d[i].y - d[j].y, d[i].x - d[j].x)) % mod; } f[i] = (f[i] + mod) % mod; } printf( %lld n , f[n]); return 0; } |
`timescale 10ns/100ps
module testbench;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
reg clk;
reg rst;
reg [15:0] io_reg;
reg intr;
// Module instantiations
memory mem0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_o),
.wb_dat_o (mem_dat_i),
.wb_adr_i (adr),
.wb_we_i (we),
.wb_sel_i (sel),
.wb_stb_i (stb & !tga),
.wb_cyc_i (cyc & !tga),
.wb_ack_o (mem_ack)
);
cpu cpu0 (
.wb_clk_i (clk),
.wb_rst_i (rst),
.wb_dat_i (dat_i),
.wb_dat_o (dat_o),
.wb_adr_o (adr),
.wb_we_o (we),
.wb_tga_o (tga),
.wb_sel_o (sel),
.wb_stb_o (stb),
.wb_cyc_o (cyc),
.wb_ack_i (ack),
.wb_tgc_i (intr),
.wb_tgc_o (inta)
);
// Assignments
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = inta ? 16'd3 : (tga ? io_dat_i : mem_dat_i);
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
// Behaviour
// IO Stub
always @(posedge clk)
if (adr[15:1]==15'h5b && sel[1] && cyc && stb)
io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1]==15'h5c & sel[0] && cyc && stb)
io_reg[15:8] <= dat_o[7:0];
always #1 clk = ~clk;
initial
begin
intr <= 1'b0;
clk <= 1'b1;
rst <= 1'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
#1000 intr <= 1'b1;
@(posedge inta)
@(posedge clk) intr <= 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; int n; int fn[200005] = {}; int a, b, c; vector<string> st(t); for (int j = 0; j < t; j++) { cin >> n; int rn[n]; for (int i = 0; i < n; i++) { cin >> rn[i]; fn[rn[i]] = i + 1; } string s = 1 ; a = min(fn[1], fn[2]); b = max(fn[1], fn[2]); for (int i = 2; i <= n; i++) { c = fn[i]; if (a >= c) a = c; else if (b <= c) b = c; if (b - a == i - 1) s.insert(i - 1, 1 ); else s.insert(i - 1, 0 ); } st[j] = s; } for (int j = 0; j < t; j++) { cout << st[j] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9 + 7; const long long INF = 1e18 + 5; const long long maxn = 5e5 + 5; long long n = 100000000000, a[1555555], d[555555], mx = -1000000001; long long u[1511111], b[1100005], sum, cnt, t[555555]; long long bi(long long x, long long y) { if (y == 0) return 1ll; if (y == 1) return x; long long z = bi(x, y / 2); z = z * z % n; if (y & 1) z = z * x % n; return z % n; } pair<int, int> p[555555]; vector<pair<int, int> > v, x; int c[555555], l[555555], y[555555], k[555555]; long long dp[555555][3][3]; int main() { cin.tie(0); cout.tie(0); ios_base::sync_with_stdio(NULL); int n, x; cin >> n >> x; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= n; i++) for (int j = 0; j <= 2; j++) for (int k = 0; k <= 2; k++) dp[i][j][k] = -1e15; dp[0][0][0] = 0; for (int i = 1; i <= n; i++) for (int j = 0; j <= 2; j++) for (int k = 0; k <= 2; k++) { if (j > 0) dp[i][j][k] = max(dp[i][j][k], dp[i][j - 1][k]); if (k > 0) dp[i][j][k] = max(dp[i][j][k], dp[i][j][k - 1]); dp[i][j][k] = max(dp[i][j][k], dp[i - 1][j][k] + (j == 1 ? a[i] : 0) * (k == 1 ? x : 1)); } cout << dp[n][2][2]; return 0; } |
// File: JohnsonCount3_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Sep 5 07:53:06 2018
`timescale 1ns/10ps
module JohnsonCount3_TBV (
);
// myHDL -> Verilog Testbench for `UpDown_Counter` module
reg clk = 0;
reg rst = 0;
wire [3:0] q;
reg [1:0] Dir = 2'b10;
reg [3:0] JohnsonCount30_0_q_i = 0;
always @(rst, q, Dir, clk) begin: JOHNSONCOUNT3_TBV_PRINT_DATA
$write("%h", clk);
$write(" ");
$write("%h", rst);
$write(" ");
$write("%h", q);
$write(" ");
$write("%h", Dir);
$write("\n");
end
always @(posedge clk, negedge rst) begin: JOHNSONCOUNT3_TBV_JOHNSONCOUNT30_0_JCSTATEMACHINE
if (rst) begin
JohnsonCount30_0_q_i <= 0;
end
else if ((Dir == 2'b00)) begin
JohnsonCount30_0_q_i[4-1:1] <= JohnsonCount30_0_q_i[(4 - 1)-1:0];
JohnsonCount30_0_q_i[0] <= (!JohnsonCount30_0_q_i[(4 - 1)]);
end
else if ((Dir == 2'b01)) begin
JohnsonCount30_0_q_i <= JohnsonCount30_0_q_i;
end
else if ((Dir == 2'b10)) begin
JohnsonCount30_0_q_i[(4 - 1)-1:0] <= JohnsonCount30_0_q_i[4-1:1];
JohnsonCount30_0_q_i[(4 - 1)] <= (!JohnsonCount30_0_q_i[0]);
end
end
assign q = JohnsonCount30_0_q_i;
initial begin: JOHNSONCOUNT3_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: JOHNSONCOUNT3_TBV_STIMULES
integer i;
i = 0;
while (1'b1) begin
if ((i == ((2 * 2) * 4))) begin
Dir <= 2'b00;
end
else if ((i == ((4 * 2) * 4))) begin
rst <= 1;
end
else if ((i == (((4 * 2) * 4) + 1))) begin
rst <= 0;
end
else if ((i == (((4 * 2) * 4) + 2))) begin
Dir <= 2'b01;
end
else begin
// pass
end
if ((i == ((5 * 2) * 4))) begin
$finish;
end
i = i + 1;
@(posedge clk);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool chmin(int64_t& a, const int64_t& b) { return b < a ? a = b, 1 : 0; } bool chmax(int64_t& a, const int64_t& b) { return a < b ? a = b, 1 : 0; } constexpr int pct(int x) { return __builtin_popcount(x); } constexpr int bits(int x) { return 31 - __builtin_clz(x); } const int N = 1e6 + 1; int64_t binpow(int64_t a, int64_t b, int64_t m) { a %= m; long long res = 1; while (b > 0) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } void run_case() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; set<int> second, ans, prev; for (int i = 0; i < n; i++) { second.insert(a[i]); for (auto it : prev) { second.insert(a[i] | it); } prev.clear(); for (auto it : second) { prev.insert(it); ans.insert(it); } second.clear(); } cout << ans.size(); } auto clk = clock(); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; t = 1; while (t--) { run_case(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int number_of_players; cin >> number_of_players; int old_bid, counter; for (counter = 0; counter < number_of_players; counter++) { int bid; cin >> bid; while (bid % 2 == 0) bid /= 2; while (bid % 3 == 0) bid /= 3; if (counter == 0) old_bid = bid; else if (old_bid != bid) { cout << No << endl; break; } } if (counter == number_of_players) cout << Yes << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_BLACKBOX_V
`define SKY130_FD_SC_HD__SEDFXTP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_BLACKBOX_V
|
// Module: altera_tse_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma optimization_level 3 #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx ) using namespace std; const long double PI = 3.14159265358979323846; const long long mod = 1e+9 + 7; const int INFi = INT_MAX; const long long INF = (long long)1e+9 + 7; const int N = 1200300, LOGN = 30, V = N * LOGN; long long dx4[] = {0, 1, 0, -1}, dy4[] = {1, 0, -1, 0}; int t = 1; long long a, b, c, ans; string second; void MAIN() { cin >> a >> b >> c; ans = 0; ans = max(ans, a / 3 + b / 3 + c / 3); if (a > 0 && b > 0 && c > 0) ans = max(ans, 1 + (a - 1) / 3 + (b - 1) / 3 + (c - 1) / 3); if (a > 1 && b > 1 && c > 1) ans = max(ans, 2 + (a - 2) / 3 + (b - 2) / 3 + (c - 2) / 3); cout << ans << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed; cout << setprecision(10); ; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); ; while (t--) { MAIN(); } } |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: Alok:user:sample_generator:1.0
// IP Revision: 2
(* X_CORE_INFO = "sample_generator_v1_0,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "design_1_sample_generator_0_0,sample_generator_v1_0,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_sample_generator_0_0 (
FrameSize,
En,
AXI_En,
m_axis_tdata,
m_axis_tstrb,
m_axis_tlast,
m_axis_tvalid,
m_axis_tready,
m_axis_aclk,
m_axis_aresetn,
s_axis_tdata,
s_axis_tstrb,
s_axis_tlast,
s_axis_tvalid,
s_axis_tready,
s_axis_aclk,
s_axis_aresetn
);
input wire [7 : 0] FrameSize;
input wire En;
input wire AXI_En;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
output wire [31 : 0] m_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TSTRB" *)
output wire [3 : 0] m_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
output wire m_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
output wire m_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
input wire m_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXIS_CLK CLK" *)
input wire m_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 M_AXIS_RST RST" *)
input wire m_axis_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
input wire [31 : 0] s_axis_tdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TSTRB" *)
input wire [3 : 0] s_axis_tstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TLAST" *)
input wire s_axis_tlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
input wire s_axis_tvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
output wire s_axis_tready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXIS_CLK CLK" *)
input wire s_axis_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S_AXIS_RST RST" *)
input wire s_axis_aresetn;
sample_generator_v1_0 #(
.C_M_AXIS_TDATA_WIDTH(32), // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
.C_M_AXIS_START_COUNT(32), // Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
.C_S_AXIS_TDATA_WIDTH(32) // AXI4Stream sink: Data Width
) inst (
.FrameSize(FrameSize),
.En(En),
.AXI_En(AXI_En),
.m_axis_tdata(m_axis_tdata),
.m_axis_tstrb(m_axis_tstrb),
.m_axis_tlast(m_axis_tlast),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.s_axis_tdata(s_axis_tdata),
.s_axis_tstrb(s_axis_tstrb),
.s_axis_tlast(s_axis_tlast),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; char str[10000]; int n, m, Q; map<string, int> mem; map<string, int>::iterator iter; struct Func { string name; int num; int v[10]; bool operator==(const Func& A) const { if (name != A.name) return false; if (num != A.num) return false; for (int i = 0; i < num; ++i) if (v[i] * A.v[i] != 0 && v[i] != A.v[i]) return false; return true; } } g[2000], pre; int Type(string x) { if (x == T ) return 0; if (x == int ) return 1; if (x == double ) return 2; if (x == string ) return 3; return -1; } void inputFunc(int gs) { gets(str); int i = 0, j = 0, len = strlen(str); while (str[j] != d ) ++j; ++j; while (j < len) { if (str[j] != ) str[i++] = str[j]; j++; } len = i; i = 0; g[gs].name = ; while (str[i] != ( ) { g[gs].name += str[i]; i++; } string temp = ; i++; for (;;) { if (str[i] == , || str[i] == ) ) { g[gs].v[g[gs].num++] = Type(temp); temp = ; if (str[i] == ) ) break; } else temp += str[i]; i++; } } void inputType() { string a, b; cin >> a >> b; mem[b] = Type(a); } void solve() { gets(str); int i = 0, j = 0, len = strlen(str); for (j = 0; j < len; ++j) { if (str[j] != ) str[i++] = str[j]; } len = i; i = 0; pre.name = ; pre.num = 0; while (str[i] != ( ) { pre.name += str[i]; i++; } string temp = ; i++; for (;;) { if (str[i] == , || str[i] == ) ) { pre.v[pre.num++] = mem.find(temp)->second; temp = ; if (str[i] == ) ) break; } else temp += str[i]; i++; } int ans = 0; for (int i = 0; i < n; ++i) if (pre == g[i]) ++ans; printf( %d n , ans); } int main() { scanf( %d , &n); gets(str); for (int i = 0; i < n; ++i) inputFunc(i); scanf( %d , &m); gets(str); mem.clear(); while (m--) inputType(); scanf( %d , &Q); gets(str); while (Q--) solve(); } |
module debounce_pulse(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in==0)
next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debouncer_pulse
|
#include <bits/stdc++.h> const int oo = 0x3f3f3f3f; template <typename T> inline bool chkmax(T &a, T b) { return a < b ? a = b, true : false; } template <typename T> inline bool chkmin(T &a, T b) { return a > b ? a = b, true : false; } template <typename T> T read(T &first) { int f = 1; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (first = 0; isdigit(ch); ch = getchar()) first = 10 * first + ch - 0 ; return first *= f; } template <typename T> void write(T first) { if (first < 0) { putchar( - ); first = -first; } static char s[20]; int top = 0; for (; first; first /= 10) s[++top] = first % 10 + 0 ; if (top == 0) putchar( 0 ); else while (top) putchar(s[top--]); } const int MAXN = 1e5 + 5, MAXK = 6; struct Line { int a, b, c; int id; bool on(const std::pair<double, double> &p) { static double EPS = 1e-8; return std::fabs(a * p.first + b * p.second + c) < EPS; } }; int N, K; Line A[MAXN]; std::pair<int, int> ans[MAXN]; int anssize; int st[MAXN]; inline bool intersection(const Line &a, const Line &b, std::pair<double, double> &p) { long long d = (long long)a.b * b.a - (long long)b.b * a.a; if (d == 0) return false; p.first = (double)((long long)b.b * a.c - (long long)a.b * b.c) / d; p.second = (double)((long long)b.c * a.a - (long long)a.c * b.a) / d; return true; } bool dfs(int n, int k) { if (n <= k) { for (int i = 0; i < n; ++i) { ans[anssize++] = std::make_pair(A[i].id + 1, -1); } return true; } if (k == 0) return false; for (int i = n - k - 1; i < n; ++i) { for (int j = i + 1; j < n; ++j) { std::pair<double, double> p; if (intersection(A[i], A[j], p) == false) continue; ans[anssize++] = std::make_pair(A[i].id + 1, A[j].id + 1); int m = n, top = 0; for (int k = n - 1; k >= 0; --k) { if (A[k].on(p)) { st[++top] = k; std::swap(A[k], A[--m]); } } if (dfs(m, k - 1) == true) return true; --anssize; while (top > 0) { std::swap(A[st[top--]], A[m++]); } } } return false; } void input() { read(N); read(K); for (int i = 0; i < N; ++i) { read(A[i].a); read(A[i].b); read(A[i].c); A[i].id = i; } } void solve() { srand(time(NULL)); if (N >= 5 * K * K) { int times = 100; while (times-- && N > 0 && K > 0) { int i = rand() % N; int j = rand() % N; std::pair<double, double> p; if (i == j || intersection(A[i], A[j], p) == false) continue; int top = 0; for (int k = N - 1; k >= 0; --k) { if (A[k].on(p)) st[++top] = k; } if (top > K) { ans[anssize++] = std::make_pair(A[i].id + 1, A[j].id + 1); for (int k = 1; k <= top; ++k) { A[st[k]] = A[--N]; } --K; break; } } } bool haveAns = dfs(N, K); if (haveAns) { puts( YES ); write(anssize); putchar( n ); for (int i = 0; i < anssize; ++i) { write(ans[i].first); putchar( ); write(ans[i].second); putchar( n ); } } else puts( NO ); } int main() { input(); solve(); return 0; } |
`timescale 1 ns / 1 ps
module multiply_accumulate_behavioural #
(
// signal width definitions
parameter integer DATA_WIDTH = 16,
parameter integer COEFFICIENT_WIDTH = 16,
parameter integer CARRY_WIDTH = 48,
parameter integer OUTPUT_OFFSET = 0,
// operation definitions
parameter integer DATA_IN_NUMBER_REGS = 1,
parameter integer COEFFICIENTS_NUMBER_REGS = 1,
parameter integer USE_SILICON_CARRY = 1,
parameter integer FIRST_IN_CHAIN = 0,
parameter integer LAST_IN_CHAIN = 0,
parameter integer CARRY_NUMBER_REGS = 1
)
(
// global signals
input wire clock,
input wire reset,
// data signals
input wire [DATA_WIDTH-1:0] data_in,
input wire [COEFFICIENT_WIDTH-1:0] coefficient_in,
input wire [CARRY_WIDTH-1:0] carry_in,
output wire [CARRY_WIDTH-1:0] carry_out,
output wire [DATA_WIDTH-1:0] data_carry,
output wire [DATA_WIDTH-1:0] data_out,
// control signals
input wire ce_calculate,
input wire ce_coefficient,
input wire reset_coefficient,
input wire [6:0] op_mode,
input wire [4:0] in_mode
);
// register to store the coefficient
reg [COEFFICIENT_WIDTH-1:0] coefficient_register;
// store the coefficient
always @(posedge clock) begin
if (reset_coefficient) begin
coefficient_register <= 0;
end
else begin
if (reset_coefficient) begin
coefficient_register <= 0;
end
else if (ce_coefficient) begin
coefficient_register <= coefficient_in;
end
else begin
coefficient_register <= coefficient_register;
end
end
end
// register to store the data
reg [DATA_WIDTH-1:0] data_in_register[DATA_IN_NUMBER_REGS-1:0];
wire [DATA_WIDTH-1:0] data_in_internal;
integer i_data;
always @(posedge clock) begin
if (reset) begin
for (i_data = 0; i_data < DATA_IN_NUMBER_REGS; i_data=i_data+1) begin
data_in_register[i_data] <= 0;
end
end
else begin
if (ce_calculate) begin
data_in_register[0] <= data_in;
for (i_data = 1; i_data < DATA_IN_NUMBER_REGS; i_data=i_data+1) begin
data_in_register[i_data] <= data_in_register[i_data-1];
end
end
end
end
// tap off the end of the shift register delay line and use it internally and pass it outside
assign data_in_internal = data_in_register[DATA_IN_NUMBER_REGS-1];
assign data_carry = data_in_internal;
// register internal value before MAC operation
reg [DATA_WIDTH-1:0] data_in_internal_delay;
always @(posedge clock) begin
if (reset) begin
data_in_internal_delay <= 0;
end
else begin
if (ce_calculate) begin
data_in_internal_delay <= data_in_internal;
end
end
end
// perform the core multiply and accumalate operation
reg [CARRY_WIDTH-1:0] mac_value;
always @(posedge clock) begin
if (reset) begin
mac_value <= 0;
end
else begin
if (ce_calculate) begin
mac_value <= $signed(coefficient_register) * $signed(data_in_internal_delay) + $signed(carry_in);
end
end
end
// output the trimmed and full precision outputs
assign carry_out = mac_value;
assign data_out = mac_value[2*DATA_WIDTH-2-1:DATA_WIDTH-2];
// used to create the GTKwave dump file
`ifdef COCOTB_SIM
initial begin
$dumpfile ("waveform.vcd");
$dumpvars (0, multiply_accumulate_behavioural);
#1;
end
`endif
endmodule |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the pipe
module pipeline_buffer (in,out,clock,reset);
// Output signal for the design module
output out; // Output data signal
// Input signals for the design module
input in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg out;
reg o1; // Output of flip-flop #1
reg o2; // Output of flip-flop #2
reg o3; // Output of flip-flop #3
reg o4; // Output of flip-flop #4
reg o5; // Output of flip-flop #5
reg o6; // Output of flip-flop #6
reg o7; // Output of flip-flop #7
reg o8; // Output of flip-flop #8
reg o9; // Output of flip-flop #9
reg o10; // Output of flip-flop #10
reg o11; // Output of flip-flop #11
reg o12; // Output of flip-flop #12
reg o13; // Output of flip-flop #13
reg o14; // Output of flip-flop #14
reg o15; // Output of flip-flop #15
reg o16; // Output of flip-flop #16
reg o17; // Output of flip-flop #17
reg o18; // Output of flip-flop #18
reg o19; // Output of flip-flop #19
reg o20; // Output of flip-flop #20
reg o21; // Output of flip-flop #21
reg o22; // Output of flip-flop #22
reg o23; // Output of flip-flop #23
reg o24; // Output of flip-flop #24
reg o25; // Output of flip-flop #25
reg o26; // Output of flip-flop #26
reg o27; // Output of flip-flop #27
reg o28; // Output of flip-flop #28
reg o29; // Output of flip-flop #29
reg o30; // Output of flip-flop #30
reg o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 1'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 1'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 1'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 1'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 1'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 1'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 1'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 1'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 1'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 1'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 1'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 1'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 1'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 1'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 1'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 1'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 1'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 1'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 1'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 1'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 1'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 1'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 1'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 1'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 1'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 1'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 1'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 1'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 1'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 1'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 1'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 1'd0;
else
out = o31;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog wrapper for tapvpwrvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvpwrvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvpwrvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__tapvpwrvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__probec_p (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBEC_P_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; char s[200005], s1[200005]; void sol() { int i, l, xp; l = strlen(s); memset(s1, 0, sizeof(s1)); xp = -1; for (i = 0; i < l; i++) { if (xp == -1) { xp++; s1[xp] = s[i]; continue; } if (s1[xp] == s[i]) xp--; else { xp++; s1[xp] = s[i]; } } xp++; s1[xp] = 0; printf( %s n , s1); } int main() { while (gets(s)) sol(); return 0; } |
#include <bits/stdc++.h> using namespace std; int num[300005][2]; int jichu = 100000; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, x; cin >> n >> m; if (n == 1) { cout << 0 << endl; return 0; } long long cont = 0, sum = n; for (int i = 1; i <= n; i++) { num[jichu + i][0] = 1; num[jichu + i][1] = 1; } for (int i = 1; i <= m; i++) { cin >> x; int l = x - i, r = x + i; if (num[jichu + l][1] > 0) { cont += 1LL * num[jichu + l][1]; num[jichu + l - 1][1] += num[jichu + l][1]; num[jichu + l][1] = 0; } if (num[jichu + r][0] > 0) { cont += 1LL * num[jichu + r][0]; num[jichu + r + 1][0] += num[jichu + r][0]; num[jichu + r][0] = 0; } } for (int i = jichu + 1 - m; i < jichu + n; i++) { if (i + m + 1 > jichu + n) { sum += 1LL * num[i][1] * ((m + 1) - (i + m + 1 - jichu - n)); } else { sum += 1LL * num[i][1] * (m + 1); } } for (int i = jichu + 2; i <= jichu + n + m; i++) { if (i <= jichu + m + 1) { sum += 1LL * num[i][0] * (i - jichu - 1); } else { sum += 1LL * num[i][0] * (m + 1); } } sum -= cont; cout << sum << endl; return 0; } |
/*
Basic fifo
Copyright 2005, Timothy Miller
Updated 2012 by Per Lenander & Anton Fosselius (ORSoC)
- basic fifo is no longer of a fixed depth
This file is part of orgfx.
orgfx is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
orgfx is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with orgfx. If not, see <http://www.gnu.org/licenses/>.
*/
module basic_fifo(
clk_i,
rst_i,
data_i,
enq_i,
full_o,
count_o,
data_o,
valid_o,
deq_i
);
parameter fifo_width = 32;
parameter fifo_bit_depth = 6;
input clk_i, rst_i;
input [fifo_width-1:0] data_i;
input enq_i;
output full_o;
output reg [fifo_bit_depth:0] count_o;
output reg [fifo_width-1:0] data_o;
output reg valid_o;
input deq_i;
reg [fifo_width-1:0] fifo_data [2**(fifo_bit_depth)-1:0];
reg [fifo_bit_depth:0] fifo_head, fifo_tail;
reg [fifo_bit_depth:0] next_tail;
// accept input
wire next_full = fifo_head[fifo_bit_depth-1:0] == next_tail[fifo_bit_depth-1:0] &&
fifo_head[fifo_bit_depth] != next_tail[fifo_bit_depth];
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
fifo_tail <= 1'b0;
next_tail <= 1'b1;
end
else if (!next_full && enq_i)
begin
// We can only enqueue when not full
fifo_data[fifo_tail[fifo_bit_depth-1:0]] <= data_i;
next_tail <= next_tail + 1'b1;
fifo_tail <= next_tail;
end
assign full_o = next_full;
always @(posedge clk_i or posedge rst_i)
if(rst_i)
count_o <= 1'b0;
else if(enq_i & ~deq_i & ~next_full)
count_o <= count_o + 1'b1;
else if(~enq_i & deq_i & valid_o)
count_o <= count_o - 1'b1;
// provide output
wire is_empty = (fifo_head == fifo_tail);
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
valid_o <= 1'b0;
fifo_head <= 1'b0;
end
else
begin
if (!is_empty)
begin
if (!valid_o || deq_i)
fifo_head <= fifo_head + 1'b1;
valid_o <= 1'b1;
end
else if (deq_i)
valid_o <= 1'b0;
end
always @(posedge clk_i)
// If no valid out or we're dequeueing, we want to grab
// the next data. If we're empty, we don't get valid_o,
// so we don't care if it's garbage.
if (!valid_o || deq_i)
data_o <= fifo_data[fifo_head[fifo_bit_depth-1:0]];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; int main() { cin >> n; if (n == 1) cout << -1; else cout << n << << n + 1 << << n * (n + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long moves = 0; for (long long i = 0; i < n; i++) { if (a[i] < 1) { moves = moves + (i + 1) - a[i]; } else if (a[i] > n) { moves = moves + (a[i] - (i + 1)); } else if (a[i] > (i + 1)) { moves = moves + (a[i] - (i + 1)); } else { moves = moves + (i + 1 - a[i]); } } cout << moves; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { solve(); cout << n ; } cerr << time taken: << (float)clock() / CLOCKS_PER_SEC << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 41; const int MASK = 1 << 21; long long sz[MAX_N], par[MAX_N], po2[MAX_N], vis[MAX_N]; long long dp[MASK]; vector<int> adj[MAX_N]; int rt(int v) { return v ^ par[v] ? par[v] = rt(par[v]) : v; } void join(int u, int v) { if ((u = rt(u)) != (v = rt(v))) { par[v] = u, sz[u] += sz[v]; } } int main() { int n, m; cin >> n >> m; if (m < 3) { cout << 0 << endl; return 0; } po2[0] = 1; for (int i = 0; i < n; i++) par[i] = i, sz[i] = 1; for (int i = 1; i < n + 1; i++) po2[i] = po2[i - 1] * 2ll; long long ans = po2[n]; for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--, b--; join(a, b); adj[a].push_back(b); adj[b].push_back(a); } set<long long> s; long long num = 0; for (int i = 0; i < n; i++) { s.insert(rt(i)); if (sz[rt(i)] == 1) num++; } ans += po2[num + 1] - po2[s.size()]; bool imposs = false; for (int i = 0; i < n; i++) { if (vis[i]) continue; queue<pair<int, int> > q; q.push({i, 1}); while (q.size()) { pair<int, int> curr = q.front(); q.pop(); if (vis[curr.first]) { if (vis[curr.first] != curr.second) { imposs = true; break; } else continue; } vis[curr.first] = curr.second; for (int next : adj[curr.first]) q.push({next, curr.second ^ 3}); } if (imposs) break; } if (!imposs) ans += po2[s.size()]; num = 0; for (int mask = 0; mask < 1 << ((n + 1) / 2); mask++) { bool nowork = false; long long new_mask = (1 << (n / 2)) - 1; for (int k = 0; k < (n + 1) / 2; k++) { if (!(mask & (1 << k))) continue; for (int nxt : adj[2 * k]) { if (nxt & 1) new_mask &= (1 << (n / 2)) - (1 << (nxt / 2)) - 1; else nowork = nowork || (mask & (1 << (nxt / 2))); } } if (!nowork) dp[new_mask]++; } for (int i = 0; i < n / 2; i++) for (int mask = 0; mask < 1 << (n / 2); mask++) if (mask != (mask | (1 << i))) dp[mask] += dp[mask | (1 << i)]; for (int mask = 0; mask < 1 << (n / 2); mask++) { bool nowork = false; for (int k = 0; k < n / 2; k++) { if (!(mask & (1 << k))) continue; for (long long nxt : adj[2 * k + 1]) { if (nxt & 1 && mask & (1 << (nxt / 2))) nowork = true; } } if (!nowork) num += dp[mask]; } ans -= 2ll * num; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int x, q; vector<int> adj[205]; bool visited[205]; void dfs(int n) { visited[n] = 1; for (int i = 0; i < adj[n].size(); i++) { if (!visited[adj[n][i]]) { visited[adj[n][i]] = 1; dfs(adj[n][i]); } } } int main() { int n, m; cin >> n >> m; bool flag = 0; for (int i = m + 1; i <= n + m; i++) { cin >> q; while (q--) { cin >> x; if (x) { flag = 1; } adj[i].push_back(x); adj[x].push_back(i); } } if (!flag) { cout << n << endl; return 0; } int ans = -1; for (int i = m + 1; i <= n + m; i++) { if (!visited[i]) { dfs(i); ans++; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; long long inf = 2e18; long long mod = 1e6; const long long M = 1e5; string s; long long a[M]; long long bmm(long long a, long long b) { if (b == 0) return a; return bmm(b, a % b); } int main() { long long n; cin >> n; string s = ; for (long long i = 0; i < n; i++) { cin >> a[i]; s += ? ; } long long su = 0; for (long long i = n - 1; i > -1; i--) { if (su > 0) { s[i] = - ; su -= a[i]; } else { s[i] = + ; su += a[i]; } } if (su < 0) for (long long i = 0; i < n; i++) if (s[i] == + ) s[i] = - ; else s[i] = + ; cout << s; } |
/*
* pll_led.v: Example program working in simulation as well as on real hardware. Tested on Digilent Basys 3.
* author: Till Mahlburg
* year: 2019
* organization: Universität Leipzig
* license: ISC
*
*/
`timescale 1 ns / 1 ps
module pll_led #(
parameter FF_NUM = 25) (
input clk,
input RST,
output [6:0] led);
/* divide the output signal, so one can see the results at the LEDs */
wire [3:0] pll_out;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : generate_div
divider_synth #(
.FF_NUM(FF_NUM)) div (
.clk_in(pll_out[i]),
.RST(RST),
.clk_out(led[i+1]));
end
endgenerate
wire CLKFB;
/* More information about the instantiiation can be found in Xilinx UG953 509ff. */
PLLE2_BASE #(
.CLKFBOUT_MULT(8),
.CLKFBOUT_PHASE(90.0),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(64),
.CLKOUT2_DIVIDE(32),
.CLKOUT3_DIVIDE(16),
.CLKOUT4_DIVIDE(128),
.CLKOUT5_DIVIDE(128),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.9),
.CLKOUT5_DUTY_CYCLE(0.1),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.DIVCLK_DIVIDE(1))
pll (
.CLKOUT0(pll_out[0]),
.CLKOUT1(pll_out[1]),
.CLKOUT2(pll_out[2]),
.CLKOUT3(pll_out[3]),
.CLKOUT4(led[5]),
.CLKOUT5(led[6]),
.CLKFBOUT(CLKFB),
.LOCKED(led[0]),
.CLKIN1(clk),
.PWRDWN(0),
.RST(RST),
.CLKFBIN(CLKFB));
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// DCFIFO_64x16_DR for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: Dual clock distributed ram FIFO (64 width, 16 depth) wrapper
// Module Name: DCFIFO_64x16_DR
// File Name: DCFIFO_64x16_DR.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DCFIFO_64x16_DR
(
input iWClock ,
input iWReset ,
input [63:0] iPushData ,
input iPushEnable ,
output oIsFull ,
input iRClock ,
input iRReset ,
output [63:0] oPopData ,
input iPopEnable ,
output oIsEmpty
);
DPBDCFIFO64x16DR
Inst_DPBDCFIFO64x16DR
(
.wr_clk (iWClock ),
.wr_rst (iWReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.rd_clk (iRClock ),
.rd_rst (iRReset ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char z[500005]; int Qs1[500005], b, Qs2[500005]; int f(char a) { if (a == w ) return b + 1; return 1; } int main() { int i, j, n, a, t, Max = 0; int *qs2 = Qs2 + 1, *qs1 = Qs1 + 1; scanf( %d %d %d %d , &n, &a, &b, &t); gets(z); qs1[0] = f(z[0]); for (i = 1; i < n; i++) { qs1[i] = a + f(z[i]) + qs1[i - 1]; } for (i = n - 1; i >= 0; i--) { qs2[n - 1 - i] = a + f(z[i]) + qs2[n - 2 - i]; } for (i = 0; i < n; i++) { if (qs1[i] <= t) Max = max(min(i + 1, n), Max); if (qs2[i] + qs1[0] <= t) Max = max(min(i + 2, n), Max); } for (i = 0; i < n; i++) { int tmp = lower_bound(qs2, qs2 + n, t - qs1[i] - a * i) - qs2; if (t - qs1[i] - a * i < qs2[tmp]) tmp--; if (tmp == -1) continue; Max = max(min(tmp + i + 2, n), Max); } for (i = 0; i < n; i++) { int tmp = lower_bound(qs1, qs1 + n, t - qs2[i] - a * i - a) - qs1; if (t - qs2[i] - a * i - a < qs1[tmp]) tmp--; if (tmp == -1) continue; Max = max(min(tmp + i + 2, n), Max); } printf( %d , Max); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200100; struct seat { int w, id; bool operator<(const seat& st) const { return w < st.w; } bool operator>(const seat& st) const { return w > st.w; } }; seat st[maxn]; int n; char tp[maxn * 2]; int main() { while (scanf( %d , &n) == 1) { for (int i = 1; i <= n; i++) { scanf( %d , &st[i].w); st[i].id = i; } scanf( %s , tp); sort(st + 1, st + 1 + n); priority_queue<seat, vector<seat>, less<seat>> que; int cnt = 1; for (int i = 0; i < n * 2; i++) { if (tp[i] == 0 ) { printf( %d , st[cnt].id); que.push(st[cnt]); cnt++; } else { printf( %d , que.top().id); que.pop(); } } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, a, b, i, a1, b1, y, y1, ans, ans1, ans2, x; cin >> n >> a >> b; for (i = 1; i <= n; i++) { cin >> x; y = x * a; ans = y % b; if (a != 0) cout << ans / a << ; else cout << x << ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:35 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: global_logic.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// GLOBAL_LOGIC
//
//
// Description: The GLOBAL_LOGIC module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 2-byte lane designs
//
`timescale 1 ns / 10 ps
module aurora_201_GLOBAL_LOGIC
(
// GTP Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR
);
`define DLY #1
//***********************************Port Declarations*******************************
// GTP Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input SOFT_ERROR;
input LANE_UP;
input HARD_ERROR;
input CHANNEL_BOND_LOAD;
input [0:1] GOT_A;
input GOT_V;
output GEN_A;
output [0:1] GEN_K;
output [0:1] GEN_R;
output [0:1] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
aurora_201_CHANNEL_INIT_SM channel_init_sm_i
(
// GTP Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
aurora_201_IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
aurora_201_CHANNEL_ERROR_DETECT channel_error_detect_i
(
// Aurora Lane Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERROR(CHANNEL_SOFT_ERROR),
.CHANNEL_HARD_ERROR(CHANNEL_HARD_ERROR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of continuous assignment.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`define SUPPORT_REAL_NETS_IN_IVTEST
`endif
module top;
wire [1:0] array1[2:1];
wire [1:0] array2[1:0];
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[0] = 2'd0;
`endif
assign array1[1] = 2'd1;
assign array1[2] = 2'd2;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[3] = 2'd3;
`endif
assign array2[0] = 2'd0;
assign array2[1] = 2'd1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array2['bx] = 2'd2;
`endif
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
wire real array3[2:1];
wire real array4[1:0];
assign array3[0] = 0.0;
assign array3[1] = 1.0;
assign array3[2] = 2.0;
assign array3[3] = 3.0;
assign array4[0] = 0.0;
assign array4[1] = 1.0;
assign array4['bx] = 2.0;
`endif
reg failed;
initial begin
#1 failed = 0;
$display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd1) || (array1[2] !== 2'd2)) failed = 1;
$display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2'd0) || (array2[1] !== 2'd1)) failed = 1;
`ifdef SUPPORT_REAL_NETS_IN_IVTEST
$display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 2.0)) failed = 1;
$display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 1.0)) failed = 1;
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> const int MAXN = 2000 + 10; int n; char s[MAXN]; struct Bitset { static const int SIZE = 2048 / 64; unsigned long long a[SIZE]; int cnt; int high; Bitset() { memset(a, 0, sizeof a); cnt = 0; high = 0; } inline bool at(int x) { return (a[x >> 6] >> (x & 63)) & 1; } inline void setone(int x) { cnt += !at(x); high = std::max(high, x >> 6); a[x >> 6] |= (1ull << (x & 63)); } inline int count() const { return cnt; } void operator^=(const Bitset &rhs) { cnt = 0; high = std::max(high, rhs.high); for (int i = 0; i <= high; i++) { a[i] ^= rhs.a[i]; cnt += __builtin_popcountll(a[i]); } } }; Bitset a[MAXN], b[MAXN]; Bitset x; void insert(int cur) { Bitset ans; ans.setone(cur); for (register int j = 2000; j >= 0; j--) { if (!x.at(j)) continue; if (b[j].count() == 0) { puts( 0 ); std::swap(a[j], x); std::swap(b[j], ans); return; } ans ^= b[j]; x ^= a[j]; if (x.count() == 0) break; } printf( %d , ans.count() - 1); for (int i = 1; i < cur; i++) { if (ans.at(i)) { printf( %d , i - 1); } } printf( n ); } Bitset to_binary() { int n = strlen(s + 1); static int num[MAXN]; std::reverse(s + 1, s + n + 1); const int B = 8; int cnt = 1, p = 1; for (int i = 1; i <= n; i++) { num[cnt] += (s[i] - 0 ) * p; p *= 10; if (i % B == 0) { cnt++; p = 1; } } int cur = 0; Bitset ans; if (num[cnt] == 0) cnt--; n = cnt; while (n) { if (num[1] & 1) ans.setone(cur); cur++; int res = 0; for (int i = n; i >= 1; i--) { num[i] += res * 100000000; res = num[i] % 2; num[i] /= 2; } while (n > 0 && num[n] == 0) n--; } return ans; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); x = to_binary(); insert(i); } } |
#include <bits/stdc++.h> using namespace std; long long fa[400005], iv[400005]; pair<long long, long long> p[2005]; long long dp[2005]; long long pw(long long bs, long long x) { long long ans = 1; while (x) { if (x & 1) ans = ans * bs % 1000000007; bs = bs * bs % 1000000007; x /= 2; } return ans % 1000000007; } void init() { fa[0] = iv[0] = 1; for (int i = 1; i <= 400000; i++) { fa[i] = fa[i - 1] * i % 1000000007; iv[i] = pw(fa[i], 1000000007 - 2) % 1000000007; } } long long cal(long long n, long long m) { if (m > n) return 0; long long ans = fa[n] % 1000000007; ans = (ans * iv[m] % 1000000007) * iv[n - m] % 1000000007; return ans; } long long lu(long long n, long long m) { if (m == 0) return 1; return cal(n % 1000000007, m % 1000000007) * lu(n / 1000000007, m / 1000000007) % 1000000007; } int main() { init(); long long n, m, k; cin >> n >> m >> k; n--; m--; for (int i = 0; i < k; i++) { cin >> p[i].first >> p[i].second; p[i].first--; p[i].second--; } sort(p, p + k); p[k].first = n; p[k].second = m; for (int i = 0; i <= k; i++) { long long sum = 0; for (int j = 0; j < i; j++) { long long x = p[i].first - p[j].first, y = p[i].second - p[j].second; if (x < 0 || y < 0) continue; sum = (sum + lu(x + y, x) * dp[j] % 1000000007) % 1000000007; } dp[i] = (cal(p[i].first + p[i].second, p[i].first) - sum + 1000000007) % 1000000007; } cout << dp[k] % 1000000007 << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100010; int n, m; int low[maxn], dfn[maxn], v[maxn << 1], A[maxn]; int nxt[maxn << 1], head[maxn], belong[maxn], a[maxn], vis[maxn << 1]; stack<int> s; int indexs = 0, cnt = 0; int ans = 0; void add_edge(int x, int y) { static int N = 1; N++; v[N] = y; nxt[N] = head[x]; head[x] = N; } void tarjan(int x, int fa) { dfn[x] = low[x] = ++indexs; for (int i = head[x]; i != -1; i = nxt[i]) { if (vis[i]) continue; vis[i] = vis[i ^ 1] = 1; s.push(i); if (!dfn[v[i]]) { tarjan(v[i], x); low[x] = min(low[x], low[v[i]]); if (low[v[i]] >= dfn[x]) { cnt++; int num = 0, bcnt = 0; while (1) { int tmp = s.top(); s.pop(); if (belong[v[tmp]] != cnt) belong[v[tmp]] = cnt, num++; if (belong[v[tmp ^ 1]] != cnt) belong[v[tmp ^ 1]] = cnt, num++; a[++bcnt] = tmp; if (tmp == i) break; } if (num == bcnt) for (int i = 1; i <= bcnt; i++) A[++ans] = a[i]; } } else low[x] = min(low[x], dfn[v[i]]); } } int main() { memset(head, -1, sizeof(head)); scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); add_edge(x, y); add_edge(y, x); } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i, 0); sort(A + 1, A + 1 + ans); printf( %d n , ans); for (int i = 1; i <= ans; i++) cout << (A[i] >> 1) << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, dad[200000 + 1], u[200000 + 1], v[200000 + 1]; long long w[200000], pop[200000], initsum, S; std::vector<int> adjl[200000 + 1]; int cnode(int node, int ed) { return node ^ u[ed] ^ v[ed]; } void dfs(int u) { int isleaf = 1; if (u != 1) pop[dad[u]] = 0; for (int ed : adjl[u]) if (ed != dad[u]) { isleaf = 0; int v = cnode(u, ed); dad[v] = ed; dfs(v); initsum += w[ed] * pop[ed]; if (u != 1) pop[dad[u]] += pop[ed]; } if (isleaf) pop[dad[u]] = 1; } struct good_cmp { bool operator()(int l, int r) { return pop[l] * ((w[l] + 1) / 2) < pop[r] * ((w[r] + 1) / 2); } }; void run() { cin >> n >> S; for (int i = 1; i <= n; ++i) adjl[i].clear(); for (int i = 1; i < n; ++i) { cin >> u[i] >> v[i] >> w[i]; adjl[u[i]].emplace_back(i); adjl[v[i]].emplace_back(i); } initsum = 0; memset(dad + 1, 0, n * sizeof(int)); dad[1] = -1; dfs(1); std::priority_queue<int, std::vector<int>, good_cmp> pq; for (int i = 1; i < n; ++i) pq.push(i); long long ans = 0; while (initsum > S) { ++ans; int top = pq.top(); pq.pop(); initsum -= pop[top] * ((w[top] + 1) / 2); w[top] /= 2; pq.push(top); } cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); int t; cin >> t; while (t--) run(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, t1, p; int b[200000], h[200000]; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> b[i]; if (!b[i]) { --i; --n; } } for (int i = 0; i < n; i++) { cin >> h[i]; if (h[i] == b[0]) p = i; if (!h[i]) --i; } for (int i = 0; i < n; i++) { if (b[i] != h[(p + i) % (n)]) { cout << NO << endl; exit(0); } } cout << YES << endl; } |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC16 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* Last two bytes of the data
* CCCCCCCCCCCCCCCC
* C = CRC bit
*
* Hold in reset when not using
*
* Online documentation is way to fucking complicated
* x^16 + x^12 + x^5 + 1
* To find the polynomial remove the top x^16 then add 2^12 + 2^5 + 1 = 0x1021
*
*
* Changes:
* 2015.08.08: Initial Add
*
*/
module crc16 #(
parameter POLYNOMIAL = 16'h1021,
parameter SEED = 16'h0000
)(
input clk,
input rst,
input en,
input bit,
output reg [15:0] crc
);
//local parameters
//registes/wires
wire inv;
//submodules
//asynchronous logic
assign inv = bit ^ crc[15]; // XOR required?
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
//crc <= SEED;
crc <= 0;
end
else begin
//Shift the output value
if (en) begin
//crc <= bit ? ({crc[14:0], 1'b0} ^ POLYNOMIAL) : {crc[14:0], 1'b0};
crc[15] <= crc[14];
crc[14] <= crc[13];
crc[13] <= crc[12];
crc[12] <= crc[11] ^ inv;
crc[11] <= crc[10];
crc[10] <= crc[9];
crc[9] <= crc[8];
crc[8] <= crc[7];
crc[7] <= crc[6];
crc[6] <= crc[5];
crc[5] <= crc[4] ^ inv;
crc[4] <= crc[3];
crc[3] <= crc[2];
crc[2] <= crc[1];
crc[1] <= crc[0];
crc[0] <= inv;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[201][201] = {0}; int n, m; int main(int argc, char *argv[]) { int x = 100; int y = 100; int ok = 0; cin >> n >> m; a[x][y] = n; do { ok = 0; int max = y; int min = x; for (int i = x; i <= y; i++) for (int j = x; j <= y; j++) if (a[i][j] >= 4) { ok = 1; int numofant = a[i][j]; int mods = numofant % 4; int temp = (numofant - mods) / 4; a[i][j - 1] += temp; a[i][j + 1] += temp; a[i - 1][j] += temp; a[i + 1][j] += temp; a[i][j] = mods; } if (a[x - 1][100] >= 4) { x--; y++; } } while (ok == 1); long long u, v; int k[50005]; for (int i = 0; i < m; i++) { cin >> u >> v; u += 100; v += 100; if (u > 200 || u < 0 || v > 200 || v < 0) k[i] = 0; else k[i] = a[u][v]; } for (int i = 0; i < m; i++) cout << k[i] << endl; return EXIT_SUCCESS; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_TB_V
`define SKY130_FD_SC_LS__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); float dist, h, w, t; cin >> dist; cin >> h; cin >> w; t = dist / (h + w); printf( %.12lf n , t * h); return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
parameter csr_addr = 4'h0,
parameter clk_freq = 50000000,
parameter baud = 115200
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
reg thru;
wire uart_tx_transceiver;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_irq),
.tx_data(tx_data),
.tx_wr(tx_wr),
.tx_done(tx_irq)
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = csr_di[7:0];
assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
parameter default_divisor = clk_freq/baud/16;
always @(posedge sys_clk) begin
if(sys_rst) begin
divisor <= default_divisor;
csr_do <= 32'd0;
end else begin
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[1:0])
2'b00: csr_do <= rx_data;
2'b01: csr_do <= divisor;
2'b10: csr_do <= thru;
endcase
if(csr_we) begin
case(csr_a[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= csr_di[15:0];
2'b10: thru <= csr_di[0];
endcase
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000500; typedef struct treap *ptreap; struct treap { int v, c, y; ptreap l, r; treap() {} treap(int v) : v(v), c(1), y(rand()), l(0), r(0) {} }; int cnt(ptreap t) { return t ? t->c : 0; } void recalc(ptreap t) { if (t) t->c = cnt(t->l) + cnt(t->r) + 1; } void split(ptreap t, int key, ptreap &l, ptreap &r) { if (!t) { l = r = 0; return; } int cur_key = cnt(t->l); if (key < cur_key) { split(t->l, key, l, t->l); r = t; } else { split(t->r, key - cur_key - 1, t->r, r); l = t; } recalc(t); } void merge(ptreap l, ptreap r, ptreap &t) { if (!l || !r) { t = l ? l : r; return; } if (l->y < r->y) { merge(l->r, r, l->r); t = l; } else { merge(l, r->l, r->l); t = r; } recalc(t); } void print(ptreap t) { if (!t) return; print(t->l); cout << t->v; print(t->r); } int n, m, val, r, cur, a[maxn]; ptreap t; int main() { ios_base::sync_with_stdio(false); cin.tie(0); srand(time(0)); cin >> n >> m; for (int i = 0; i < m; ++i) { cin >> a[i]; --a[i]; } for (int i = 0; i < n; ++i) { cin >> val; if (val == -1) { for (int j = 0; j < r; ++j) { ptreap q, w; split(t, a[j] - j, q, t); split(q, a[j] - j - 1, w, q); merge(w, t, t); } cur -= r; while (r > 0 && a[r - 1] > cur - 1) --r; } else { ptreap tmp = new treap(val); merge(t, tmp, t); ++cur; if (a[r] == cur - 1) ++r; } } if (!cur) cout << Poor stack! ; else print(t); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5; const int inf = 1e9 + 7; long long minv[1 << 16]; long long numx[15], numy[15]; long long n, a[maxn], x, y, A, B, facy[15000], ans; inline long long read() { char ch = getchar(); long long u = 0, f = 1; while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { u = u * 10 + ch - 48; ch = getchar(); } return u * f; } inline long long gcd(long long x, long long y) { return y == 0 ? x : gcd(y, x % y); } inline long long mul(long long x, long long y, long long p) { long long cnt = 0; while (y) { if (y & 1) cnt = (cnt + x) % p; x = (x + x) % p; y >>= 1; } return cnt; } inline long long ksm(long long x, long long k, long long p) { long long cnt = 1; while (k) { if (k & 1) cnt = mul(cnt, x, p); x = mul(x, x, p); k >>= 1; } return cnt; } inline bool judge(long long a, long long p) { long long q = p - 1; int k = 0; while (q % 2 == 0) ++k, q >>= 1; long long v = ksm(a, q, p); if (v == 1 || v == p - 1) return false; while (k-- != 0) { v = mul(v, v, p); if (v == p - 1) return false; } return true; } inline bool miller_rabbin(long long p) { if (p == 2) return true; if (p % 2 == 0) return false; for (register int i = 1; i <= 60; i++) { long long a = rand() % (p - 1) + 1; if (judge(a, p)) return false; } return true; } const int M = (1 << 7) - 1; inline long long pollard_rho(long long n) { if (n % 2 == 0) return 2; if (n % 3 == 0) return 3; long long x = 0, y = x, t = 1, q = 1, a = (rand() % (n - 1)) + 1; for (int k = 2;; k <<= 1, y = x, q = 1) { for (int i = 1; i <= k; ++i) { x = (mul(x, x, n) + a) % n; q = mul(q, abs(x - y), n); if (!(i & M)) { t = gcd(q, n); if (t > 1) break; } } if (t > 1 || (t = gcd(q, n)) > 1) break; } if (t == n) { t = 1; while (t == 1) t = gcd(abs((x = ((mul(x, x, n) + a) % n)) - y), n); } return t; } inline void findfac(long long x) { if (x == 1) return; if (miller_rabbin(x)) { facy[++facy[0]] = x; return; } long long p = x; while (p >= x) p = pollard_rho(p); findfac(p); findfac(x / p); } inline void dEBUG(long long *x, long long len) { cerr << ----------------------------------DEBUG----------------------------- ----- << endl; for (register int i = 0; i <= len; i++) cerr << x[i] << ; cerr << endl; cerr << ----------------------------------DEBUG----------------------------- ----- << endl; } int main() { srand(19260817); n = read(); A = x = read(); B = y = read(); if (y % x != 0) { cout << 0; return 0; } for (register int i = 1; i <= n; i++) a[i] = read(); if (B != 100000000000123502ll) { findfac(B); sort(facy + 1, facy + 1 + facy[0]); facy[0] = unique(facy + 1, facy + 1 + facy[0]) - facy - 1; } else { for (register int i = 2; 1ll * i * i <= B; i++) { if (B % i == 0) facy[++facy[0]] = i; while (B % i == 0) B /= i; } if (B != 1) facy[++facy[0]] = B; B = y; } for (register int i = 1; i <= facy[0]; i++) while (B % facy[i] == 0) B /= facy[i], numy[i]++; for (register int i = 1; i <= facy[0]; i++) while (A % facy[i] == 0) A /= facy[i], numx[i]++; for (register int i = 1; i <= n; i++) { if (a[i] % x != 0) continue; int maskx = 0; long long T = a[i]; for (register int k = 1; k <= facy[0]; k++) { int p = 0; if (numx[k] == numy[k]) continue; while (T % facy[k] == 0) T /= facy[k], p++; maskx |= ((p > numx[k]) << (k - 1)); } minv[maskx]++; } for (register int i = 0; i < facy[0]; i++) for (register int G = 0; G < (1 << facy[0]); G++) if (G & (1 << i)) minv[G] += minv[G ^ (1 << i)]; int MK = (1 << facy[0]) - 1; for (register int i = 1; i <= n; i++) { if (y % a[i] != 0) continue; int masky = 0; long long T = a[i]; for (register int k = 1; k <= facy[0]; k++) { int p = 0; while (T % facy[k] == 0) T /= facy[k], p++; masky |= ((p < numy[k]) << (k - 1)); } ans += minv[masky ^ MK]; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int k; cin >> k; int days[14]; int ones = 0; for (int i = 0; i < 7; i++) { cin >> days[i]; if (days[i]) ones++; days[i + 7] = days[i]; } int ans = 0; int left = 0; if (k % ones == 0) { ans = 7 * (k / ones - 1); left = ones; } else { ans = 7 * (k / ones); left = k % ones; } int c = 0, mini = INT_MAX; for (int i = 0; i < 14; i++) { if (!days[i]) continue; int c = 0, c2 = 0; for (int j = i; j < 14; j++) { if (days[j] == 1) c++; c2++; if (c == left) { mini = min(mini, c2); break; } } } cout << mini + ans << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_HD__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, t, dp[20][4][4][11][11]; int main() { scanf( %d%d , &n, &t); memset(dp, 0, sizeof(dp)); for (int i = 0; i != 4; ++i) for (int j = 0; j != 4; ++j) dp[1][i][j][0][0] = i != j; for (int i = 2; i != n; ++i) for (int j = 0; j != 4; ++j) for (int k = 0; k != 4; ++k) for (int l = 0; l <= t; ++l) for (int m = 0; m <= t; ++m) for (int o = 0; o != 4; ++o) dp[i][k][o][l + (j < k && k > o)][m + (j > k && k < o)] += k == o ? 0 : dp[i - 1][j][k][l][m]; int ans = 0; for (int i = 0; i != 4; ++i) for (int j = 0; j != 4; ++j) ans += dp[n - 1][i][j][t][t - 1]; printf( %d n , ans); return 0; } |
/*
* Module for performing other ALU operations
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_othop (x, y, seg, off, iflags, func, word_op, out, oflags);
// IO ports
input [15:0] x, y, off, seg, iflags;
input [2:0] func;
input word_op;
output [19:0] out;
output [8:0] oflags;
// Net declarations
wire [15:0] deff, deff2, outf, clcm, setf, intf, strf;
wire [19:0] dcmp, dcmp2;
wire dfi;
// Module instantiations
zet_mux8_16 mux8_16 (func, dcmp[15:0], dcmp2[15:0], deff, outf, clcm, setf,
intf, strf, out[15:0]);
assign out[19:16] = func ? dcmp2[19:16] : dcmp[19:16];
// Assignments
assign dcmp = (seg << 4) + deff;
assign dcmp2 = (seg << 4) + deff2;
assign deff = x + y + off;
assign deff2 = x + y + off + 16'd2;
assign outf = y;
assign clcm = y[2] ? (y[1] ? /* -1: clc */ {iflags[15:1], 1'b0}
: /* 4: cld */ {iflags[15:11], 1'b0, iflags[9:0]})
: (y[1] ? /* 2: cli */ {iflags[15:10], 1'b0, iflags[8:0]}
: /* 0: cmc */ {iflags[15:1], ~iflags[0]});
assign setf = y[2] ? (y[1] ? /* -1: stc */ {iflags[15:1], 1'b1}
: /* 4: std */ {iflags[15:11], 1'b1, iflags[9:0]})
: (y[1] ? /* 2: sti */ {iflags[15:10], 1'b1, iflags[8:0]}
: /* 0: outf */ iflags);
assign intf = {iflags[15:10], 2'b0, iflags[7:0]};
assign dfi = iflags[10];
assign strf = dfi ? (x - y) : (x + y);
assign oflags = word_op ? { out[11:6], out[4], out[2], out[0] }
: { iflags[11:8], out[7:6], out[4], out[2], out[0] };
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n; long long s(long long x) { long long ans = 0; while (x) ans += x % 10, x /= 10; return ans; } long long solve(long long x) { return x * x + s(x) * x - n; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; long long sq = sqrt(n); int i; for (i = sq - 1000000; i <= sq + 1000000; i++) { if (i > 0) if (solve(i) == 0) { cout << i << n ; return 0; } } cout << -1 << n ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
genvar g;
integer i;
reg [31:0] v;
reg [31:0] gen_pre_PLUSPLUS = 32'h0;
reg [31:0] gen_pre_MINUSMINUS = 32'h0;
reg [31:0] gen_post_PLUSPLUS = 32'h0;
reg [31:0] gen_post_MINUSMINUS = 32'h0;
reg [31:0] gen_PLUSEQ = 32'h0;
reg [31:0] gen_MINUSEQ = 32'h0;
reg [31:0] gen_TIMESEQ = 32'h0;
reg [31:0] gen_DIVEQ = 32'h0;
reg [31:0] gen_MODEQ = 32'h0;
reg [31:0] gen_ANDEQ = 32'h0;
reg [31:0] gen_OREQ = 32'h0;
reg [31:0] gen_XOREQ = 32'h0;
reg [31:0] gen_SLEFTEQ = 32'h0;
reg [31:0] gen_SRIGHTEQ = 32'h0;
reg [31:0] gen_SSRIGHTEQ = 32'h0;
generate
for (g=8; g<=16; ++g) always @(posedge clk) gen_pre_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; --g) always @(posedge clk) gen_pre_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g++) always @(posedge clk) gen_post_PLUSPLUS[g] = 1'b1;
for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
`ifndef verilator //UNSUPPORTED
for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
for (g=7; g>4; g&=4) always @(posedge clk) gen_ANDEQ[g] = 1'b1;
for (g=1; g<=1; g|=2) always @(posedge clk) gen_OREQ[g] = 1'b1;
for (g=7; g==7; g^=2) always @(posedge clk) gen_XOREQ[g] = 1'b1;
for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
`endif
endgenerate
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc == 3) begin
`ifdef TEST_VERBOSE
$write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS);
$write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS);
$write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS);
$write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS);
$write("gen_PLUSEQ %b\n", gen_PLUSEQ);
$write("gen_MINUSEQ %b\n", gen_MINUSEQ);
$write("gen_TIMESEQ %b\n", gen_TIMESEQ);
$write("gen_DIVEQ %b\n", gen_DIVEQ);
$write("gen_MODEQ %b\n", gen_MODEQ);
$write("gen_ANDEQ %b\n", gen_ANDEQ);
$write("gen_OREQ %b\n", gen_OREQ);
$write("gen_XOREQ %b\n", gen_XOREQ);
$write("gen_SLEFTEQ %b\n", gen_SLEFTEQ);
$write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ);
$write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ);
`endif
if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop;
if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
`ifndef verilator //UNSUPPORTED
if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop;
if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop;
if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
`endif
v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
`ifndef verilator //UNSUPPORTED
v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop;
v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop;
v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module peripheral_spi_master(clk , rst , d_in , cs , addr , rd , wr, d_out,mosi ,miso, sck, ss);
//entradas y salidas j1
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
input miso;
output mosi, sck, sssd_out;
//------------------------------------ regs and wires-------------------------------
//registros modulo peripheral
reg [6:0] s; //selector mux_4 and write registers
reg [7:0] data_in=0;
reg start=0;
reg reset=0;
reg sssd_in=1;
wire [7:0] data_out;
wire busy;
wire new_data;
//salidas fisicas
wire mosi;
wire miso;
wire sck;
wire ss;
//------------------------------------ regs and wires-------------------------------
always @(*) begin//------address_decoder------------------------------
case (addr)
//se asignan direcciones
//direcciones de escritura
4'h0:begin s = (cs && wr) ? 7'b0000001 : 7'b0000000 ;end //dMOSI
4'h2:begin s = (cs && wr) ? 7'b0000010 : 7'b0000000 ;end //start
4'h4:begin s = (cs && wr) ? 7'b0000100 : 7'b0000000 ;end //reset
4'h6:begin s = (cs && wr) ? 7'b0001000 : 7'b0000000 ;end //sssd_in
//direcciones de lectura
4'h8:begin s = (cs && rd) ? 7'b0010000 : 7'b0000000 ;end //dMISO
4'hA:begin s = (cs && rd) ? 7'b0100000 : 7'b0000000 ;end //busy
4'hC:begin s = (cs && rd) ? 7'b1000000 : 7'b0000000 ;end //avail
default:begin s = 7'b0000000 ; end
endcase
end//------------------address_decoder--------------------------------
always @(negedge clk) begin//-------------------- escritura de registros
data_in = (s[0]) ? d_in[7:0] : data_in; //dMISO //Write Registers
start = s[1] ; //Write Registers
reset = s[2] ; //Write Registers
sssd_in = (s[3]) ? d_in[0] : data_in;
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s[6:4])
3'b001: d_out[7:0] = data_out ; //dMOSI
3'b010: d_out[0] = busy ;
3'b100: d_out[0] = new_data ; //avail
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_4
spi_master spi_m (.clk(clk), .rst(reset), .sssd_in(sssd_in), .data_in(data_in), .start(start), .data_out(data_out), .busy(busy), .new_data(new_data), .miso(miso), .mosi(mosi), .sck(sck), .ss(ss), .sssd_out(sssd_out)); // se instancia modulo crc16
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; const int M = N * 30; int tree[M][2]; vector<int> val[M]; int main() { int n; scanf( %d , &n); vector<int> a(n + 1); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int idx = 0; auto insert = [&](int n, int id) { int tmp = 0; bitset<30> st(n); for (int i = 29; i >= 0; i--) { if (!tree[tmp][st[i]]) tree[tmp][st[i]] = ++idx; tmp = tree[tmp][st[i]]; val[tmp].emplace_back(id); } }; for (int i = 1; i <= n; i++) insert(a[i], i); auto get_cal = [&](vector<int> &a, vector<int> &b) -> long long { long long ans = 0; int i = 0, j = 0; while (i < a.size() && j < b.size()) { if (a[i] < b[j]) i++; else ans += (int)a.size() - i, j++; } return ans; }; vector<vector<long long>> ans(30, vector<long long>(2, 0)); function<void(int, int)> query = [&](int root, int deep) { if (!tree[root][0] && !tree[root][1]) return; long long cnt = get_cal(val[tree[root][0]], val[tree[root][1]]); ans[deep][0] += cnt; ans[deep][1] += 1LL * val[tree[root][0]].size() * val[tree[root][1]].size() - cnt; if (tree[root][0]) query(tree[root][0], deep - 1); if (tree[root][1]) query(tree[root][1], deep - 1); }; query(0, 29); int res = 0; long long cnt = 0; for (int i = 29; i >= 0; i--) { if (ans[i][0] > ans[i][1]) res += 1 << i, cnt += ans[i][1]; else cnt += ans[i][0]; } printf( %lld %d n , cnt, res); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int n = s.length(), cur = 1, best = 1; s += s; for (size_t i = 1; i < s.size(); i++) if (s[i] != s[i - 1]) cur++; else { best = max(best, cur); cur = 1; } best = max(best, cur); cout << min(n, best); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 105, INF = 1 << 30, MOD = 1e9 + 7; int n, k; vector<int> adj[N]; long long cnt[N][N]; long long ans = 0, F[N]; long long sumOfProducts(vector<int>& arr, int n, int k) { long long dp[n + 1][n + 1]; memset(dp, 0, sizeof(dp)); long long cur_sum = 0; for (int i = 1; i <= n; i++) { dp[1][i] = arr[i - 1]; (cur_sum += arr[i - 1]) %= MOD; } for (int i = 2; i <= k; ++i) { long long temp_sum = 0; for (int j = 1; j <= n; j++) { (cur_sum -= dp[i - 1][j]) %= MOD; dp[i][j] = (arr[j - 1] * cur_sum) % MOD; (temp_sum += dp[i][j]) %= MOD; } cur_sum = temp_sum; } return (cur_sum + MOD) % MOD; } void dfs(int u, int root, int p, int d) { ++cnt[root][d]; for (int v : adj[u]) { if (v == p) continue; dfs(v, root, u, d + 1); } } void solve(int u) { memset(cnt, 0, sizeof(cnt)); if (adj[u].size() < k) return; for (int v : adj[u]) { dfs(v, v, u, 0); } for (int i = 0; i < n; ++i) { int CNT = 0; for (int v : adj[u]) if (cnt[v][i]) ++CNT; if (CNT < k) break; vector<int> C; for (int v : adj[u]) if (cnt[v][i]) C.push_back(cnt[v][i]); (ans += sumOfProducts(C, CNT, k)) %= MOD; } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); F[0] = 1; for (int i = 1; i < N; ++i) F[i] = (F[i - 1] * i) % MOD; int t; cin >> t; while (t--) { ans = 0; cin >> n >> k; for (int i = 0; i < n; ++i) adj[i].clear(); for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; adj[--u].push_back(--v); adj[v].push_back(u); } if (k == 2) cout << n * (n - 1) / 2 << n ; else { for (int i = 0; i < n; ++i) solve(i); cout << ans % MOD << n ; } } } |
#include <bits/stdc++.h> using namespace std; void prime(long long int n, set<long long int> &s) { if (n % 2 == 0) { s.insert(2); n /= 2; } while (n % 2 == 0) { n /= 2; } for (int i = 3; i <= sqrt(n); i += 2) { if (n % i == 0) { s.insert(i); n /= i; } while (n % i == 0) { n /= i; } } if (n > 2) s.insert(n); } int main() { long long int n; cin >> n; set<long long int> s; prime(n, s); if (s.size() == 1) cout << *(s.begin()) << endl; else cout << 1 << endl; return (0); } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int RLEN = 1 << 18 | 1; inline char nc() { static char ibuf[RLEN], *ib, *ob; (ib == ob) && (ob = (ib = ibuf) + fread(ibuf, 1, RLEN, stdin)); return (ib == ob) ? -1 : *ib++; } inline int rd() { char ch = nc(); int i = 0, f = 1; while (!isdigit(ch)) { if (ch == - ) f = -1; ch = nc(); } while (isdigit(ch)) { i = (i << 1) + (i << 3) + ch - 0 ; ch = nc(); } return i * f; } const int N = 1e5 + 50; char ch[N]; int n, a[N], pre[N][26], suf[N][26]; int f[N][26], g[N], mem[27]; inline int mex(int sta) { return __builtin_ctz(~sta); } inline int calc(int l, int r, int c, int flag) { if (l > r) return 0; if (~mem[c]) return mem[c]; int sta = 0; for (int j = 0; j < 26; ++j) { int _l = suf[l][j], _r = pre[r][j]; if (_r >= l) sta |= 1 << (g[_r] ^ g[_l] ^ (!flag ? f[_l - 1][c] : calc(l, _l - 1, j, 1)) ^ (flag ? f[r][j] : calc(_r + 1, r, j, 0))); } return mem[c] = mex(sta); } int main() { scanf( %s , ch + 1); n = strlen(ch + 1); for (int i = 1; i <= n; i++) a[i] = ch[i] - a ; for (int i = 1; i <= n; i++) { for (int j = 0; j < 26; ++j) pre[i][j] = pre[i - 1][j]; pre[i][a[i]] = i; } for (int j = 0; j < 26; ++j) suf[n + 1][j] = n + 1; for (int i = n; i >= 1; i--) { for (int j = 0; j < 26; ++j) suf[i][j] = suf[i + 1][j]; suf[i][a[i]] = i; } for (int i = 1; i <= n; i++) { g[i] = f[i - 1][a[i]] ^ g[pre[i - 1][a[i]]]; memset(mem, -1, sizeof(mem)); for (int j = 0; j < 26; ++j) f[i][j] = calc(pre[i][j] + 1, i, j, 0); } int q = rd(); for (int i = 1; i <= q; i++) { int l = rd(), r = rd(); memset(mem, -1, sizeof(mem)); if (calc(l, r, 26, 1)) puts( Alice ); else puts( Bob ); } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
static task static_task(int x);
$write("Called static task: %d\n", x);
if (x != 16) $stop;
endtask
static function int static_function(int x);
$write("Called static function: %d\n", x);
if (x != 23) $stop;
return 42;
endfunction
endclass : Cls
class OCls;
int i;
static function OCls create();
OCls o = new;
o.i = 42;
return o;
endfunction
static task test_obj(OCls o);
if (o.i != 42) $stop;
endtask
endclass
module t (/*AUTOARG*/);
initial begin
int x;
OCls oc;
Cls::static_task(16);
x = Cls::static_function(23);
$write("Static function result: %d\n", x);
if (x != 42) $stop;
oc = OCls::create();
OCls::test_obj(oc);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool flag = false; long long n; long long mat[1000][1000]; bool vis[1000][1000]; long long ans[1000][1000]; bool isSol() { long long s = 0; for (int i = 0; i < n; i++) { s += ans[i][i]; } long long s2 = 0; for (int i = 0; i < n; i++) { s2 += ans[n - i - 1][i]; } if (s2 != s) return false; for (int i = 0; i < n; i++) { s2 = 0; for (int j = 0; j < n; j++) { s2 += ans[i][j]; } if (s2 != s) return false; } for (int i = 0; i < n; i++) { s2 = 0; for (int j = 0; j < n; j++) { s2 += ans[j][i]; } if (s2 != s) return false; } return true; } void find_sol(long long pos) { if (flag) return; if (pos == n * n) { if (isSol()) flag = true; return; } long long pos_x = pos / n; long long pos_y = pos % n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (!vis[i][j] && !flag) { vis[i][j] = true; ans[pos_x][pos_y] = mat[i][j]; find_sol(pos + 1); vis[i][j] = false; } } } } int main() { cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> mat[i][j]; vis[i][j] = false; } } find_sol(0); long long s = 0; for (int i = 0; i < n; i++) s += ans[i][0]; cout << s << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cout << ans[i][j] << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) using namespace std; const long long mod = 998244353; long long binpow(long long a, long long n) { if (n == 0) return 1; if (n % 2 == 1) { return (binpow(a, n - 1) * a) % mod; ; } else { long long b = binpow(a, n / 2); return (b * b) % mod; } } long long f[500]; long long f_obr[500]; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); f[0] = 1; f_obr[0] = 1; for (long long i = 1; i < 500; ++i) { f[i] = f[i - 1] * i; f[i] %= mod; f_obr[i] = binpow(f[i], mod - 2); } long long d; cin >> d; vector<long long> pr; pr.reserve(1e7 + 5); for (long long i = 2; i * i <= d; ++i) { if (d % i == 0) { pr.push_back(i); while (d % i == 0) d /= i; } } if (d > 1) pr.push_back(d); int q; cin >> q; for (int i = 0; i < q; ++i) { long long v[2]; cin >> v[0] >> v[1]; vector<long long> vc[2]; vector<int> cnt[2]; for (int j = 0; j < 2; ++j) for (int k = 0; k < int(pr.size()); ++k) if (v[j] % pr[k] == 0) { vc[j].push_back(pr[k]); cnt[j].push_back(0); while (v[j] % pr[k] == 0) { cnt[j].back()++; v[j] /= pr[k]; } } int uk = 0; vector<int> res[2]; for (int j = 0; j < int(cnt[0].size()); ++j) { while (uk < int(cnt[1].size()) && vc[1][uk] <= vc[0][j]) { if (vc[1][uk] == vc[0][j]) { if (cnt[0][j] > cnt[1][uk]) res[0].push_back(cnt[0][j] - cnt[1][uk]); else res[1].push_back(cnt[1][uk] - cnt[0][j]); } else res[1].push_back(cnt[1][uk]); ++uk; } if (!(uk > 0 && vc[1][uk - 1] == vc[0][j])) res[0].push_back(cnt[0][j]); } while (uk < int(cnt[1].size())) { res[1].push_back(cnt[1][uk]); ++uk; } int sum[2]; sum[0] = 0; sum[1] = 0; long long ans = 1; for (int j = 0; j < 2; ++j) for (int k = 0; k < int(res[j].size()); ++k) { sum[j] += res[j][k]; ans *= f_obr[res[j][k]]; ans %= mod; } ans *= f[sum[0]]; ans %= mod; ans *= f[sum[1]]; ans %= mod; cout << ans << n ; } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:33:17 05/25/2015
// Design Name: OneShot
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/One-ShotTest.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: OneShot
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module OneShotTest;
// Inputs
reg pulse;
reg clk;
reg rst;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
OneShot uut (
.pulse(pulse),
.clk(clk),
.rst(rst),
.out(out)
);
initial begin
// Initialize Inputs
pulse = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
#10;
pulse = 1;
#100; $stop;
// Add stimulus here
end
always #1.25 clk=~clk;
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double EPS = 1e-7; const int inf = 1e8; int main() { int n, sum = 0; cin >> n; vector<int> in(n); for (int i = 0; i < n; i++) cin >> in[i]; for (int i = 0; i < n; i++) sum += in[i]; vector<int> used(n); for (int i = 0; i < n; i++) if (!used[i]) { for (int j = i + 1; j < n; j++) if (!used[j] && in[i] + in[j] == sum * 2 / n) { used[i] = used[j] = true; cout << i + 1 << << j + 1 << endl; break; } } } |
/* Author: QAQAutoMaton Lang: C++ Code: F.cpp Mail: [email protected] Blog: https://www.qaq-am.com/ */ #include<bits/stdc++.h> #define int long long #define debug(qaq...) fprintf(stderr,qaq) #define DEBUG printf( Passing [%s] in LINE %d n ,__FUNCTION__,__LINE__) #define Debug debug( Passing [%s] in LINE %d n ,__FUNCTION__,__LINE__) #define all(x) x.begin(),x.end() #define x first #define y second #define unq(a) sort(all(a)),a.erase(unique(all(a)),a.end()) using namespace std; typedef unsigned uint; typedef long long ll; typedef unsigned long long ull; typedef complex<double> cp; typedef pair<int,int> pii; int inf; const double eps=1e-8; const double pi=acos(-1.0); template<class T,class T2>int chkmin(T &a,T2 b){return a>b?a=b,1:0;} template<class T,class T2>int chkmax(T &a,T2 b){return a<b?a=b,1:0;} template<class T>T sqr(T a){return a*a;} template<class T,class T2>T mmin(T a,T2 b){return a<b?a:b;} template<class T,class T2>T mmax(T a,T2 b){return a>b?a:b;} template<class T>T aabs(T a){return a<0?-a:a;} template<class T>int dcmp(T a,T b){return a>b;} template<int *a>int cmp_a(int x,int y){return a[x]<a[y];} template<class T>bool sort2(T &a,T &b){return a>b?swap(a,b),1:0;} #define min mmin #define max mmax #define abs aabs struct __INIT__{ __INIT__(){ fill((unsigned char*)&inf,(unsigned char*)&inf+sizeof(inf),0x3f); } }__INIT___; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; int f, qr; // getchar #define gc() (iS == iT ? (iT = (iS = ibuf) + fread (ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS ++)) : *iS ++) // print the remaining part inline void flush () { fwrite (obuf, 1, oS - obuf, stdout); oS = obuf; } // putchar inline void putc (char x) { *oS ++ = x; if (oS == oT) flush (); } template<typename A> inline bool read (A &x) { for (f = 1, c = gc(); c < 0 || c > 9 ; c = gc()) if (c == - ) f = -1;else if(c==EOF)return 0; for (x = 0; c <= 9 && c >= 0 ; c = gc()) x = x * 10 + (c & 15); x *= f; return 1; } inline bool read (char &x) { while((x=gc())== ||x== n || x== r ); return x!=EOF; } inline bool read(char *x){ while((*x=gc())== n || *x== ||*x== r ); if(*x==EOF)return 0; while(!(*x== n ||*x== ||*x== r ||*x==EOF))*(++x)=gc(); *x=0; return 1; } template<typename A,typename ...B> inline bool read(A &x,B &...y){ return read(x)&&read(y...); } template<typename A> inline bool write (A x) { if (!x) putc ( 0 ); if (x < 0) putc ( - ), x = -x; while (x) qu[++ qr] = x % 10 + 0 , x /= 10; while (qr) putc (qu[qr --]); return 0; } inline bool write (char x) { putc(x); return 0; } inline bool write(const char *x){ while(*x){putc(*x);++x;} return 0; } inline bool write(char *x){ while(*x){putc(*x);++x;} return 0; } template<typename A,typename ...B> inline bool write(A x,B ...y){ return write(x)||write(y...); } //no need to call flush at the end manually! struct Flusher_ {~Flusher_(){flush();}}io_flusher_; } using io :: read; using io :: putc; using io :: write; int p[200005]; int a[200005],b[200005]; int to[200005],mn[200005]; int fa[19][200005],f[19][200005]; int stk[200005],cnt[200005]; int query(int l,int r){ if(l==r)return 0; int ans=0; for(int i=18;~i;--i)if(fa[i][l]<=r){ ans+=f[i][l];l=fa[i][l]; } return ans; } int ans[200005]; vector<pii> xa[200005],xd[200005]; void add(int l,int r,int id){ xa[r].emplace_back(l,id); } void del(int l,int r,int id){ xd[r].emplace_back(l,id); } set<int> st; bitset<200005>cur; int t; int ask(int x){ int v=lower_bound(stk+1,stk+t+1,x)-stk; return cnt[t]-cnt[v]+query(x,stk[v]); } signed main(){ #ifdef QAQAutoMaton freopen( F.in , r ,stdin); freopen( F.out , w ,stdout); #endif int n,q; read(n,q); for(int i=1;i<=n;++i)read(p[i]); p[n+1]=n+1; for(int i=1;i<=n;++i)read(a[i]); for(int i=1;i<=n;++i)read(b[i]); stk[0]=n+1; for(int i=0;i<=18;++i){ fa[i][n+1]=n+1;f[i][n+1]=0; } for(int i=n;i;--i){ while(p[stk[t]]<p[i])--t; int j=stk[t]; stk[++t]=i; to[i]=j; mn[i]=min(b[i],a[i]+query(i+1,j)); f[0][i]=mn[i];fa[0][i]=to[i]; //write(i, ,to[i], ,mn[i], n ); for(int j=1;j<=18;++j){fa[j][i]=fa[j-1][fa[j-1][i]];f[j][i]=f[j-1][i]+f[j-1][fa[j-1][i]];} } st.insert(1);st.insert(n+1); add(1,n+1,0); for(int i=1;i<=q;++i){ int x; read(x); if(x==1)continue; if(cur[x]){ auto it=st.lower_bound(x); auto l=it,r=it; --l;++r; add(*l,*r,i); del(*l,x,i); del(x,*r,i); st.erase(it); cur[x]=0; } else{ cur[x]=1; auto r=st.lower_bound(x); auto l=r; --l; del(*l,*r,i); add(*l,x,i); add(x,*r,i); st.insert(x); } } stk[t=0]=0; p[0]=n+2; for(int i=1;i<=n+1;++i){ while(p[stk[t]]<p[i]){ --t; } stk[++t]=i; cnt[t]=cnt[t-1]+(a[stk[t-1]]+query(stk[t-1]+1,stk[t])); for(auto x:xa[i]){ans[x.y]+=ask(x.x);} for(auto x:xd[i]){ans[x.y]-=ask(x.x);} } for(int i=1;i<=q;++i){ ans[i]+=ans[i-1]; write(ans[i], n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long calc2(long long a, long long b, long long c, long long ab, long long ac, long long bc, long long abc) { long long parts[] = {a - ab - ac + abc, b - ab - bc + abc, c - ac - bc + abc, ab - abc, ac - abc, bc - abc, abc}; int masks[3] = {1 + 8 + 16 + 64, 2 + 8 + 32 + 64, 4 + 16 + 32 + 64}; static int mark[64 * 8] = {0}; static int id = 0; ++id; long long res = 0; for (int i = 0; i < 7; ++i) if ((masks[0] >> i) & 1) for (int j = 0; j < 7; ++j) if ((masks[1] >> j) & 1) for (int k = 0; k < 7; ++k) if ((masks[2] >> k) & 1) { int a1 = min(i, min(j, k)); int a3 = max(i, max(j, k)); int a2 = i + j + k - a1 - a3; if (mark[64 * a1 + 8 * a2 + a3] == id) continue; mark[64 * a1 + 8 * a2 + a3] = id; if (i == j && j == k) { long long x = parts[i]; res += +x * (x - 1) * (x - 2) / 6 + x * (x - 1) + x; } else if (i == j || j == k || i == k) { long long x = parts[i]; long long y = parts[j]; if (i == j) y = parts[k]; else if (j == k) swap(x, y); res += x * (x + 1) / 2 * y; } else { res += parts[i] * parts[j] * parts[k]; } } return res; } int get_common_num(vector<int> &a, vector<int> &b) { int ia = 0, ib = 0; int res = 0; while (ia < a.size() && ib < b.size()) { if (a[ia] == b[ib]) { ++res; ++ia, ++ib; } else if (a[ia] < b[ib]) ++ia; else ++ib; } return res; } int get_common_num(vector<int> &a, vector<int> &b, vector<int> &c) { int ia = 0, ib = 0, ic = 0; int res = 0; while (ia < a.size() && ib < b.size() && ic < c.size()) { if (a[ia] == b[ib] && b[ib] == c[ic]) { ++res; ++ia, ++ib, ++ic; } else if (a[ia] <= min(b[ib], c[ic])) ++ia; else if (b[ib] <= min(a[ia], c[ic])) ++ib; else ++ic; } return res; } vector<int> dividers[100111]; int main() { ios::sync_with_stdio(false); dividers[1].push_back(1); vector<int> smallest_fact(100111 + 1, 0); for (int i = 2; i < 100111; ++i) { if (!smallest_fact[i]) { smallest_fact[i] = i; for (long long j = i * (long long)i; j < 100111; j += i) { if (!smallest_fact[j]) smallest_fact[j] = i; } } int p = smallest_fact[i]; int x = i; while (x % p == 0) x /= p; int y = i; int pp = p; dividers[i] = dividers[x]; while (y % p == 0) { for (int d : dividers[x]) dividers[i].push_back(pp * d); pp *= p; y /= p; } sort(dividers[i].begin(), dividers[i].end()); } int t; cin >> t; while (t--) { int a, b, c; cin >> a >> b >> c; int x = dividers[a].size(); int y = dividers[b].size(); int z = dividers[c].size(); int xy = get_common_num(dividers[a], dividers[b]); int xz = get_common_num(dividers[a], dividers[c]); int yz = get_common_num(dividers[b], dividers[c]); int xyz = get_common_num(dividers[a], dividers[b], dividers[c]); long long ans = calc2(x, y, z, xy, xz, yz, xyz); cout << ans << n ; } return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module FX3_IF (
inout wire [31:0] fx3_bus,
input wire fx3_wr,
input wire fx3_oe,
input wire fx3_cs,
input wire fx3_clk, // FX3 generates user clock
output reg fx3_rdy, // will be monitored by FPGA internally during READ
output reg fx3_ack,
output reg fx3_rd_finish,
input wire fx3_rst,
output wire BUS_CLK, // FX3 generates user clock
output wire BUS_RST,
output reg BUS_WR,
output reg BUS_RD,
output reg [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_BYTE_ACCESS,
input wire FLAG1,
input wire FLAG2
);
wire [31:0] DataOut; // data from FPGA core
reg [31:0] DataIn; // data to FPGA core, force IOB register
assign BUS_DATA = BUS_WR ? DataIn[31:0]: 32'bz;
assign DataOut[31:0] = BUS_WR ? 32'bz : BUS_DATA;
genvar gen;
reg [31:0] DATA_MISO; // master in slave out FPGA -> FX3, registered
wire [31:0] DATA_MOSI; // master out slave in FX3 -> FPGA
reg [31:0] ReqCountLimit;
reg [31:0] ReqCount;
reg OE;
reg CS;
reg FLAG1_reg;
reg FLAG2_reg;
reg RD_VALID;
reg RDY;
assign BUS_RST = fx3_rst;
// clock buffer
IBUFG #(
.IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
.IOSTANDARD("DEFAULT") // Specify the input I/O standard
) IBUFG_inst (
.O(BUS_CLK), // Clock buffer output
.I(fx3_clk) // Clock buffer input (connect directly to top-level port)
);
reg [7:0] DATA_BYTE_RD [3:0];
reg [7:0] DATA_BYTE_WR [3:0];
wire [1:0] BYTE;
assign BYTE = ReqCount[1:0]-1;
reg WR_BYTE;
always @(posedge BUS_CLK)
DATA_BYTE_RD[BYTE] <= DataOut[7:0];
reg RD_FINISH;
// output register
always @(posedge BUS_CLK)
begin
fx3_ack <= RD_VALID; // will be generated during RD_ADDR_INC
fx3_rd_finish <= RD_FINISH;
fx3_rdy <= RDY;
if(BUS_RST)
DATA_MISO <= 0;
else if(BUS_BYTE_ACCESS) begin
if(BYTE==0)
DATA_MISO <= { {3{8'b0}}, DataOut[7:0]};
else if(BYTE==1)
DATA_MISO <= { {2{8'b0}}, DataOut[7:0], DATA_BYTE_RD[0]};
else if(BYTE==2)
DATA_MISO <= {8'b0, DataOut[7:0], DATA_BYTE_RD[1], DATA_BYTE_RD[0]};
else
DATA_MISO <= {DataOut[7:0], DATA_BYTE_RD[2], DATA_BYTE_RD[1], DATA_BYTE_RD[0]};
end
else
DATA_MISO <= DataOut;
end
reg first_word_written_check;
// input register
always @(posedge BUS_CLK)
begin
if(BUS_BYTE_ACCESS)
BUS_WR <= (fx3_wr | WR_BYTE);
else
BUS_WR <= fx3_wr;
OE <= fx3_oe;
CS <= fx3_cs;
FLAG1_reg <= FLAG1;
FLAG2_reg <= FLAG2;
if(!CS | !BUS_BYTE_ACCESS)
first_word_written_check <= 0;
if(BUS_BYTE_ACCESS & (fx3_wr | BUS_WR) & ((ReqCount+1) < ReqCountLimit)) begin
if(((ReqCount[1:0]==0)|(ReqCount[1:0]==3)) & (!first_word_written_check)) begin
{DATA_BYTE_WR[2], DATA_BYTE_WR[1], DATA_BYTE_WR[0], DataIn[7:0]} <= DATA_MOSI;
first_word_written_check <= 1;
end
else if((ReqCount[1:0]==0) & first_word_written_check) begin
DataIn[7:0] <= DATA_BYTE_WR[0];
first_word_written_check <= 0;
end
else if(ReqCount[1:0]==1)
DataIn[7:0] <= DATA_BYTE_WR[1];
else if(ReqCount[1:0]==2)
DataIn[7:0] <= DATA_BYTE_WR[2];
end
else
DataIn <= DATA_MOSI;
end
parameter IDLE = 0;
parameter IN_ADDR = 1;
parameter WR_ADDR_INC = 2;
parameter IN_COUNT = 3;
parameter FINISH_RD = 4;
parameter RD_ADDR_INC = 5;
parameter RD_WAIT = 6;
parameter WAIT = 7;
reg [4:0] state, next_state;
always @(posedge BUS_CLK)
if (BUS_RST)
state <= IDLE;
else
state <= next_state;
always @(*) begin
case(state)
IDLE :
if (CS & !OE & !first_word_written_check) // !OE is needed to prevent entering IN_ADDR after read request is finished. !first_word_written_check -||- after writing is finished.
next_state = IN_ADDR;
else
next_state = IDLE;
IN_ADDR :
next_state = IN_COUNT;
IN_COUNT :
if (OE)
next_state = RD_ADDR_INC;
else if (BUS_WR)
next_state = WR_ADDR_INC;
else
next_state = WAIT;
WR_ADDR_INC :
if(BUS_BYTE_ACCESS)
begin
if (BUS_WR & ((ReqCount+1) != ReqCountLimit))
next_state = WR_ADDR_INC;
else if ((ReqCount+1) == ReqCountLimit)
next_state = IDLE;
end
else
begin
if (BUS_WR)
next_state = WR_ADDR_INC;
else if (!CS)
next_state = IDLE;
end
RD_ADDR_INC :
if (OE & (ReqCount != ReqCountLimit))
next_state = RD_ADDR_INC;
else if (ReqCount == ReqCountLimit)
next_state = FINISH_RD;
FINISH_RD:
next_state = IDLE;
RD_WAIT :
next_state = IDLE;
WAIT :
if (OE)
next_state = RD_ADDR_INC;
else if (BUS_WR)
next_state = WR_ADDR_INC;
else
next_state = WAIT;
default : next_state = IDLE;
endcase
end
always @(posedge BUS_CLK)
begin
if (BUS_RST)
begin
BUS_ADD <= 32'd0;
ReqCountLimit <= 32'd0;
ReqCount <= 32'd0;
BUS_RD <= 0;
RD_VALID <= 0;
RDY <= 0;
RD_FINISH <= 0;
WR_BYTE <= 0;
end
else
begin
if (state == IDLE)
begin
ReqCountLimit <= 32'd0;
ReqCount <= 32'd0;
BUS_RD <= 0;
RDY <= 0;
end
else if (state == IN_ADDR)
begin
BUS_ADD <= DataIn[31:0];
RD_FINISH <= 0;
RDY <= 1; // First RDY strobe is generated for FX3. FX3 will receive it and go to Write Data state where fx3_wr signal will be asserted. (3 clock cycles delay between RDY and fx3_wr)
end
else if (state == IN_COUNT)
begin
if (OE)
BUS_RD <= 1;
else if (BUS_WR)
begin
if(BUS_BYTE_ACCESS)
begin
BUS_ADD[31:0] <= BUS_ADD[31:0] + 1;
ReqCount <= ReqCount + 1;
end
else
BUS_ADD[31:0] <= BUS_ADD[31:0] + 4;
end
else
begin
ReqCountLimit <= (DataIn[31:0]);
if (BUS_BYTE_ACCESS)
RDY <= 0; // Deassert first RDY strobe
else
RDY <= 1;
if (fx3_wr & BUS_BYTE_ACCESS)
WR_BYTE <= 1; // "Or" with WR - to keep WR high even when fx3_wr is low during BYTE_ACCESS
end
end
else if (state == WR_ADDR_INC)
begin
if(BUS_BYTE_ACCESS)
begin
if (BUS_WR & ((ReqCount+1) != ReqCountLimit))
begin
BUS_ADD[31:0] <= BUS_ADD[31:0] + 1;
ReqCount <= ReqCount + 1;
if(ReqCount[1:0] == 2'b11 && ((ReqCount+4) < ReqCountLimit))
RDY <= 1; // Assert next RDY strobe if there is next transfer of 1-4 bytes expected. RDY will be asserted on the next cycle after the last byte of the current transfer that was sampled.
else
RDY <= 0;
end
if (ReqCount+2 >= ReqCountLimit)
WR_BYTE <= 0;
end
else
if (BUS_WR)
BUS_ADD[31:0] <= BUS_ADD[31:0] + 4;
end
else if (state == RD_ADDR_INC)
begin
if (OE & (ReqCount != ReqCountLimit))
begin
if(BUS_BYTE_ACCESS)
begin
BUS_ADD[31:0] <= BUS_ADD + 1;
ReqCount <= ReqCount + 1;
if(ReqCount + 1 == ReqCountLimit)
BUS_RD <= 0;
else
BUS_RD <= 1;
if(ReqCount[1:0] == 2'b11 || ReqCount + 1 == ReqCountLimit)
RD_VALID <= 1;
else
RD_VALID <= 0;
end
else
begin
BUS_ADD[31:0] <= BUS_ADD + 4;
ReqCount <= ReqCount + 4;
if(ReqCount + 4 == ReqCountLimit)
BUS_RD <= 0;
else
BUS_RD <= 1;
RD_VALID <= 1;
end
end
else if (ReqCount == ReqCountLimit)
begin
BUS_RD <= 0;
RD_VALID <= 0;
RD_FINISH <= 1;
end
end
else if (state == FINISH_RD)
;
else if (state == WAIT)
begin
if (OE)
BUS_RD <= 1;
else if (BUS_WR)
begin
if(BUS_BYTE_ACCESS)
begin
BUS_ADD[31:0] <= BUS_ADD[31:0] + 1;
ReqCount <= ReqCount + 1;
RDY <= 0; // Deassert second RDY strobe
if(ReqCountLimit == 2)
WR_BYTE <= 0; // WR deasserts with 1 cycle delay after WR_BYTE deasserts
end
else
BUS_ADD[31:0] <= BUS_ADD[31:0] + 4;
end
else if (fx3_wr & BUS_BYTE_ACCESS)
begin
if(ReqCountLimit > 1)
WR_BYTE <= 1;
if ((ReqCount+4) < ReqCountLimit)
RDY <= 1; // Assert second RDY strobe if there is second transfer of 1-4 bytes expected
end
end
end
end
// tristate buffer for bus
generate
for (gen = 0; gen < 32; gen = gen + 1)
begin : tri_buf // 32 bit databus
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS33"), // Specify the I/O standard
.SLEW("FAST") // Specify the output slew rate
) IOBUF_inst (
.O(DATA_MOSI[gen]), // Buffer output
.IO(fx3_bus[gen]), // Buffer inout port (connect directly to top-level port)
.I(DATA_MISO[gen]), // Buffer input
.T(!(fx3_oe & fx3_cs)) // 3-state enable input, high=input, low=output
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long double F(int A, int B) { long double S = 1; for (int i = 0; i < B; i++) S = S * (A - i) / (i + 1); return S; } int main() { int N; scanf( %d , &N); static int C[100000], Max[100000]; static long double P[100000][101]; memset(P, 0, sizeof(P)); for (int i = 0; i < N; i++) { scanf( %d , &C[i]); Max[i] = C[i]; P[i][C[i]] = 1; } int Query; scanf( %d , &Query); long double Ans = 0; for (int i = 0; i < N; i++) if (!C[i]) Ans++; while (Query--) { int a, b, K; scanf( %d%d%d , &a, &b, &K); a--; b--; static long double DP[101]; memset(DP, 0, sizeof(DP)); long double All = F(C[a], K); for (int i = 0; i <= C[a] && i <= Max[a]; i++) for (int j = max(0, K - C[a] + i); j <= K && j <= i; j++) DP[i - j] += P[a][i] * F(i, j) * F(C[a] - i, K - j) / All; Ans += DP[0] - P[a][0]; for (int i = 0; i <= Max[a]; i++) P[a][i] = DP[i]; C[a] -= K; C[b] += K; printf( %0.10lf n , (double)Ans); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
/**
* sdlxtp: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlxtp (
Q ,
D ,
SCD ,
SCE ,
GATE
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_BLACKBOX_V
|
`timescale 1ns / 1ps
// width = 32
// depth = 256
// depth_log2 = 8
// is_async_fifo = 0
// is_sync_read = 1
// is_read_without_pop = 0
// is_multi_pop = 0
// is_write_commit = 0
// is_flush = 1
module fifo (
din
, write_busy
, fifo_full
, dout
, read_busy
, fifo_empty
, fifo_clk
, rst_n
, fifo_flush
);
//INPUT ports
input [32-1:0] din;
input write_busy;
input read_busy;
input fifo_clk;
input rst_n;
input fifo_flush;
//OUTPUT ports
output [32-1:0] dout;
output fifo_empty;
output fifo_full;
reg [32-1:0] dout;
reg fifo_full;
reg fifo_empty;
reg [8:0] write_occupancy;
reg [8:0] read_occupancy;
reg [8:0] next_write_occupancy;
reg [8:0] next_read_occupancy;
wire [7:0] next_write_ptr;
reg [7:0] write_ptr;
wire [7:0] next_read_ptr;
reg [7:0] read_ptr;
reg [32-1:0] data_array[256-1:0];
wire [7:0] read_index;
wire [32-1:0] dout_next;
reg write_busy_d;
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n) begin
write_ptr <= 8'b0;
end else begin
write_ptr <= next_write_ptr;
end
end // always posedge ..
//Calculate next write pointer value
assign next_write_ptr = fifo_flush ? 8'b0 : (write_ptr + (write_busy & ~fifo_full));
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n) begin
read_ptr <= 8'b0;
end else begin
read_ptr <= next_read_ptr;
end
end // always posedge ..
//Calculate next read pointer value
assign next_read_ptr = fifo_flush ? 8'b0 : (read_ptr + (read_busy & ~fifo_empty));
// Read correct memory location
assign read_index[8-1:0] = read_busy ? next_read_ptr : read_ptr;
//Write data into memory
always @(posedge fifo_clk)
if (write_busy )
data_array[write_ptr] <= din;
//Read memory data
always @(posedge fifo_clk) begin
dout <= dout_next;
end
assign dout_next = {data_array[read_index[8-1:0]]};
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n) begin
write_occupancy <= 8'b0;
end else begin
write_occupancy <= next_write_occupancy;
end
end
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n) begin
read_occupancy <= 8'b0;
end else begin
read_occupancy <= next_read_occupancy;
end
end
always @(posedge fifo_clk or negedge rst_n) begin
if(!rst_n) begin
write_busy_d <= 1'b0;
end else begin
write_busy_d <= write_busy;
end
end
always @(*) begin
if (fifo_flush) begin
next_read_occupancy = 8'b0;
end else begin
case ({write_busy_d,read_busy})
2'b00: next_read_occupancy = read_occupancy;
2'b01: next_read_occupancy = read_occupancy - 1'b1;
2'b10: next_read_occupancy = read_occupancy + 1'b1;
2'b11: next_read_occupancy = read_occupancy;
default: next_read_occupancy = read_occupancy;
endcase
end
end
always @(*) begin
if (fifo_flush) begin
next_write_occupancy = 8'b0;
end else begin
case ({write_busy,read_busy})
2'b00: next_write_occupancy = write_occupancy;
2'b01: next_write_occupancy = write_occupancy - 1'b1;
2'b10: next_write_occupancy = write_occupancy + 1'b1;
2'b11: next_write_occupancy = write_occupancy;
default: next_write_occupancy = write_occupancy;
endcase
end
end
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n)
fifo_full <= 0;
else if (next_write_occupancy == 256)
fifo_full <= 1;
else
fifo_full <= 0;
end
always @(posedge fifo_clk or negedge rst_n) begin
if (!rst_n)
fifo_empty <= 1;
else if (next_read_occupancy == 0)
fifo_empty <= 1;
else
fifo_empty <= 0;
end
// synthesis translate_off
always @(posedge fifo_clk) begin
if (fifo_full && write_busy) begin
$display("ERROR: %m: Fifo overflow at time %t", $time);
$finish;
end
end // always
// synthesis translate_on
// synthesis translate_off
always @(posedge fifo_clk) begin
if (fifo_empty && read_busy) begin
$display("ERROR: %m: Fifo underflow at time %t", $time);
$finish;
end
end // always
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 0 ), c = getchar(); return x * f; } const int N = 2e5 + 5; int d, n, m; struct node { int x, p; } a[N]; inline int operator<(const node x, const node y) { if (x.p == y.p) return x.x > y.x; return x.p > y.p; } inline int cmp(node x, node y) { return x.x < y.x; } priority_queue<node> q; long long ans; int main() { d = read(), n = read(), m = read(); for (int i = 1; i <= m; i++) a[i] = {read(), read()}; sort(a + 1, a + m + 1, cmp); int t = n, j = 1; while (t < d) { while (j <= m && a[j].x <= t) q.push(a[j++]); while (!q.empty() && q.top().x + n <= t) q.pop(); if (q.empty()) return puts( -1 ), 0; int x = q.top().x, p = q.top().p; int nxt = min(d, x + n); if (j <= m && nxt >= a[j].x) nxt = a[j].x; ans += 1ll * p * (nxt - t); t = nxt; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void dbg_out() { cerr << b b] n ; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << H << , ; dbg_out(T...); } void solve() { long double n; cin >> n; cout << fixed << setprecision(10); if (n == 2) { long double ans = 1; cout << ans << n ; return; } n *= 2; const double pi = acosl((long double)-1); double radian = pi / n; double radius = 1.0 / tan(radian); cout << radius << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t = 0; cin >> t; while (t--) { solve(); } return 0; } |
`timescale 1 ns / 1 ps
module axis_fifo #
(
parameter integer S_AXIS_TDATA_WIDTH = 32,
parameter integer M_AXIS_TDATA_WIDTH = 32
)
(
// System signals
input wire aclk,
// Slave side
output wire s_axis_tready,
input wire [S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
// FIFO_WRITE port
input wire fifo_write_full,
output wire [S_AXIS_TDATA_WIDTH-1:0] fifo_write_data,
output wire fifo_write_wren,
// FIFO_READ port
input wire fifo_read_empty,
input wire [M_AXIS_TDATA_WIDTH-1:0] fifo_read_data,
output wire fifo_read_rden
);
assign m_axis_tdata = fifo_read_empty ? {(M_AXIS_TDATA_WIDTH){1'b0}} : fifo_read_data;
assign m_axis_tvalid = 1'b1;
assign s_axis_tready = 1'b1;
assign fifo_read_rden = m_axis_tready;
assign fifo_write_data = s_axis_tdata;
assign fifo_write_wren = s_axis_tvalid;
endmodule
|
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