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#include <bits/stdc++.h> using namespace std; bool test_cases_exist = false; void solve() { long long int i, j, n, m, k, x, y, ans; cin >> n; vector<long long int> v(n); for (auto &z : v) cin >> z; long long int bit = 23; long long int oneall = (1 << 23) - 1; vector<long long int> dp((1 << 23), -1); for (auto z : v) dp[z] = z; for (i = 0; i < (1 << bit); i++) { for (j = 0; j < bit; j++) { if (dp[i] != -1) break; if (i >> j & 1) dp[i] = dp[i ^ 1 << j]; } } for (auto z : v) cout << dp[oneall ^ z] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int t = 1; if (test_cases_exist) cin >> t; while (t--) solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_4_V
`define SKY130_FD_SC_LP__A32O_4_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 10; char g[maxn][maxn]; long long dp[1 << maxn][1 << maxn]; int main() { int n, mask1, mask2, i, j, m, k, a, b, count; long long ans; cin >> n >> m >> k; for (i = 0; i < m; i++) { cin >> a >> b; a--; b--; g[a][b] = g[b][a] = 1; dp[(1 << a) | (1 << b)][(1 << a) | (1 << b)] = 2; } for (mask1 = 0; mask1 < (1 << n); mask1++) for (mask2 = mask1; mask2; mask2 = (mask1 & (mask2 - 1))) { if (!dp[mask1][mask2]) continue; count = 0; for (i = 0; i < n; i++) if (mask2 & (1 << i)) count++; dp[mask1][mask2] /= count; for (i = 0; i < n; i++) if (mask1 & (1 << i)) for (j = 0; j < n; j++) if (g[i][j] && !(mask1 & (1 << j))) { if (mask2 & (1 << i)) dp[mask1 ^ (1 << j)][mask2 ^ (1 << i) ^ (1 << j)] += dp[mask1][mask2]; else dp[mask1 ^ (1 << j)][mask2 ^ (1 << j)] += dp[mask1][mask2]; } } ans = 0; for (i = 0; i < (1 << n); i++) { count = 0; for (j = 0; j < n; j++) if (i & (1 << j)) count++; if (count == k) ans += dp[(1 << n) - 1][i]; } cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int a[110]; int gcd(int x, int y) { if (!x) return y; else return gcd(y % x, x); } int main() { int n, mx = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; mx = max(mx, a[i]); } int g = a[0]; for (int i = 1; i < n; i++) g = gcd(g, a[i]); if ((mx / g - n) % 2 == 1) cout << Alice << endl; else cout << Bob << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_4_V
`define SKY130_FD_SC_HDLL__OR4B_4_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_4 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4b_4 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_4_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
module ISpm(input clk,
input [11:0] io_core_r_addr,
input io_core_r_enable,
output[31:0] io_core_r_data_out,
input [11:0] io_core_rw_addr,
input io_core_rw_enable,
output[31:0] io_core_rw_data_out,
input io_core_rw_write,
input [31:0] io_core_rw_data_in,
input [11:0] io_bus_addr,
input io_bus_enable,
output [31:0] io_bus_data_out,
input io_bus_write,
input [31:0] io_bus_data_in,
output io_bus_ready
);
genvar i;
generate
for(i = 0; i < 8; i = i+1)
begin: BRAMS
reg [3:0] ispm [4095:0];
reg [3:0] r_data_out, rw_data_out;
always @(posedge clk) begin
if(io_core_r_enable) begin
r_data_out <= ispm[io_core_r_addr];
end
end
assign io_core_r_data_out[4*i+3:4*i] = r_data_out;
always @(posedge clk) begin
if(io_core_rw_enable) begin
if(io_core_rw_write) begin
ispm[io_core_rw_addr] <= io_core_rw_data_in[4*i+3:4*i];
end
rw_data_out <= ispm[io_core_rw_addr];
end
end
//assign io_core_rw_data_out[4*i+3:4*i] = rw_data_out;
end
endgenerate
//assign io_core_rw_data_out = 32'b0;
assign io_bus_ready = 1'b0;
//assign io_bus_data_out = 32'b0;
endmodule
|
/*
* sram_ctl - Push and pull data to/from the SRAM
*
* This allows the supervisor to put data in the SRAM memory and read it out again.
* Note that this operation halts the CPC clock and so affects CPC timing
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
* Registers:
* 0000 (0x0) Data In/Out
* 1000 (0x8) Set address low byte (0-7)
* 1001 (0x9) Set address middle byte (8-15)
* 1010 (0xa) Set address high byte (16-23)
* 1111 (0xF) Control signals
* b7 - Assert supervisor bus control (halts CPC clock)
* b6 - Use control signals, not memory addresses
*/
`timescale 1ns/1ns
`default_nettype none
module sram_ctl (
// Control signals
input wire clk_i,
input wire reset_i,
// Support Bus signals
input wire [3:0] A_i,
input wire [7:0] D_i,
output wire [7:0] D_o,
input wire rd_i,
input wire wr_i,
output reg wait_o,
// Memory arbiter signals
output reg cpc_pause_o,
input cpc_pause_ack_i,
// CPC Signals/RAMROM signals
input wire [23:0] cpc_A_i,
input wire [7:0] cpc_D_i,
output wire [7:0] cpc_D_o,
input wire cpc_en_i,
input wire cpc_rd_i,
input wire cpc_wr_i,
output wire [63:0] cpc_romflags_o,
// Memory signals
output wire [23:0] mem_A_o,
input wire [15:0] mem_D_i,
output wire [15:0] mem_D_o,
output wire mem_go_o,
output wire [2:0] mem_cmd_o,
input wire mem_busy_i,
input wire mem_valid_i
);
// Wire definitions ===========================================================================
wire rd_rise, wr_rise, crd_rise, cwr_rise, busy_rise;
wire [7:0] support_data_snip;
// Registers ==================================================================================
reg [7:0] A[0:3], DOUT = 8'd0;
reg [1:0] track_rd = 2'd0, track_wr = 2'd0, track_crd = 2'd0, track_cwr = 2'd0;
reg control_ops = 1'd0;
reg old_lsb = 1'b0, incr_address = 1'b0;
reg [63:0] romflags = 64'd0;
// Assignments ================================================================================
assign mem_A_o = (cpc_pause_o & cpc_pause_ack_i) ? {1'b0, A[2], A[1], A[0][7:1]} : {1'b0,cpc_A_i[23:1]}; // A multiplexor
assign mem_D_o = (cpc_pause_o & cpc_pause_ack_i) ? {D_i,D_i} : {cpc_D_i,cpc_D_i}; // D multiplexor
assign mem_go_o = (cpc_pause_o & cpc_pause_ack_i) ? // en multiplexor
((rd_rise | wr_rise) & (A_i==4'd0)) :
((crd_rise | cwr_rise) & cpc_en_i);
assign mem_cmd_o = (cpc_pause_o & cpc_pause_ack_i) ? {control_ops, rd_i, control_ops ? 1'b1 : A[0][0]} : {1'b0, cpc_rd_i, cpc_A_i[0]};
// CPC Output
assign cpc_D_o = cpc_A_i[0] ? mem_D_i[15:8] : mem_D_i[7:0];
// Snip the correct byte from the word returned from memory
assign support_data_snip = (old_lsb ? mem_D_i[15:8] : mem_D_i[7:0]);
// Switch between internal code and memory data
assign D_o = (A_i == 4'd0) ? support_data_snip : DOUT;
// Output the ROMFLAGS
assign cpc_romflags_o = romflags;
// Track rise
assign rd_rise = (track_rd == 2'b01);
assign wr_rise = (track_wr == 2'b01);
assign crd_rise = (track_crd == 2'b01);
assign cwr_rise = (track_cwr == 2'b01);
// Wait signal when processing a txn, and data not yet valid
//assign wait_o = incr_address & ~mem_valid_i;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Core logic ================================================================================
// Track rises
always @(posedge clk_i) track_rd <= {track_rd[0],rd_i};
always @(posedge clk_i) track_wr <= {track_wr[0],wr_i};
always @(posedge clk_i) track_crd <= {track_rd[0],cpc_rd_i};
always @(posedge clk_i) track_cwr <= {track_wr[0],cpc_wr_i};
// Handle the IO bus signals
always @(posedge clk_i or posedge reset_i)
if( reset_i ) begin
{A[3],A[2],A[1],A[0]} <= 32'd0;
DOUT <= 8'd0;
cpc_pause_o <= 1'b0;
incr_address <= 1'b0;
romflags <= 64'd0;
end else begin
// When controller accepted address, then increment address
if( (mem_valid_i | mem_busy_i) & incr_address ) begin
old_lsb <= A[0][0];
{A[3],A[2],A[1],A[0]} <= {A[3],A[2],A[1],A[0]} + 1'b1;
incr_address <= 1'b0;
end
else
case( A_i )
4'b0000 : begin
// Trigger an update to the address is requested
if( rd_rise | wr_rise ) incr_address <= 1'b1;
end
// Read/write the starting address
4'b1000, 4'b1001, 4'b1010, 4'b1011 : begin
if( rd_i ) DOUT <= A[A_i[1:0]];
else
if( wr_i ) A[A_i[1:0]] <= D_i;
end
// Not really an SRAM function, but manages the rom flags
4'b1100 : begin
if( wr_i ) case( D_i[7:6] )
2'b01 : romflags[D_i[5:0]] <= 1'b0; // Clear
2'b10 : romflags[D_i[5:0]] <= 1'b1; // Set
2'b11 : romflags <= 64'd0; // Flush ROMS
endcase
end
// Control signals
4'b1111 : begin
if( wr_i ) begin
cpc_pause_o <= D_i[7];
control_ops <= D_i[6];
end
else
if( rd_i ) DOUT <= {cpc_pause_ack_i,control_ops,6'd0};
end
default: ;
endcase
end
// Manage WAIT signal
always @(posedge clk_i or posedge reset_i)
if( reset_i ) wait_o <= 1'b0;
else begin
if( ( A_i == 4'd0 ) && (rd_rise/*|wr_rise*/) ) wait_o <= 1'b1;
else if( mem_valid_i | ~mem_busy_i ) wait_o <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__FILL_DIODE_PP_BLACKBOX_V
/**
* fill_diode: Fill diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [41:0] aaa;
wire [41:0] bbb;
// verilator public_module
wire [41:0] z_0;
wire [41:0] z_1;
wide w_0(
.xxx( { {40{1'b0}},2'b11 } ),
.yyy( aaa[1:0] ),
.zzz( z_0 )
);
wide w_1(
.xxx( aaa ),
.yyy( 2'b10 ),
.zzz( z_1 )
);
assign bbb= z_0 + z_1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
aaa <= 42'b01;
end
if (cyc==2) begin
aaa <= 42'b10;
if (z_0 != 42'h4) $stop;
if (z_1 != 42'h3) $stop;
end
if (cyc==3) begin
if (z_0 != 42'h5) $stop;
if (z_1 != 42'h4) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module wide (
input [41:0] xxx,
input [1:0] yyy,
output [41:0] zzz
);
// verilator public_module
assign zzz = xxx+ { {40{1'b0}},yyy };
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2ai (
VPWR,
VGND,
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire nand1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
/**
* lsbufhv2lv_simple: Level shifting buffer, High Voltage to Low
* Voltage, simple (hv devices in inverters on lv
* power rail).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv_simple (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_SIMPLE_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, x[1042], y[1042]; double eps = 0.00000001; int dist2(int x1, int y1, int x2, int y2) { return (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); } double dist(double x1, double y1, double x2, double y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } int cross(int a, int b, int c) { return (x[a] - x[b]) * (y[c] - y[b]) - (x[c] - x[b]) * (y[a] - y[b]); } bool acute(int a, int b, int c) { if (cross(a, b, c) == 0) { return 0; } int dAB = dist2(x[a], y[a], x[b], y[b]); int dBC = dist2(x[b], y[b], x[c], y[c]); int dAC = dist2(x[a], y[a], x[c], y[c]); if (dAB >= dBC + dAC) { return 0; } if (dAC >= dBC + dAB) { return 0; } if (dBC >= dAC + dAB) { return 0; } return 1; } bool r(int a, int b, int c) { int dAB = dist2(x[a], y[a], x[b], y[b]); int dBC = dist2(x[b], y[b], x[c], y[c]); int dAC = dist2(x[a], y[a], x[c], y[c]); if (dAB == dBC + dAC) { return 1; } if (dAC == dBC + dAB) { return 1; } if (dBC == dAC + dAB) { return 1; } return 0; } bool covered(double cx, double cy, double t) { for (int i = 0; i < n; i++) { if (dist(cx, cy, x[i], y[i]) < t) { return 1; } } return 0; } pair<double, double> getCirC(int a, int b, int c) { int dx1 = x[a] - x[b], dx2 = x[b] - x[c], dx3 = x[c] - x[a]; int dy1 = y[a] - y[b], dy2 = y[b] - y[c], dy3 = y[c] - y[a]; double xc1 = (x[a] + x[b]) / 2., xc2 = (x[b] + x[c]) / 2., xc3 = (x[c] + x[a]) / 2.; double yc1 = (y[a] + y[b]) / 2., yc2 = (y[b] + y[c]) / 2., yc3 = (y[c] + y[a]) / 2.; if (dy1 == 0) { swap(dx1, dx3); swap(dy1, dy3); swap(xc1, xc3); swap(yc1, yc3); } if (dy2 == 0) { swap(dx2, dx3); swap(dy2, dy3); swap(xc2, xc3); swap(yc2, yc3); } double n1 = -1. * dx1 / (double)dy1, n2 = -1. * dx2 / (double)dy2; double x = (yc2 - yc1 + n1 * xc1 - n2 * xc2) / (n1 - n2); double y = n1 * (x - xc1) + yc1; return make_pair(x, y); } int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x[i] >> y[i]; } double ans = -1; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { for (int k = j + 1; k < n; k++) { if (acute(i, j, k)) { pair<double, double> crr = getCirC(i, j, k); double px = crr.first, py = crr.second; double d = dist(px, py, x[i], y[i]); if (!covered(px, py, d - eps)) { ans = max(ans, d); } } } } } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { vector<int> ids; ids.clear(); for (int k = 0; k < n; k++) { if (k == i || k == j) { continue; } if (dist2(x[i], y[i], x[k], y[k]) != dist2(x[j], y[j], x[k], y[k])) { continue; } if (!r(i, j, k)) { continue; } ids.push_back(k); } if (ids.size() < 2) { continue; } int k = ids[0]; int cc = ids[1]; double px = (x[i] + x[j] + x[k] + x[cc]) / 4.; double py = (y[i] + y[j] + y[k] + y[cc]) / 4.; double d = dist(x[i], y[i], px, py); if (!covered(px, py, d - eps)) { ans = max(ans, d); } } } cout << ans << n ; return 0; } |
module scheduler1(clk, reset, wen, enablein, datain, dataout, full, empty, enableout);
parameter data_width = 32;
//parameter data_width1 = 34;
//
parameter data_width1 = 36;
parameter address_width = 5;
parameter FIFO_depth = 1024;
input clk,reset,wen,enablein;
input [data_width-1:0] datain;
output [data_width1-1:0] dataout;
output full,empty;
output enableout;
reg[31:0] write_p,read_p;
reg[address_width:0] counter;
reg[data_width-1:0] dataout1;
wire[data_width1-1:0] dataout;
reg [data_width-1:0] memory[FIFO_depth-1:0];
reg[data_width-1:0] keywordnumber,textfilenumber;
reg enableout1;
reg[3:0] routeraddress;
reg wen1;
reg [data_width-1:0] datain1;
reg ren;
reg counter1;
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
wen1=0;
else
if(wen)
wen1=1;
else
//if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
wen1=0;
else
wen1=wen1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
ren=0;
else
//if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
ren=1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter1=0;
else
if(wen&&counter1<2)
counter1=counter1+1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
dataout1=dataout1+1;
// Added by me.
else
dataout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
//routeraddress=0;
routeraddress=4'b0000;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
//routeraddress=2;
routeraddress=4'b0001;
else
if(ren&&(read_p<write_p)&&(write_p<FIFO_depth-1))
//routeraddress=1;
routeraddress=4'b1001;
else
//routeraddress=0;
routeraddress=4'b0000;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
enableout1=0;
else
if(wen1)
enableout1=1;
else
if(ren&&(read_p<write_p))
enableout1=1;
else
enableout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
read_p=2;
else if(ren&&(read_p<write_p)&&(read_p<FIFO_depth))
read_p=read_p+1;
else
read_p=read_p;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else if(ren&&(read_p<=write_p)&&(enableout1==1))
dataout1=memory[read_p];
end
//*************
reg end_f;
always@(posedge clk or negedge reset)
if(!reset)
end_f <= 0;
else if(datain == 32'hffffffff)
end_f <= 1'b1;
else
end_f <= end_f;
//*************
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
write_p=0;
else
if(enablein&&(write_p<FIFO_depth-1)&&(end_f==0))
write_p=write_p+1;
else
write_p=write_p;
end
always@(posedge clk)
begin
if(wen1&&enablein==1)
memory[write_p]=datain;
datain1=datain;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter=0;
else if(wen1&&!ren&&(counter!=FIFO_depth))
counter=counter+1;
else if(ren&&!wen1&&(counter!=0))
counter=counter-1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
keywordnumber=0;
else if (write_p>=3)
keywordnumber=memory[2];
else
keywordnumber=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
textfilenumber=0;
else if (write_p>=4)
textfilenumber=memory[3];
else
textfilenumber=0;
end
assign full=(counter==(FIFO_depth-1));
assign empty=(counter==0);
//
//assign dataout[31:0]=dataout1;
//assign dataout[33:32]=routeraddress;
assign dataout[35:4]=dataout1;
assign dataout[3:0]=routeraddress;
//
assign enableout=enableout1;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_dp_macb_l.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_dp_macb_l(/*AUTOARG*/
// Outputs
data_out_cx_l, scan_out, shiftenable_buf,
// Inputs
arb_cpxdp_qsel1_ca, arb_cpxdp_qsel0_ca, arb_cpxdp_grant_ca,
arb_cpxdp_shift_cx, arb_cpxdp_q0_hold_ca, src_cpx_data_ca,
data_prev_cx_l, rclk, scan_in, shiftenable
);
output [149:0] data_out_cx_l; // cpx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_cpxdp_qsel1_ca; // queue write sel
input arb_cpxdp_qsel0_ca; // queue write sel
input arb_cpxdp_grant_ca;//grant signal
input arb_cpxdp_shift_cx;//grant signal
input arb_cpxdp_q0_hold_ca;//grant signal
input [149:0] src_cpx_data_ca; // scache to cpx data
input [149:0] data_prev_cx_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_cx;
wire [149:0] q0_datain_ca;
wire [149:0] q1_dataout, q0_dataout;
wire [149:0] data_cx_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
//HEADER SECTION
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
/*
always @ (clk or arb_cpxdp_qsel1_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq1 = arb_cpxdp_qsel1_ca ;
end // always @ (clk or arb_cpxdp_qsel1_ca or tmb)
assign clkq1 = clkenq1 & clk;
always @ (clk or arb_cpxdp_q0_hold_ca )
begin
if (!clk) //latch opens on rclk low phase
clkenq0 = !arb_cpxdp_q0_hold_ca ;
end // always @ (clk or arb_cpxdp_q0_hold_ca or tmb)
assign clkq0 = clkenq0 & clk;
*/
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_cpxdp_q0_hold_ca),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_cpxdp_qsel1_ca),
.tmb_l(se_l));
dff_s #(1) dff_cpx_grin_r(
.din (arb_cpxdp_grant_ca),
.q (grant_cx),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(150) dff_cpx_datain_q1(
.din (src_cpx_data_ca[149:0]),
.q (q1_dataout[149:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
assign q0_datain_ca[149:0] =
(arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
(arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
dff_s #(150) dff_cpx_datain_q0(
.din (q0_datain_ca[149:0]),
.q (q0_dataout[149:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_cx_l[149:0] = ~(grant_cx ? q0_dataout[149:0] : 150'd0);
assign data_out_cx_l[149:0] = data_prev_cx_l[149:0] & data_cx_l[149:0];
// Local Variables:
// verilog-library-directories:("." "../../../../../common/rtl")
// End:
// Code start here
//
endmodule
|
module SIS (
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_w_address,
input ram_w_waitrequest,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_w_byteenable,
output wire ram_w_write,
output wire[DATA_WIDTH-1:0] ram_w_writedata,
output wire[BURST_WIDTH_W-1:0] ram_w_burstcount,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
input [23:0] din_data,
input din_valid,
output wire din_ready,
input wire din_sop,
input wire din_eop,
input cpu_clk,
input cpu_rst,
input cpu_clk_en,
input cpu_start,
output wire cpu_done,
input[DATA_WIDTH-1:0] cpu_addr,
input[DATA_WIDTH-1:0] cpu_addw,
output wire[DATA_WIDTH-1:0] cpu_result,
input [1:0] n
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BURST_WIDTH_W = 5;
parameter BURST_WIDTH_R = 6;
parameter BYTE_ENABLE_WIDTH = 4; // derived parameter
parameter FIFO_DEPTH_LOG2 = 8;
wire [DATA_WIDTH-1:0] data_fifo_in;
wire read_fifo_in;
wire start_fifo_in;
wire [ADD_WIDTH-1:0] address_fifo_in;
wire [DATA_WIDTH-1:0] n_burst_fifo_in;
wire bussy_fifo_in;
wire empty_fifo_in;
wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in;
wire [DATA_WIDTH-1:0] data_fifo_out;
wire data_valid_fifo_out;
wire start_fifo_out;
wire [ADD_WIDTH-1:0] address_fifo_out;
wire [DATA_WIDTH-1:0] n_burst_fifo_out;
wire bussy_fifo_out;
wire full_fifo_out;
wire [FIFO_DEPTH_LOG2:0] usedw_fifo_out;
wire [DATA_WIDTH-1:0] data_out_frame_writer;
wire data_out_valid_frame_writer;
wire [DATA_WIDTH-1:0] data_out_agrises;
wire data_out_valid_agrises;
wire [DATA_WIDTH-1:0] data_out_sobel;
wire data_out_valid_sobel;
wire read_agrises;
wire read_sobel;
wire reset_values;
reg [1:0] init;
reg run;
reg valid;
reg [DATA_WIDTH-1:0] bridge;
wire framewriter_end;
wire agrises_end;
wire sobel_end;
wire start_framewriter;
wire start_agrises;
wire start_sobel;
wire[ADD_WIDTH-1:0] agrises_ram_r_address;
wire[BYTE_ENABLE_WIDTH-1:0] agrises_ram_r_byteenable;
wire agrises_ram_r_read;
wire[BURST_WIDTH_R-1:0] agrises_ram_r_burstcount;
wire[ADD_WIDTH-1:0] sobel_ram_r_address;
wire[BYTE_ENABLE_WIDTH-1:0] sobel_ram_r_byteenable;
wire sobel_ram_r_read;
wire[BURST_WIDTH_R-1:0] sobel_ram_r_burstcount;
ram_r ram_r_instance (
.clk(clk),
.rst(rst),
.ram_r_address(agrises_ram_r_address),
.ram_r_waitrequest(ram_r_waitrequest),
.ram_r_readdatavalid(ram_r_readdatavalid),
.ram_r_byteenable(agrises_ram_r_byteenable),
.ram_r_read(agrises_ram_r_read),
.ram_r_readdata(ram_r_readdata),
.ram_r_burstcount(agrises_ram_r_burstcount),
.data_fifo_in(data_fifo_in),
.read_fifo_in(read_fifo_in),
.start_fifo_in(start_fifo_in),
.address_fifo_in(address_fifo_in),
.n_burst_fifo_in(n_burst_fifo_in),
.bussy_fifo_in(bussy_fifo_in),
.empty_fifo_in(empty_fifo_in),
.usedw_fifo_in(usedw_fifo_in)
);
ram_w ram_w_instance (
.clk(clk),
.rst(rst),
.ram_w_address(ram_w_address),
.ram_w_waitrequest(ram_w_waitrequest),
.ram_w_byteenable(ram_w_byteenable),
.ram_w_write(ram_w_write),
.ram_w_writedata(ram_w_writedata),
.ram_w_burstcount(ram_w_burstcount),
.data_fifo_out(data_fifo_out),
.data_valid_fifo_out(data_valid_fifo_out),
.start_fifo_out(start_fifo_out),
.address_fifo_out(address_fifo_out),
.n_burst_fifo_out(n_burst_fifo_out),
.bussy_fifo_out(bussy_fifo_out),
.full_fifo_out(full_fifo_out),
.usedw_fifo_out(usedw_fifo_out)
);
FrameWriter FrameWriter_instance (
.clk(clk),
.rst(rst),
.din_data(din_data),
.din_valid(din_valid),
.din_ready(din_ready),
.din_sop(din_sop),
.din_eop(din_eop),
.data_fifo_out(data_out_frame_writer),
.data_valid_fifo_out(data_out_valid_frame_writer),
.usedw_fifo_out(usedw_fifo_out),
.start(start_framewriter),
.endf(framewriter_end)
);
AGrises AGrises_instance (
.clk(clk),
.rst(rst),
.data_fifo_out(data_out_agrises),
.data_valid_fifo_out(data_out_valid_agrises),
.usedw_fifo_out(usedw_fifo_out),
.data_fifo_in(data_fifo_in),
.read_fifo_in(read_agrises),
.usedw_fifo_in(usedw_fifo_in),
.start(start_agrises),
.endf(agrises_end)
);
Sobel Sobel_instance (
.clk(clk),
.rst(rst),
.data_fifo_out(data_out_sobel),
.data_valid_fifo_out(data_out_valid_sobel),
.usedw_fifo_out(usedw_fifo_out),
.ram_r_address(sobel_ram_r_address),
.ram_r_waitrequest(ram_r_waitrequest),
.ram_r_readdatavalid(ram_r_readdatavalid),
.ram_r_byteenable(sobel_ram_r_byteenable),
.ram_r_read(sobel_ram_r_read),
.ram_r_readdata(ram_r_readdata),
.ram_r_burstcount(sobel_ram_r_burstcount),
.start(start_sobel),
.endf(sobel_end),
.base_add(cpu_addr)
);
// Inicializacion
always @(negedge cpu_clk or posedge cpu_rst) begin
if (cpu_rst == 1) begin
init <= 2'd0;
end else begin
if ((cpu_clk_en == 1) && (cpu_start == 1)) begin
init <= 2'd1;
end else begin
if ((bussy_fifo_out == 0) && (run == 1'd1)) begin
init <= 2'd2;
end else begin
if ((init == 2'd2) && (run == 1'd0)) begin
init <= 2'd3;
end else begin
if (cpu_done == 1) begin
init <= 2'd0;
end
end
end
end
end
end
always @(posedge clk) begin
if (reset_values == 1) begin
run <= 1;
end else begin
if (init == 2'd2) begin
run <= 0;
end
end
end
assign data_fifo_out = (n == 0)? data_out_frame_writer : ((n == 1)? data_out_agrises : data_out_sobel);
assign data_valid_fifo_out = (n == 0)? data_out_valid_frame_writer : ((n == 1)? data_out_valid_agrises : data_out_valid_sobel);
assign start_fifo_out = reset_values;
assign address_fifo_out = cpu_addw;
assign n_burst_fifo_out = 12000;
assign read_fifo_in = (n == 0)? 0 : ((n == 1)? read_agrises : read_sobel);
assign start_fifo_in = reset_values;
assign address_fifo_in = cpu_addr;
assign n_burst_fifo_in = (n != 1)? 0 : 12000;
assign ram_r_address = (n == 1)? agrises_ram_r_address : sobel_ram_r_address;
assign ram_r_byteenable = (n == 1)? agrises_ram_r_byteenable : sobel_ram_r_byteenable;
assign ram_r_read = (n == 1)? agrises_ram_r_read : sobel_ram_r_read;
assign ram_r_burstcount = (n == 1)? agrises_ram_r_burstcount : sobel_ram_r_burstcount;
assign start_framewriter = (reset_values == 1) & (n == 0);
assign start_agrises = (reset_values == 1) & (n == 1);
assign start_sobel = (reset_values == 1) & (n == 2);
assign reset_values = ((init == 1) & (run == 0));
assign cpu_done = (init == 2'd3);
assign cpu_result = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 2000000000000000000LL; const int inf = 0x3f3f3f3f; const long double EPS = 1e-9; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long x, i, j, n = 0, t; cin >> x; while (x / 2 != 0) { if (x % 2 == 1) n++; x = x / 2; } cout << n + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long a1, b1, a2, b2; int main() { cin >> a1 >> b1 >> a2 >> b2; long long t1, t2, t3, t4; t1 = a1 * b1; t2 = a2 * b2; int c12, c13; int c22, c23; c12 = c13 = c22 = c23 = 0; while (t1 % 2LL == 0LL) { c12++; t1 /= 2LL; } while (t1 % 3LL == 0LL) { c13++; t1 /= 3LL; } while (t2 % 2LL == 0LL) { c22++; t2 /= 2LL; } while (t2 % 3LL == 0LL) { c23++; t2 /= 3LL; } if (t1 != t2) { cout << -1 << endl; return 0; } int d13, d23; int d12, d22; d13 = d23 = 0; while (c13 > c23) c13--, c12++, d13++; while (c23 > c13) c23--, c22++, d23++; d12 = d22 = 0; if (c12 > c22) d12 = c12 - c22; else d22 = c22 - c12; cout << d12 + d22 + d23 + d13 << endl; while (d13) { if (a1 % 3 == 0) { a1 /= 3LL; a1 *= 2LL; } else { b1 /= 3LL; b1 *= 2LL; } d13--; } while (d12) { if (a1 % 2LL == 0) { a1 /= 2LL; } else { b1 /= 2LL; } d12--; } while (d23) { if (a2 % 3 == 0) { a2 /= 3LL; a2 *= 2LL; } else { b2 /= 3LL; b2 *= 2LL; } d23--; } while (d22) { if (a2 % 2 == 0) { a2 /= 2LL; } else { b2 /= 2LL; } d22--; } cout << a1 << << b1 << endl; cout << a2 << << b2 << endl; ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = INT_MAX; const int mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int arr[2][n]; int sum[2][n]; for (int i = 0; i < 2; i++) { for (int j = 0; j < n; j++) { cin >> arr[i][j]; if (j == 0) sum[i][j] = arr[i][j]; else sum[i][j] = sum[i][j - 1] + arr[i][j]; } } int move1 = sum[0][n - 1]; int move2 = sum[1][n - 1]; int ans = min(move1 - arr[0][0], move2 - arr[1][n - 1]); for (int i = 1; i < n; i++) { int temp1 = move1 - sum[0][i]; int temp2 = sum[1][i - 1]; ans = min(ans, max(temp1, temp2)); } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; string t; vector<string> query(3); void ask(string &q) { cout << ? << q << n ; fflush(stdout); cin >> q; } int main() { ios_base::sync_with_stdio(false); ; cin >> t; for (int i = 0; i < t.length(); i++) { query[0] += (char)( a + (i % 26)); query[1] += (char)( a + ((i % (26 * 26)) / (26))); query[2] += (char)( a + (i % (26 * 26 * 26)) / (26 * 26)); } ask(query[0]); ask(query[1]); ask(query[2]); string ans(t.length(), ); for (int i = 0; i < t.length(); i++) { int pos = (query[0][i] - a ) + (query[1][i] - a ) * 26 + (query[2][i] - a ) * 26 * 26; ans[pos] = t[i]; } cout << ! << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/02/13 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= 1'b0;
data1 <= 1'b0;
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mx(long long a, long long b) { return a >= b ? a : b; } long long mn(long long a, long long b) { return a <= b ? a : b; } string a[3] = {( twone ), ( two ), ( one )}; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t, x; cin >> t; while (t--) { string str, str2; long long ans = 0; vector<long long> v; cin >> str; if (str.size() <= 2) { cout << 0 << n << n ; continue; } for (long long i = 0; i < str.size() - 2; i++) { if (str[i] == t and str[i + 1] == w and str[i + 2] == o and str[i + 3] == n and str[i + 4] == e ) str[i + 2] = l , ans++, v.push_back(i + 3); if (str[i] == t and str[i + 1] == w and str[i + 2] == o ) ans++, str[i + 1] = l , v.push_back(i + 2); if (str[i] == o and str[i + 1] == n and str[i + 2] == e ) ans++, str[i + 1] = l , v.push_back(i + 2); } cout << ans << n ; for (long long i = 0; i < v.size(); i++) cout << v[i] << ; cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, temp; cin >> n; long long int sum = 0, sum2 = 0; for (int i = 0; i < n; i++) { cin >> temp; sum += temp; } for (int i = 0; i < n - 1; i++) { cin >> temp; sum2 += temp; } cout << sum - sum2 << endl; sum = 0; for (int i = 0; i < n - 2; i++) { cin >> temp; sum += temp; } cout << sum2 - sum; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sc_0_1_dbg_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sc_0_1_dbg_rptr(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
// file: ddr3_clkgen_exdes.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module ddr3_clkgen_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [3:1] CLK_OUT,
// High bits of counters driven by clocks
output [3:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 3;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
ddr3_clkgen clknetwork
(// Clock in ports
.clk50in (CLK_IN1),
// Clock out ports
.clk50 (clk_int[1]),
.clk400 (clk_int[2]),
.clk100 (clk_int[3]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
assign CLK_OUT = clk_int;
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
assign clk[3] = clk_int[3];
// Reset synchronizer
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen]<= 1'b1;
rst_sync_int1[count_gen]<= 1'b1;
rst_sync_int2[count_gen]<= 1'b1;
end
else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
`define CYCLE_TIME 50
module TestBench;
reg Clk;
reg Reset;
reg Start;
integer i, outfile, outfile2, counter;
reg flag;
reg [26:0] address;
reg [23:0] tag;
reg [4:0] index;
wire [256-1:0] mem_cpu_data;
wire mem_cpu_ack;
wire [256-1:0] cpu_mem_data;
wire [32-1:0] cpu_mem_addr;
wire cpu_mem_enable;
wire cpu_mem_write;
always #(`CYCLE_TIME/2) Clk = ~Clk;
CPU CPU(
.clk (Clk),
.rst (Reset),
.start(Start),
.ReadData(mem_cpu_data),
.MemAck(mem_cpu_ack),
.WriteData(cpu_mem_data),
.MemAddr(cpu_mem_addr),
.MemEnable(cpu_mem_enable),
.MemWrite(cpu_mem_write)
);
Data_Memory Data_Memory
(
.clk_i(Clk),
.rst_i (Reset),
.addr_i(cpu_mem_addr),
.data_i(cpu_mem_data),
.enable_i(cpu_mem_enable),
.write_i(cpu_mem_write),
.ack_o(mem_cpu_ack),
.data_o(mem_cpu_data)
);
initial begin
counter = 0;
// initialize instruction memory (2KB)
for(i=0; i<512; i=i+1) begin
CPU.InstrMem.memory[i] = 32'b0;
end
// initialize data memory (16KB)
for(i=0; i<512; i=i+1) begin
Data_Memory.memory[i] = 256'b0;
end
// initialize cache memory (1KB)
for(i=0; i<32; i=i+1) begin
CPU.dcache.dcache_tag_sram.memory[i] = 24'b0;
CPU.dcache.dcache_data_sram.memory[i] = 256'b0;
end
// initialize Register File
for(i=0; i<32; i=i+1) begin
CPU.Registers.register[i] = 32'b0;
end
// Load instructions into instruction memory
$readmemb("instruction.txt", CPU.InstrMem.memory);
// Open output file
outfile = $fopen("output.txt") | 1;
outfile2 = $fopen("cache.txt") | 1;
// Set Input n into data memory at 0x00
Data_Memory.memory[0] = 256'h5; // n = 5 for example
Clk = 1;
Start = 0;
Reset = 0;
#(`CYCLE_TIME/2)
Start = 1;
Reset = 1;
end
always@(posedge Clk) begin
if(counter == 150) begin // store cache to memory
$fdisplay(outfile, "Flush Cache! \n");
for(i=0; i<32; i=i+1) begin
tag = CPU.dcache.dcache_tag_sram.memory[i];
index = i;
address = {tag[21:0], index};
Data_Memory.memory[address] = CPU.dcache.dcache_data_sram.memory[i];
end
end
if(counter > 150) begin // stop
$stop;
end
$fdisplay(outfile, "cycle = %d, Start = %b", counter, Start);
// print PC
$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
//$fdisplay(outfile, "PC = %d (%b,%d)", CPU.PC.pc_o,CPU.MemStall,CPU.dcache.state);
/* $fdisplay(outfile, "%b %b %b",CPU.Control_MEM,
CPU.Control.Op,CPU.Control.MemWrite);
$fdisplay(outfile, "$ = %d %b %b %b %b",CPU.dcache.state,
CPU.dcache.sram_cache_tag,CPU.dcache.cache_sram_tag,
CPU.dcache.cache_sram_enable,CPU.dcache.p1_req);*/
// print Registers
$fdisplay(outfile, "Registers");
$fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", CPU.Registers.register[0], CPU.Registers.register[8] , CPU.Registers.register[16], CPU.Registers.register[24]);
$fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", CPU.Registers.register[1], CPU.Registers.register[9] , CPU.Registers.register[17], CPU.Registers.register[25]);
$fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", CPU.Registers.register[2], CPU.Registers.register[10], CPU.Registers.register[18], CPU.Registers.register[26]);
$fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", CPU.Registers.register[3], CPU.Registers.register[11], CPU.Registers.register[19], CPU.Registers.register[27]);
$fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", CPU.Registers.register[4], CPU.Registers.register[12], CPU.Registers.register[20], CPU.Registers.register[28]);
$fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", CPU.Registers.register[5], CPU.Registers.register[13], CPU.Registers.register[21], CPU.Registers.register[29]);
$fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", CPU.Registers.register[6], CPU.Registers.register[14], CPU.Registers.register[22], CPU.Registers.register[30]);
$fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", CPU.Registers.register[7], CPU.Registers.register[15], CPU.Registers.register[23], CPU.Registers.register[31]);
// print Data Memory
$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
$fdisplay(outfile, "Data Memory: 0x0060 = %h", Data_Memory.memory[3]);
$fdisplay(outfile, "Data Memory: 0x0080 = %h", Data_Memory.memory[4]);
$fdisplay(outfile, "Data Memory: 0x00A0 = %h", Data_Memory.memory[5]);
$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
$fdisplay(outfile, "\n");
// print Data Cache Status
if(CPU.dcache.p1_stall_o && CPU.dcache.state==0) begin
if(CPU.dcache.sram_dirty) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
else begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b1;
end
else if(!CPU.dcache.p1_stall_o) begin
if(!flag) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Hit , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b0;
end
counter = counter + 1;
end
endmodule
|
module flash_writer(
input p_ready,
input WE_CLK,
input iFLASH_RY_N,
input iOSC_28 ,
input iERASE ,
input iPROGRAM ,
input iVERIFY ,
input iOK ,
input iFAIL,
input iRESET_N ,
output oREAD_PRO_END,
output oVERIFY_TIME,
output [21:0] oFLASH_ADDR,
output reg [3:0] oFLASH_CMD,
output oFLASH_TR
);
//flash rom command//
always @(posedge iOSC_28)begin
case ({iFAIL,iOK,iRESET_N,iVERIFY,iPROGRAM,iERASE})
6'b000100: oFLASH_CMD = 4'h0; //read
6'b000001: oFLASH_CMD = 4'h4; //iERASE
6'b000010: oFLASH_CMD = 4'h1; //prog
6'b001000: oFLASH_CMD = 4'h7; //reset
6'b010000: oFLASH_CMD = 4'h8; //ok
6'b100000: oFLASH_CMD = 4'h9; //fail
endcase
end
//time scal //
reg [31:0]delay;
always @(posedge iOSC_28)begin
delay <= delay+1;
end
wire ck_prog = delay[5]; // program time 8 6
wire ck_read = delay[4]; // verify time //
wire [21:0]end_address;
assign end_address = 22'h3fffff; //end address//
// PROGRAM ADDRESS COUNTER //
reg [21:0]addr_prog;
reg end_prog;
reg PROGRAM_TR_r;
reg [7:0]ST_P;
always @(posedge iRESET_N or posedge ck_prog ) begin
if (iRESET_N) begin
addr_prog <= end_address;
end_prog <= 1;
ST_P <= 9; //end_st
PROGRAM_TR_r <= 0;
end
else if (iPROGRAM) begin
addr_prog <= 0;
end_prog <= 0;
ST_P <= 0;
PROGRAM_TR_r<= 0;
end
else begin
case ( ST_P )
0:begin
ST_P <= ST_P + 1;
PROGRAM_TR_r <=1 ;
end
1:begin
ST_P <= 4;//ST_P + 1;
PROGRAM_TR_r <=0;
end
2:begin
ST_P <= ST_P + 1;
//PROGRAM_TR_r <=0;
end
3:begin
ST_P <= ST_P + 1;
end
4:begin
ST_P <= ST_P + 1;
end
5:begin
if ( iFLASH_RY_N ) ST_P <= 7;//ST_P + 1;
end
6:begin
ST_P <= ST_P + 1;
end
7:begin
if (addr_prog == end_address )
ST_P <= 9;
else
begin
addr_prog <= addr_prog + 1;
ST_P <= 0;
end
end
8:begin
addr_prog <= addr_prog + 1;
ST_P <= 0;
end
9:begin // end_st
end_prog <= 1;
end
endcase
end
end
// Verify Address Counter //
reg [21:0]addr_read;
reg end_read;
always @(posedge iRESET_N or posedge ck_read) begin
if ( iRESET_N ) begin
addr_read <= end_address;
end_read <= 1;
end
else if (iVERIFY) begin
addr_read <= 0;
end_read <= 0;
end
else if (addr_read<end_address)
addr_read=addr_read+1;
else if (addr_read == end_address) end_read <= 1;
end
//flash address switch//
assign oFLASH_ADDR = (
(oFLASH_CMD==4'h1)? addr_prog: (
(oFLASH_CMD==4'h0)? addr_read: 0
));
wire erase_tr = (iERASE)?1:0; // erase trigger signal
wire porgram_tr= PROGRAM_TR_r ; //program trigger signal
wire verify_tr = (addr_read < end_address)?~ck_read : 0; //read trigger signal
assign oFLASH_TR = erase_tr | porgram_tr | verify_tr; // flash trigger signal
assign oREAD_PRO_END = end_read & end_prog;
assign oVERIFY_TIME = ~end_read ;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long x, y, m; int main() { cin >> x >> y >> m; if (x >= m || y >= m) cout << 0 << n ; else { if (x <= 0 && y <= 0) cout << -1 << n ; else { long long cc = 0; if (x > y) swap(x, y); if (x < 0) { cc += x >= 0 ? x : -x / y; x += y * (long long)cc; } while (x < m && y < m) { if (x < y) x = x + y; else y = x + y; cc++; } cout << cc << n ; } } } |
module foo;
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif
// instead of:
`ifdef LABEL_A
CHIP CPU (
.clkin(clkin),
`ifdef LABEL_B
.bclko(bclko),
`endif
.cmode(cmode),
);
input sysclk;
`ifdef LABEL_B
input bclko;
`endif
input cmode;
`endif // `ifdef LABEL_A
reg a,b;
`ifdef A
always @(a) begin
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
b = a; // asfSDfsdfsasa //
end
`elsif B
always @(b) begin
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa
a = b; // asfSDfsdfsasa //
end
`else // !`elsif B
always @(a or b) begin
a <= b;
b <= a;
end
`endif // !`elsif B
endmodule // foo
|
#include <bits/stdc++.h> using namespace std; char F1[2000000]; char F2[2000000]; void computeLPSArray(string pat, int M, int* lps); void KMPSearch(string pat, string txt, vector<int>& st, vector<int>& end) { int M = pat.size(); int N = txt.size(); int lps[M]; computeLPSArray(pat, M, lps); int i = 0; int j = 0; while (i < N) { if (pat[j] == txt[i]) { j++; i++; } if (j == M) { end.push_back(i - 1); st.push_back(i - M); j = lps[j - 1]; } else if (i < N && pat[j] != txt[i]) { if (j != 0) j = lps[j - 1]; else i = i + 1; } } } void computeLPSArray(string pat, int M, int* lps) { int len = 0; lps[0] = 0; int i = 1; while (i < M) { if (pat[i] == pat[len]) { len++; lps[i] = len; i++; } else { if (len != 0) { len = lps[len - 1]; } else { lps[i] = 0; i++; } } } } long long int Stoi(string s) { long long int ans = 0; for (int i = 0; i < s.size(); i++) ans = ans * 10 + s[i] - 0 ; return ans; } string itos(long long int num) { if (num == 0) return 0 ; string ans = ; while (num) { int digit = num % 10; char ch = 0 + digit; ans = ch + ans; num = num / 10; } return ans; } long long int numBefore(int i, string& s) { int indx = i - 1; while (s[indx] >= 0 && s[indx] <= 9 && indx >= 0) indx--; indx++; int len = i - indx; long long int num = Stoi(s.substr(indx, len)); return num; } int charAfter(int i, string& s) { if (i == s.size() - 1) return -1; int indx = i + 1; while (s[indx] >= 0 && s[indx] <= 9 && indx >= 0) indx++; return indx; } int main() { int m, n; cin >> n >> m; long long int prevFreq = 0; char prevCh = Q ; string Final = ; int ptr1 = 0, ptr2 = 0; for (int i = 0; i < n; i++) { string s; cin >> s; int size = s.size(); int indx = size - 2; ; string num1 = s.substr(0, indx); long long int frq = Stoi(num1); char Chr = s[indx + 1]; if (Chr == prevCh) prevFreq += frq; else { if (prevCh != Q ) { string s1 = itos(prevFreq) + prevCh; for (int i = 0; i < s1.size(); i++) { F1[ptr1] = s1[i]; ptr1++; } } prevFreq = frq; prevCh = Chr; } } string s1 = itos(prevFreq) + prevCh; for (int i = 0; i < s1.size(); i++) { F1[ptr1] = s1[i]; ptr1++; } F1[ptr1] = 0; Final = F1; prevFreq = 0; prevCh = Q ; string Final2 = ; for (int i = 0; i < m; i++) { string s; cin >> s; int indx = s.find( - ); string num1 = s.substr(0, indx); long long int frq = Stoi(num1); char Chr = s[indx + 1]; if (Chr == prevCh) prevFreq += frq; else { if (prevCh != Q ) { string s2 = itos(prevFreq) + prevCh; for (int i = 0; i < s2.size(); i++) { F2[ptr2] = s2[i]; ptr2++; } } prevFreq = frq; prevCh = Chr; } } string s2 = itos(prevFreq) + prevCh; for (int i = 0; i < s2.size(); i++) { F2[ptr2] = s2[i]; ptr2++; } Final2 = F2; vector<int> st, end; int indx = 0; int indx2 = Final2.size() - 2; while (Final2[indx] >= 0 && Final2[indx] <= 9 ) indx++; while (indx2 >= 0 && Final2[indx2] >= 0 && Final2[indx2] <= 9 ) indx2--; long long int ans = 0; if (indx2 >= 0) { string toSrch = Final2.substr(indx, indx2 - indx + 1); KMPSearch(toSrch, Final, st, end); for (int i = 0; i < st.size(); i++) { long long int Aval = numBefore(st[i], Final); long long int Req = numBefore(indx, Final2); int i2 = charAfter(end[i], Final); int i3 = charAfter(indx2, Final2); if (i2 >= 0 && i3 >= 0 && Final2[i3] == Final[i2]) { long long int Aval2 = numBefore(i2, Final); long long int Req2 = numBefore(i3, Final2); if (Aval >= Req && Aval2 >= Req2) ans++; } } } else { char ch = Final2[Final2.size() - 1]; for (int i = 0; i < Final.size(); i++) { if (Final[i] == ch) { long long int Aval = numBefore(i, Final); long long int Req = numBefore(Final2.size() - 1, Final2); if (Aval >= Req) ans = ans + (Aval - Req + 1); } } } cout << ans << endl; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] par1; // From a1 of t_param_first_a.v
wire [4:0] par2; // From a2 of t_param_first_a.v
wire [4:0] par3; // From a3 of t_param_first_a.v
wire [4:0] par4; // From a4 of t_param_first_a.v
wire [1:0] varwidth1; // From a1 of t_param_first_a.v
wire [2:0] varwidth2; // From a2 of t_param_first_a.v
wire [3:0] varwidth3; // From a3 of t_param_first_a.v
wire [3:0] varwidth4; // From a4 of t_param_first_a.v
// End of automatics
/*t_param_first_a AUTO_TEMPLATE (
.par (par@[]));
.varwidth (varwidth@[]));
*/
parameter XX = 2'bXX;
parameter THREE = 3;
t_param_first_a #(1,5) a1
(
// Outputs
.varwidth (varwidth1[1:0]),
/*AUTOINST*/
// Outputs
.par (par1[4:0])); // Templated
t_param_first_a #(2,5) a2
(
// Outputs
.varwidth (varwidth2[2:0]),
/*AUTOINST*/
// Outputs
.par (par2[4:0])); // Templated
t_param_first_a #(THREE,5) a3
(
// Outputs
.varwidth (varwidth3[3:0]),
/*AUTOINST*/
// Outputs
.par (par3[4:0])); // Templated
t_param_first_a #(THREE,5) a4
(
// Outputs
.varwidth (varwidth4[3:0]),
/*AUTOINST*/
// Outputs
.par (par4[4:0])); // Templated
parameter THREE_BITS_WIDE = 3'b011;
parameter THREE_2WIDE = 2'b11;
parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
parameter THREEPP_32_WIDE = 2*8*2+3;
parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide
// Width propagation doesn't care about LHS vs RHS
// But the width of a RHS/LHS on a upper node does affect lower nodes;
// Thus must double-descend in width analysis.
// VCS 7.0.1 is broken on this test!
parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop;
parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop;
// Parameters assign LHS is affectively width zero.
parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop;
parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop;
// Must be careful about LSB's with extracts
parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop;
//
parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3;
parameter THREE_32_WIDE = 3%32;
parameter THIRTYTWO = 2; // Param is 32 bits
parameter [40:0] WIDEPARAM = 41'h12_3456789a;
parameter [40:0] WIDEPARAM2 = WIDEPARAM;
reg [7:0] eightb;
reg [3:0] fourb;
wire [7:0] eight = 8'b00010000;
wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE];
wire [2:0] threebits = ALSO_THREE_WIDE;
// surefire lint_off CWCCXX
initial _ranit = 0;
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_param: Running\n", $time);
//
$write(" %d %d %d\n", par1,par2,par3);
if (par1!==5'd1) $stop;
if (par2!==5'd2) $stop;
if (par3!==5'd3) $stop;
if (par4!==5'd3) $stop;
if (varwidth1!==2'd2) $stop;
if (varwidth2!==3'd2) $stop;
if (varwidth3!==4'd2) $stop;
if (varwidth4!==4'd2) $stop;
if (threebits !== 3'b011) $stop;
if (eight !== 8'b00010000) $stop;
if (eight2two !== 2'b10) $stop;
$write(" Params = %b %b\n %b %b\n",
THREEPP_32_WIDE,THREEPP_3_WIDE,
THIRTYTWO, THREEPP_32P_WIDE);
if (THREEPP_32_WIDE !== 32'h23) $stop;
if (THREEPP_3_WIDE !== 3'h3) $stop;
if (THREEPP_32P_WIDE !== 32'h23) $stop;
if (THIRTYTWO[1:0] !== 2'h2) $stop;
if (THIRTYTWO !== 32'h2) $stop;
if (THIRTYTWO !== 2) $stop;
if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop;
if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop;
if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1
//
// Example of assignment LHS affecting expression widths.
// verilator lint_off WIDTH
// surefire lint_off ASWCMB
// surefire lint_off ASWCBB
eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop;
fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop;
fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop;
// verilator lint_on WIDTH
// surefire lint_on ASWCMB
// surefire lint_on ASWCBB
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> const int mn = 10100, mm = 5010000; char st[mm], ans[mm]; int f[mm], s[mm], L[mn], R[mn]; int n, m, K, i, j, d, len, now; void del(int p) { for (; p <= m; p += p & (-p)) --s[p]; } int query(int v) { int i = 1, l = m >> 1; for (; l; l >>= 1) if (s[i + l - 1] < v) v -= s[i + l - 1], i += l; return i; } int main() { scanf( %s , st + 1); scanf( %d , &K); for (m = 1; m < K; m <<= 1) ; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d%d , L + i, R + i); for (i = 1; i <= m; ++i) s[i] = i & (-i); for (i = n; i >= 1; --i) { if (R[i] >= s[m]) continue; len = R[i] - L[i] + 1, now = L[i] + 1; for (j = 1; j <= len; ++j) { if (R[i] >= s[m]) break; if (now > R[i]) now = L[i]; d = query(R[i] + 1), del(d); f[d] = query(now); now += 2; } } j = 1; for (i = 1; i <= K; ++i) ans[i] = f[i] ? ans[f[i]] : st[j++]; puts(ans + 1); return 0; } |
#include <bits/stdc++.h> int min(int a, int b) { return a < b ? a : b; } int max(int a, int b) { return a > b ? a : b; } unsigned int X; void srand_() { struct timeval tv; gettimeofday(&tv, NULL); X = tv.tv_sec ^ tv.tv_usec | 1; } int rand_() { return (X *= 3) >> 1; } int *ej[1000], eo[1000]; void append(int i, int j) { int o = eo[i]++; if (o >= 2 && (o & o - 1) == 0) ej[i] = (int *)realloc(ej[i], o * 2 * sizeof *ej[i]); ej[i][o] = j; } int aa[1000], bb[1000], ii[1000], n; int compare(int i, int j) { return aa[i] != aa[j] ? aa[i] - aa[j] : i - j; } void sort(int *ii, int l, int r) { while (l < r) { int i = l, j = l, k = r, i_ = ii[l + rand_() % (r - l)], tmp; while (j < k) { int c = compare(ii[j], i_); if (c == 0) j++; else if (c < 0) { tmp = ii[i], ii[i] = ii[j], ii[j] = tmp; i++, j++; } else { k--; tmp = ii[j], ii[j] = ii[k], ii[k] = tmp; } } sort(ii, l, i); l = k; } } char visited[1000]; int qu[1000], cnt; int i_; void dfs1(int i) { int o; if (visited[i] || compare(i, i_) > 0) return; visited[i] = 1; qu[cnt++] = i; for (o = eo[i]; o--;) { int j = ej[i][o]; dfs1(j); } } char add[1000]; int cc[1000][1000]; void dfs2(int p, int i, int c) { int o; for (o = eo[i]; o--;) { int j = ej[i][o]; if (j != p) { if (compare(j, i_) > 0) cc[i_][j] = max(cc[i_][j], c); else dfs2(i, j, min(c + bb[j], 0x3f3f3f3f)); } } } int dp[1000]; int solve(int s) { int g; memset(dp, 0, n * sizeof *dp), dp[0] = s; for (g = 0; g < n; g++) { int i_ = ii[g], x = dp[i_], j; if (x == 0) continue; for (j = 0; j < n; j++) if (compare(i_, j) < 0 && cc[i_][j] != -1) { int c = add[i_] ? min(x + cc[i_][j], 0x3f3f3f3f) : min(s + cc[i_][j], 0x3f3f3f3f); if (c >= aa[j]) dp[j] = max(dp[j], min(c + bb[j], 0x3f3f3f3f)); } } return dp[ii[n - 1]] > 0; } int main() { int t; srand_(); scanf( %d , &t); while (t--) { static int qu_[1000], dd[1000], pp[1000]; int m, g, h, i, j, o, cnt_, lower, upper; scanf( %d%d , &n, &m); aa[0] = 0; for (i = 1; i < n; i++) scanf( %d , &aa[i]), aa[i]++; for (i = 1; i < n; i++) scanf( %d , &bb[i]); for (i = 0; i < n; i++) ej[i] = (int *)malloc(2 * sizeof *ej[i]), eo[i] = 0; for (h = 0; h < m; h++) { scanf( %d%d , &i, &j), i--, j--; append(i, j), append(j, i); } for (i = 0; i < n; i++) ii[i] = i; sort(ii, 0, n); for (g = 0; g < n; g++) { i_ = ii[g]; memset(visited, 0, n * sizeof *visited), cnt = 0; memset(cc[i_], -1, n * sizeof *cc[i_]); dfs1(0); if (visited[i_]) { int tree, p; memset(dd, 0, n * sizeof *dd); memset(pp, -1, n * sizeof *pp); for (h = 0; h < cnt; h++) { i = qu[h]; for (o = eo[i]; o--;) { j = ej[i][o]; if (visited[j]) dd[i]++; } } cnt_ = 0; for (h = 0; h < cnt; h++) { i = qu[h]; if (dd[i] == 1) qu_[cnt_++] = i; } while (cnt_) { i = qu_[--cnt_]; dd[i] = -1; for (o = eo[i]; o--;) { j = ej[i][o]; if (dd[j] > 0) { pp[i] = j; if (--dd[j] == 1) qu_[cnt_++] = j; } } } tree = 1; for (h = 0; h < cnt; h++) { i = qu[h]; if (dd[i] > 0) { tree = 0; break; } } p = -1, i = 0; while (i != -1 && dd[i] <= 0 && i != i_) p = i, i = pp[i]; add[i_] = 1; if (dd[i_] <= 0 && i != i_) dfs2(pp[i_], i_, 0); else if (tree) dfs2(p, i_, 0); else { int c; add[i_] = 0; c = 0; for (i = 0; i != -1 && dd[i] <= 0; i = pp[i]) c = min(c + bb[i], 0x3f3f3f3f); for (h = 0; h < cnt; h++) { i = qu[h]; if (dd[i] > 0) c = min(c + bb[i], 0x3f3f3f3f); } for (p = -1, i = 0; i != -1 && dd[i] <= 0; p = i, i = pp[i]) for (o = eo[i]; o--;) { j = ej[i][o]; if (compare(j, i_) > 0) cc[i_][j] = max(cc[i_][j], c); else if (j != pp[i] && j != p) dfs2(i, j, min(c + bb[j], 0x3f3f3f3f)); } for (h = 0; h < cnt; h++) { i = qu[h]; if (dd[i] > 0) for (o = eo[i]; o--;) { j = ej[i][o]; if (compare(j, i_) > 0) cc[i_][j] = max(cc[i_][j], c); else if (pp[j] == i && j != p) dfs2(i, j, min(c + bb[j], 0x3f3f3f3f)); } } } } } lower = 0, upper = 0x3f3f3f3f; while (upper - lower > 1) { int s = (lower + upper) / 2; if (solve(s)) upper = s; else lower = s; } printf( %d n , upper); for (i = 0; i < n; i++) free(ej[i]); } return 0; } |
module autoinst_bits_lba_gi
// ==xxxxxxx==
// xxxxxxxxx 1997-1998, xxxxx xxx.
// xxx xxxxxx xxxxxxxx
// ****************************************************************** /
// ****************************************************************** /
// xxxxx, xxxxxxxxxxxx
// xxxxxxx: xxx-4080
// xxxxxx: xxx xxxxxxx
// xxxxx: xxxxxxx 16, 1998
// ******************************************************************* /
// ******************************************************************* /
// xxxx xxxx: xxx_xx.x
// xxxxxxxx xxxxxxx:
// $xxx: xxx_xx.x,x $
// xxxxxxxx 1.3 1998/03/06 00:27:00 xxx
// -- xxxxx xxxxxxx xx xx.xxxx xxx xxxxxxxx xxxxxxx.
// -- xxxx xxxxxxxxxxxxx xx xx xxxxxxxxxxx xx xx.x xxx xx.x xx xxxxxxx xxx xxxxxxxxxxx.
// -- xxxx xxxxx xxx xxxxxxxxxxxxx xxx1'x (xxxxxxx xx xxxxx) xx xx.x xxx xxxx xxxxxx
// xxxxxxxxxx.
// -- xxxxx xxxxxxxxxx xxxxxxxx xx xxx xx xxxxxxxxxxx xxx xxxx xxxxxx xxxxxxxxxxxx xxxx.
// -- xx xxx xxxxxxxxx xxx xxxxxx xx xx xx xxx xxxxx xxxxx xx xxxx xxxxxxxx xx xxxx.
// -- xx xx xxxx xxxxxxx xxx xxx xxxx xxxxxx xxxxxx (xxx xxx xxxx) xxx xxx xxxx/xxxx
// xxxxxxxxxx xxxx xxxxxxx.
//
// xxxxxxxx 1.2 1998/03/04 18:58:55 xxx
// xxxxx xxxxxxxxx xxx-xx xxxxxxx xxxxxxx xx xxxx xxxxx.
//
// xxxxxxxx 1.1 1998/02/23 19:31:52 xxx
// xxxxx xxxxx xxxxxx xxx xxxx xxxxx xxxxx xxxxxxxxxx.
//
// ---------------------------------------------------------------
//
// xxxxxxx xxx xxxxxxxxx xxx xxxxx xxx xxxxxxx xxx
//
// xxxx xxxxxx xxxxx xxx xxxxx xxxxxx xxxxxxx/xxxx xxx xxxx
// xx.x xxx xx xx xxxxxxxxx xxxx xxxx.x xxxxxx xx
// xxxx xxx xxxxxxx xx xxx. xx xxxx xxxxates the
// bidir Foo Bus into a chip input for use by li.v
//
// This module also isolates for input to lbsm.v, and drives
// (if so indicated by lbsm.v) the bidir Fooileo Cmd bus.
//
//
(
CLK,
WWADoe,
WWCoe,
WWCmdIfOE,
WWADHold,
iWWADO,
WWCmdI,
WWADI,
WWADB,
WWCmdB
);
/////////////////////////////////////////////////////////////////////
// inputs
input CLK; // LBA clk
// inputs from lbsm.v
input WWADoe; // FooBus Addr/Data OE
input WWCoe; // FooBus Cmd OE
input [8:0] WWCmdIfOE; // FooBus Cmd if enabled
input WWADHold; // FooBus Addr hold
// inputs from li.v
input [31:0] iWWADO; // FooBus Address/Data out next cycle
/////////////////////////////////////////////////////////////////////
// outputs
// outputs to lbsm.v
output [8:0] WWCmdI; // FooBus Command in
// outputs to li.v
output [31:0] WWADI; // FooBus Address/Data in
/////////////////////////////////////////////////////////////////////
// bidirs
// bidirs to/from off-chip
inout [31:0] WWADB; // bidir FooBus addr/data
inout [8:0] WWCmdB; // bidir FooBus command
/////////////////////////////////////////////////////////////////////
// reg's for outputs (some flops, some not)
/////////////////////////////////////////////////////////////////////
// other flops
reg [31:0] WWADIfOE; // FooBus Addr/Data Out if enabled
endmodule
// Local Variables:
// eval:(if (fboundp `verilog-enable-indentation) (verilog-enable-indentation))
// End:
|
#include <bits/stdc++.h> using namespace std; void solve() { long long a, b; cin >> a >> b; long long ans = abs(a - b) / 5; a = abs(a - b) % 5; if (a == 4) cout << ans + 2; if (a == 3) cout << ans + 2; if (a == 2) cout << ans + 1; if (a == 1) cout << ans + 1; if (a == 0) cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.precision(20); long long t = 1; cin >> t; while (t--) { solve(); cout << n ; } cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; int read(); int n; char t[102]; int w[102][102], rnk[102][102], pos[102]; vector<int> p[102]; queue<int> q; void init(int t) { for (int i = 1; i <= n; ++i) { p[i].clear(), p[i + n].clear(); for (int j = 1; j <= n; ++j) p[i].push_back(j + n), p[i + n].push_back(j); sort(p[i].begin(), p[i].end(), [&](int a, int b) { return w[i][a - n] > w[i][b - n] ^ t; }); sort(p[i + n].begin(), p[i + n].end(), [&](int a, int b) { return w[a][i] < w[b][i] ^ t; }); q.push(i), pos[i] = 0, pos[i + n] = n; for (int j = 0; j < n; ++j) rnk[j][p[i][j]] = j, rnk[i + n][p[i + n][j]] = j; } while (!q.empty()) { int u = q.front(), v; while (pos[v = p[u][pos[u]]] < rnk[v][u]) ++pos[u]; if (pos[v] < n) q.push(p[v][pos[v]]); pos[v] = rnk[v][u], q.pop(); } } int main() { for (int T = read(); T; --T) { n = read(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) w[i][j] = read(); puts( B ), fflush(stdout), scanf( %s , t); if (t[0] == I ) for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) w[i][j] = -w[i][j]; int u; for (init((u = read()) > n); ~u; u = read()) printf( %d n , p[u][pos[u]]), fflush(stdout); } return 0; } int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) f = (c == - ) ? -1 : f, c = getchar(); while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x * f; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const long long inf = 1e16; const long long ninf = LLONG_MIN; const double eps = 1e-12; const long long N = 1000005; const double PI = 3.14159265358979323846; const long long LOGN = 19; long long n, m; long long s[N], t[N]; char a[N]; long long dp[(1 << 21)]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) cin >> s[i]; cin >> m; sort(s, s + n); reverse(s, s + n); for (int i = 0; i < m; i++) cin >> a[i] >> t[i]; for (long long mask = (1 << m) - 1; mask >= 0; mask--) { long long done = __builtin_popcount(mask); if (done == m) { dp[mask] = 0; continue; } if (a[done] == p ) { for (int j = 0; j < m; j++) { if ((mask & (1 << j)) == 0) { dp[mask] = (t[done] == 1 ? s[j] : -s[j]) + dp[mask | (1 << j)]; break; } } } else { if (t[done] == 1) { dp[mask] = -inf; for (int j = 0; j < m; j++) { dp[mask] = max(dp[mask], dp[mask | (1 << j)]); } } else { dp[mask] = inf; for (int j = 0; j < m; j++) { dp[mask] = min(dp[mask], dp[mask | (1 << j)]); } } } } cout << dp[0] << n ; return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:31:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_stub.v
// Design : zynq_design_1_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
`timescale 1ns / 1ps
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 19-3-2017
*/
module jt12_mod6
(
input [2:0] in, // only 0 to 5 are valid entries
input [2:0] sum,
output reg [2:0] out // output between 0 to 5
);
reg [3:0] aux;
always @(*) begin
aux <= in+sum;
case( aux )
4'd6: out <= 3'd0;
4'd7: out <= 3'd1;
4'd8: out <= 3'd2;
4'd9: out <= 3'd3;
4'ha: out <= 3'd4;
4'hb: out <= 3'd5;
4'hc: out <= 3'd0;
4'he: out <= 3'd1;
4'hf: out <= 3'd2;
default: out <= aux;
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi embedded syncs data out.
module cf_v2h_vdma (
// hdmi interface
hdmi_fs_toggle,
hdmi_raddr_g,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_be,
vdma_data,
vdma_last,
vdma_ready,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle, // start of frame write address toggle and data
vdma_fs_waddr,
vdma_tpm_oos,
vdma_be_error,
vdma_ovf,
vdma_unf,
// debug signals (chipscope)
debug_data,
debug_trigger);
// hdmi interface
input hdmi_fs_toggle;
input [ 8:0] hdmi_raddr_g;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [ 7:0] vdma_be;
input [63:0] vdma_data;
input vdma_last;
output vdma_ready;
output vdma_wr;
output [ 8:0] vdma_waddr;
output [47:0] vdma_wdata;
output vdma_fs_ret_toggle;
output [ 8:0] vdma_fs_waddr;
output vdma_tpm_oos;
output vdma_be_error;
output vdma_ovf;
output vdma_unf;
// debug signals (chipscope)
output [35:0] debug_data;
output [ 7:0] debug_trigger;
reg vdma_fs_toggle_m1 = 'd0;
reg vdma_fs_toggle_m2 = 'd0;
reg vdma_fs_toggle_m3 = 'd0;
reg vdma_fs = 'd0;
reg [ 8:0] vdma_fs_waddr = 'd0;
reg vdma_fs_ret_toggle = 'd0;
reg vdma_wr = 'd0;
reg [ 8:0] vdma_waddr = 'd0;
reg [47:0] vdma_wdata = 'd0;
reg [22:0] vdma_tpm_data = 'd0;
reg [ 4:0] vdma_tpm_mismatch_count = 'd0;
reg vdma_tpm_oos = 'd0;
reg [ 4:0] vdma_be_count = 'd0;
reg vdma_be_error = 'd0;
reg [ 8:0] vdma_raddr_g_m1 = 'd0;
reg [ 8:0] vdma_raddr_g_m2 = 'd0;
reg [ 8:0] vdma_raddr = 'd0;
reg [ 8:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg [ 4:0] vdma_ovf_count = 'd0;
reg vdma_ovf = 'd0;
reg [ 4:0] vdma_unf_count = 'd0;
reg vdma_unf = 'd0;
wire [47:0] vdma_tpm_data_s;
wire vdma_tpm_mismatch_s;
wire vdma_be_error_s;
wire [ 9:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
// grey to binary conversion
function [8:0] g2b;
input [8:0] g;
reg [8:0] b;
begin
b[8] = g[8];
b[7] = b[8] ^ g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// debug ports
assign debug_data[35:35] = vdma_tpm_oos;
assign debug_data[34:34] = vdma_tpm_mismatch_s;
assign debug_data[33:33] = vdma_ovf_s;
assign debug_data[32:32] = vdma_unf_s;
assign debug_data[31:31] = vdma_almost_full;
assign debug_data[30:30] = vdma_almost_empty;
assign debug_data[29:29] = vdma_fs;
assign debug_data[28:28] = vdma_fs_ret;
assign debug_data[27:27] = vdma_valid;
assign debug_data[26:26] = vdma_ready;
assign debug_data[25:25] = vdma_last;
assign debug_data[24:24] = vdma_be_error_s;
assign debug_data[23: 0] = vdma_data[23:0];
assign debug_trigger[7] = vdma_tpm_mismatch_s;
assign debug_trigger[6] = vdma_ovf_s;
assign debug_trigger[5] = vdma_unf_s;
assign debug_trigger[4] = vdma_fs;
assign debug_trigger[3] = vdma_fs_ret;
assign debug_trigger[2] = vdma_last;
assign debug_trigger[1] = vdma_valid;
assign debug_trigger[0] = vdma_ready;
// get fs from hdmi side, return fs and sof write address back
always @(posedge vdma_clk) begin
vdma_fs_toggle_m1 <= hdmi_fs_toggle;
vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
vdma_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
if (vdma_fs_ret == 1'b1) begin
vdma_fs_waddr <= vdma_waddr;
vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
end
end
// vdma write
always @(posedge vdma_clk) begin
vdma_wr <= vdma_valid & vdma_ready;
if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
end
// test error conditions
assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
assign vdma_tpm_mismatch_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
assign vdma_be_error_s = (vdma_be == 8'hff) ? 1'b0 : (vdma_valid & vdma_ready);
always @(posedge vdma_clk) begin
if (vdma_fs_ret == 1'b1) begin
vdma_tpm_data <= 23'd0;
end else if (vdma_wr == 1'b1) begin
vdma_tpm_data <= vdma_tpm_data + 1'b1;
end
if (vdma_tpm_mismatch_s == 1'b1) begin
vdma_tpm_mismatch_count <= 5'h10;
end else if (vdma_tpm_mismatch_count[4] == 1'b1) begin
vdma_tpm_mismatch_count <= vdma_tpm_mismatch_count + 1'b1;
end
vdma_tpm_oos <= vdma_tpm_mismatch_count[4];
if (vdma_be_error_s == 1'b1) begin
vdma_be_count <= 5'h10;
end else if (vdma_be_count[4] == 1'b1) begin
vdma_be_count <= vdma_be_count + 1'b1;
end
vdma_be_error <= vdma_be_count[4];
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < 3) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > 509) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk) begin
vdma_raddr_g_m1 <= hdmi_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[8:0];
if (vdma_addr_diff >= 500) begin
vdma_ready <= 1'b0;
end else if (vdma_addr_diff <= 450) begin
vdma_ready <= 1'b1;
end
vdma_almost_full = (vdma_addr_diff > 509) ? 1'b1 : 1'b0;
vdma_almost_empty = (vdma_addr_diff < 3) ? 1'b1 : 1'b0;
if (vdma_ovf_s == 1'b1) begin
vdma_ovf_count <= 5'h10;
end else if (vdma_ovf_count[4] == 1'b1) begin
vdma_ovf_count <= vdma_ovf_count + 1'b1;
end
vdma_ovf <= vdma_ovf_count[4];
if (vdma_unf_s == 1'b1) begin
vdma_unf_count <= 5'h10;
end else if (vdma_unf_count[4] == 1'b1) begin
vdma_unf_count <= vdma_unf_count + 1'b1;
end
vdma_unf <= vdma_unf_count[4];
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; long long int power(long long int a, long long int x) { long long int res = 1; while (x > 0) { if (x & 1) { res *= a; } a *= a; x = x / 2; } return res; } int main() { long long int n; scanf( %lld , &n); long long int ans = 0; ans = power(4, n - 2) * 6; if (n > 3) { ans += (n - 3) * 4 * 9 * power(4, n - 4); } printf( %lld n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s18.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__clkdlybuf4s18 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_TB_V
|
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9, PI = acos(-1.); const int INF = 0x3f3f3f3f, MOD = 1e9 + 7; const int N = 2e5 + 5, SQ = 500; int n, q, a[N], l[N], r[N], p[N]; long long ans[N], c[1000005], s; void add(int x) { int v = a[x]; s -= c[v] * c[v] * v; c[v]++; s += c[v] * c[v] * v; } void rem(int x) { int v = a[x]; s -= c[v] * c[v] * v; c[v]--; s += c[v] * c[v] * v; } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 0; i < q; ++i) scanf( %d%d , &l[i], &r[i]), p[i] = i; sort(p, p + q, [](int a, int b) { return l[a] / SQ == l[b] / SQ ? r[a] < r[b] : l[a] < l[b]; }); int cl = 0, cr = 0; for (int i = 0; i < q; ++i) { int cur = p[i]; while (cl < l[cur]) rem(cl++); while (cl > l[cur]) add(--cl); while (cr < r[cur]) add(++cr); while (cr > r[cur]) rem(cr--); ans[cur] = s; } for (int i = 0; i < q; ++i) printf( %lld n , ans[i]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O32A_PP_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const double eps = 1e-9; const long long INF = 1000000000; const int MAXN = 128; int points[] = {0, 25, 18, 15, 12, 10, 8, 6, 4, 2, 1}; int t, n; map<string, vector<int> > places; map<string, int> score; struct T { string name; vector<int> place; int score; }; bool cmp1(const T& a, const T& b) { if (a.score != b.score) return a.score > b.score; for (int i = 1; i <= 55; ++i) if (a.place[i] != b.place[i]) return a.place[i] > b.place[i]; return a.name < b.name; } bool cmp2(const T& a, const T& b) { if (a.place[1] != b.place[1]) return a.place[1] > b.place[1]; if (a.score != b.score) return a.score > b.score; for (int i = 2; i <= 55; ++i) if (a.place[i] != b.place[i]) return a.place[i] > b.place[i]; return a.name < b.name; } int main() { cin >> t; for (int tt = 0; tt < t; ++tt) { cin >> n; for (int i = 1; i <= n; ++i) { string s; cin >> s; int kk = 0; if (i <= 10) kk = points[i]; score[s] += kk; if (places.find(s) == places.end()) places[s] = vector<int>(60); places[s][i]++; } } map<string, int>::iterator it; vector<T> a; for (it = score.begin(); it != score.end(); ++it) { a.push_back(T()); a.back().name = it->first; a.back().place = places[it->first]; a.back().score = it->second; } sort((a).begin(), (a).end(), cmp1); cout << a[0].name << endl; sort((a).begin(), (a).end(), cmp2); cout << a[0].name << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire pwrgood_pp1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , pwrgood_pp0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , pwrgood_pp1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c; cin >> a >> b >> c; long long power = 0, l = 0, emp = 1, aa = 0; for (long long i = 0; i > -1; i++) { if (i != 0) { for (long long j = 0; j < i; j++) { emp = emp * c; } } if (emp >= a && emp <= b) { cout << emp << ; power++; } if (emp > b / c) { break; } emp = 1; } if (power == 0) { cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T--) { long long n, k; cin >> n >> k; if (k % 3 != 0) { if (n % 3 == 0) cout << Bob << endl; else cout << Alice << endl; } else { n %= (k + 1); if (n == k || n % 3) cout << Alice << endl; else cout << Bob << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long s[200005], e[200005]; long long win(long long s, long long e) { if (e & 1) { if (s & 1) return 0; return 1; } if (s > e / 2) { if (s & 1) return 1; return 0; } if (s > e / 4) return 1; return win(s, e >> 2); } long long lose(long long s, long long e) { if (s > e / 2) return 1; return win(s, e >> 1); } int main() { long long i, n, j, k, t, m, w, l, cur = 0; scanf( %lld , &t); for (i = 1; i <= t; i++) scanf( %lld%lld , &s[i], &e[i]); for (i = 1; i <= t; i++) { w = win(s[i], e[i]); l = lose(s[i], e[i]); w ^= cur; l ^= cur; if (w == l) break; if (w) cur = 1; else cur = 0; } printf( %lld %lld n , w, l); } |
//
// Pseudo Random Number Generator interface.
// Uses the xoroshiro128+ PRNG.
//
`include "inc/timescale.vh"
module prng (
// Bus interface
input wire clk,
input wire resetn,
input wire enable,
input wire mem_valid,
output wire mem_ready,
input wire mem_instr,
input wire [3:0] mem_wstrb,
input wire [31:0] mem_wdata,
input wire [31:0] mem_addr,
output wire [31:0] mem_rdata
);
wire [63:0] prng_out;
reg prng_clk;
reg rdy;
reg [31:0] q;
xoroshiro128plus prng(
.resn(resetn),
.clk(prng_clk),
.out(prng_out)
);
always @(negedge clk) begin
if (!resetn) begin
rdy <= 0;
prng_clk <= 0;
end else if (mem_valid & enable) begin
prng_clk <= 1;
rdy <= 1;
end else begin
prng_clk <= 0;
rdy <= 0;
end
q <= prng_out;
end
// Wire-OR'ed bus outputs.
assign mem_rdata = enable ? q : 32'b0;
assign mem_ready = enable ? rdy : 1'b0;
endmodule
|
`timescale 1ns / 1ps
/*
Instruction decode pipeline stage
*/
module id_stage( input clk, rst,
input reg_write,
input [4:0] wreg_addr, // write register number
input [31:0] wreg_data, // data to write into regfile
input [31:0] instruction, next_i_addr, // instruction fetched, next instruction address
//inputs to support forwarding
input [1:0] rs_fwd_sel, rt_fwd_sel, // forwarding control signals
input [31:0] mem_fwd_val, wb_fwd_val, // forwarded data values
input hazard,
input pstop_i,
//outputs
output [4:0] id_rs,
output [4:0] id_rt,
output [5:0] id_opcode,
output reg [31:0] ID_EX_A,
output reg [31:0] ID_EX_B,
output reg [4:0] ID_EX_rt,
output reg [4:0] ID_EX_rs,
output reg [4:0] ID_EX_rd,
output reg [5:0] ID_EX_opcode,
output reg [31:0] ID_EX_sign_extend_offset,
output reg ID_EX_wb_reg_write,
output reg ID_EX_wb_mem_to_reg,
output reg ID_EX_mem_read,
output reg ID_EX_mem_write,
output reg ID_EX_ex_imm_command,
output reg ID_EX_ex_alu_src_b,
output reg ID_EX_ex_alu_rslt_src,
output reg [1:0] ID_EX_ex_dst_reg_sel,
output reg [1:0] ID_EX_ex_alu_op,
output [31:0] branch_addr, jump_addr, // branch and jump adresses
output id_rt_is_source,
output [1:0] if_pc_source );
reg [31:0] A, B;
wire [31:0] a_out;
wire [31:0] b_out;
wire [31:0] sign_extend_offset;
wire ex_imm_command;
wire ex_alu_src_b;
wire ex_alu_rslt_src;
wire [1:0] ex_dst_reg_sel;
wire [1:0] ex_alu_op;
wire mem_read;
wire mem_write;
wire wb_mem_to_reg;
wire wb_reg_write;
wire is_nop;
wire branch_eq;
regfile regfile_inst (
.clk( clk ),
.rst( rst ),
.raddr1( instruction[25:21] ),
.raddr2( instruction[20:16] ),
.waddr( wreg_addr ),
.wdata( wreg_data ),
.w_en( reg_write ),
.rdata1( a_out ),
.rdata2( b_out ));
// Forwarding muxes
always @* begin
A = 0;
case (rs_fwd_sel)
0: A = a_out;
1: A = mem_fwd_val;
2: A = wb_fwd_val;
endcase
end
always @* begin
B = 0;
case (rt_fwd_sel)
0: B = b_out;
1: B = mem_fwd_val;
2: B = wb_fwd_val;
endcase
end
assign sign_extend_offset = { { 16{instruction[15]} }, instruction [15:0]};
assign branch_addr = next_i_addr + ( sign_extend_offset << 2 );
assign jump_addr = {next_i_addr[31:28], instruction[25:0], 2'b00 };
assign branch_eq = ( A == B);
assign id_rs = instruction[25:21];
assign id_rt = instruction[20:16];
assign id_opcode = instruction[31:26];
assign is_nop = ~|instruction;
//Control Unit -- Opcode Decoder
control cunit_instance (
.opcode( instruction [31:26] ),
.special( instruction [5:0] ),
.branch_eq( branch_eq ),
.id_rt_is_source(id_rt_is_source),
.if_pc_source(if_pc_source),
.ex_imm_command(ex_imm_command),
.ex_alu_src_b(ex_alu_src_b),
.ex_alu_rslt_src(ex_alu_rslt_src),
.ex_dst_reg_sel(ex_dst_reg_sel),
.ex_alu_op(ex_alu_op),
.mem_read(mem_read),
.mem_write(mem_write),
.wb_mem_to_reg(wb_mem_to_reg),
.wb_reg_write(wb_reg_write));
//ID/EX Pipeline register
always @(posedge clk) begin
if (rst) begin
ID_EX_A <= 0;
ID_EX_B <= 0;
ID_EX_rt <= 0;
ID_EX_rs <= 0;
ID_EX_rd <= 0;
ID_EX_opcode <= 0;
ID_EX_sign_extend_offset <= 0;
ID_EX_wb_reg_write <= 0;
ID_EX_wb_mem_to_reg <= 0;
ID_EX_mem_read <= 0;
ID_EX_mem_write <= 0;
ID_EX_ex_imm_command <= 0;
ID_EX_ex_alu_src_b <= 0;
ID_EX_ex_alu_rslt_src <= 0;
ID_EX_ex_dst_reg_sel <= 0;
ID_EX_ex_alu_op <= 0;
end
else begin
if(!pstop_i) begin
ID_EX_A <= A;
ID_EX_B <= B;
ID_EX_rt <= id_rt;
ID_EX_rs <= id_rs;
ID_EX_rd <= instruction[15:11];
ID_EX_opcode <= id_opcode;
ID_EX_sign_extend_offset <= sign_extend_offset;
end
if(!pstop_i) begin
if (is_nop || hazard) begin
ID_EX_wb_reg_write <= 0;
ID_EX_wb_mem_to_reg <= 0;
ID_EX_mem_read <= 0;
ID_EX_mem_write <= 0;
ID_EX_ex_imm_command <= 0;
ID_EX_ex_alu_src_b <= 0;
ID_EX_ex_alu_rslt_src <= 0;
ID_EX_ex_dst_reg_sel <= 0;
ID_EX_ex_alu_op <= 0;
end
else begin
ID_EX_wb_reg_write <= wb_reg_write;
ID_EX_wb_mem_to_reg <= wb_mem_to_reg;
ID_EX_mem_read <= mem_read;
ID_EX_mem_write <= mem_write;
ID_EX_ex_imm_command <= ex_imm_command;
ID_EX_ex_alu_src_b <= ex_alu_src_b;
ID_EX_ex_alu_rslt_src <= ex_alu_rslt_src;
ID_EX_ex_dst_reg_sel <= ex_dst_reg_sel;
ID_EX_ex_alu_op <= ex_alu_op;
end
end
end
end
endmodule
|
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
int_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
int_output_ecc_code_r <= int_output_ecc_code;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = int_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = int_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = int_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] int_decoder_input;
wire [32 : 0] int_decoder_output;
// Assign decoder output
assign int_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = int_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (int_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (int_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32 decoder_inst
(
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64 decoder_inst
(
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_PR_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DLATCH_PR_SYMBOL_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$PR (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET,
//# {{clocks|Clocking}}
input GATE
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_PR_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, h, a, b, k; cin >> n >> h >> a >> b >> k; for (long long int i = 0; i < k; i++) { long long int t1, f1, t2, f2; cin >> t1 >> f1 >> t2 >> f2; long long int ans; if (t1 == t2) { cout << abs(f1 - f2) << endl; continue; } if (a <= f1 && f1 <= b) { cout << abs(t1 - t2) + abs(f1 - f2) << endl; continue; } long long int temp; if (abs(f1 - a) <= abs(f1 - b)) { temp = a; ans = abs(f1 - a); } else { temp = b; ans = abs(f1 - b); } ans = ans + abs(t1 - t2) + abs(temp - f2); cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; struct point { double x, y; }; struct segment { double a, b, c; }; point operator+(point a, point b) { return (point){a.x + b.x, a.y + b.y}; } point operator-(point a, point b) { return (point){a.x - b.x, a.y - b.y}; } double operator*(point a, point b) { return a.x * b.x + a.y * b.y; } double operator/(point a, point b) { return a.x * b.y - a.y * b.x; } point operator*(point a, double b) { return (point){a.x * b, a.y * b}; } point operator/(point a, double b) { return (point){a.x / b, a.y / b}; } int T; point I, J, K, L; segment midline(point A, double a, double b) { segment line; line.a = b; line.b = -a; line.c = -(A.x * line.a + A.y * line.b); return line; } point getpoint(segment A, segment B) { point C; C.x = (-A.c * B.b + B.c * A.b) / (A.a * B.b - B.a * A.b); C.y = (-A.a * B.c + B.a * A.c) / (A.a * B.b - B.a * A.b); return C; } point mirror(point A, point B) { point C; C = A + (B - A) * 2; return C; } int zero1(double x) { return x > eps; } int zero0(double x) { return x < -eps; } int solve(point A, point B, point C) { point D, E, F, G, H; point IJ, JK, KL, LI; segment lineAC, lineBC, lineD, lineE, lineHG; bool ans; ans = false; lineAC = (segment){A.y - C.y, C.x - A.x, A / C}; lineBC = (segment){B.y - C.y, C.x - B.x, B / C}; D = (A + C) / 2; E = (B + C) / 2; lineD = midline(D, lineAC.a, lineAC.b); lineE = midline(E, lineBC.a, lineBC.b); F = getpoint(lineD, lineE); G = mirror(E, C); H = mirror(F, C); lineHG = (segment){H.y - G.y, G.x - H.x, H / G}; I = getpoint(lineHG, lineD); J = mirror(I, C); K = mirror(J, B); L = mirror(I, A); IJ = J - I; JK = K - J; KL = L - K; LI = I - L; if (zero1(IJ / JK) && zero1(JK / KL) && zero1(KL / LI) && zero1(LI / IJ)) ans = true; if (zero0(IJ / JK) && zero0(JK / KL) && zero0(KL / LI) && zero0(LI / IJ)) ans = true; return ans; } void print() { printf( YES n%.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf n , I.x, I.y, J.x, J.y, K.x, K.y, L.x, L.y); } int main() { point A, B, C; scanf( %d , &T); while (T--) { scanf( %lf%lf%lf%lf%lf%lf , &A.x, &A.y, &B.x, &B.y, &C.x, &C.y); if (solve(A, B, C)) print(); else if (solve(A, C, B)) print(); else if (solve(B, C, A)) print(); else printf( NO n ); } return 0; } |
`timescale 1 ns / 1 ps
module decoder_axi_m_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0
)
(
// Users to add ports here
output wire [31:0] incoming_data,
output wire incoming_data_valid,
output wire rburst_active,
output wire wburst_active,
output wire wnext,
input wire dram_rreq,
input wire dram_wreq,
input wire [C_M00_AXI_ADDR_WIDTH-1:0] dram_raddr,
input wire [C_M00_AXI_ADDR_WIDTH-1:0] dram_waddr,
input wire [31:0] outgoing_data,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
decoder_axi_m_v1_0_M00_AXI # (
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) decoder_axi_m_v1_0_M00_AXI_inst (
.dram_rreq ( dram_rreq ), // input
.dram_wreq ( dram_wreq ), // input
.dram_raddr ( dram_raddr ), // input
.dram_waddr ( dram_waddr ), // input
.outgoing_data ( outgoing_data ), // input
.wnext ( wnext ), // output
.rburst_active ( rburst_active ), // output
.wburst_active ( wburst_active ), // output
.error_reg(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
assign incoming_data = m00_axi_rdata;
// The data is valid when rvalid AND rready.
// This is needed if slave is allowed to deassert rvalid signal
// during a burst, or if the master asserts rready irrespective
// of expectation of data (NOT our case).
assign incoming_data_valid = m00_axi_rvalid && m00_axi_rready;
// User logic ends
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, h, k, i, j, s2, H[2][3000], H2[2][3000], s, a, x, y, z, l[2], top; vector<pair<int, int> > v[2]; int main() { cin >> n >> m; for (i = 0; i < n; i++) { cin >> x >> y >> z; v[x].push_back(make_pair(z, y)); } h = m; sort(v[0].begin(), v[0].end()); sort(v[1].begin(), v[1].end()); l[0] = v[0].size(); l[1] = v[1].size(); while (1) { a = 0; for (i = l[k] - 1; i >= 0; i--) if (v[k][i].second <= m && !H[k][i]) { s++; H[k][i] = 1; m += v[k][i].first; a = 1; break; } if (!a) break; k = !k; } m = h; k = 1; while (1) { a = 0; for (i = l[k] - 1; i >= 0; i--) if (v[k][i].second <= m && !H2[k][i]) { s2++; H2[k][i] = 1; m += v[k][i].first; a = 1; break; } if (!a) break; k = !k; } cout << max(s, s2); } |
/*
** -----------------------------------------------------------------------------**
** encoderDCAC353.v
**
** RLL encoder for JPEG compressor
**
** Copyright (C) 2002-2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// Accepts 13-bits signed data (only 12-bit can be ecoded), so DC difference (to be encoded) is limited (saturated) to 12 bits, not the value itself
// AC - always limited to 800 .. 7ff
module encoderDCAC(clk,
en,
// firsti, // was "first MCU in a frame" (@ stb)
lasti, // was "last MCU in a frame" (@ stb)
first_blocki, // first block in frame - save fifo write address (@ stb)
comp_numberi, // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb)
comp_firsti, // fitst this component in a frame (reset DC) (@ stb)
comp_colori, // use color - huffman? (@ stb)
comp_lastinmbi, // last component in a macroblock (@ stb) is it needed?
stb, // strobe that writes firsti, lasti, tni,average
zdi, // [11:0] zigzag-reordered data input
first_blockz, // first block input (@zds)
zds, // strobe - one ahead of the DC component output
last, //
do,
dv
);
input clk;
input en;
// input firsti;
input lasti;
input first_blocki; // first block in frame - save fifo write address (@ stb)
input [2:0] comp_numberi; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb)
input comp_firsti; // fitst this component in a frame (reset DC) (@ stb)
input comp_colori; // use color - huffman? (@ stb)
input comp_lastinmbi; // last component in a macroblock (@ stb)
input stb;
input [12:0] zdi;
input first_blockz; // first block input (@zds)
input zds;
output last;
output [15:0] do;
output dv;
// reg [2:0] ic;
// reg [2:0] oc;
reg last;
// 8x13 DC storage memory
reg [12:0] dc_mem[7:0];
reg [12:0] dc_diff0, dc_diff;
wire [11:0] dc_diff_limited= (dc_diff[12]==dc_diff[11])? dc_diff[11:0] : {~dc_diff[11],{11{dc_diff[11]}}}; // difference (to be encoded) limited to fit 12 bits
reg [12:0] dc_restored; // corrected DC value of the current block, compensated to fit difference to 12 bits
reg [5:0] rll_cntr;
reg [15:0] do;
// reg dv0;
reg dv;
//
reg [5:0] cntr;
// reg ac_on;
reg [11:0] ac_in;
wire izero=(ac_in[11:0]==12'b0);
reg [14:0] val_r; // DC diff/AC values to be sent out, registered
reg DCACen; // enable DC/AC (2 cycles ahead of do
wire rll_out;
// wire eob_out;
wire pre_dv;
reg was_nonzero_AC;
reg [12:0] zdi_d;
reg [3:0] zds_d;
// wire dc_mem_we= zds_d[3]; // not needed
wire DC_tosend= zds_d[2];
wire pre_DCACen= zds_d[1];
wire [2:0] comp_numbero; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use
wire comp_firsto; // first this component in a frame (reset DC)
wire comp_coloro; // use color - huffman?
// wire first_blocko; // first block in frame - save fifo write address
wire comp_lastinmbo; // last component in a macroblock
wire lasto; // last macroblock in a frame
reg [2:0] block_mem_ra;
reg [2:0] block_mem_wa;
reg [2:0] block_mem_wa_save;
reg [6:0] block_mem[0:7];
wire [6:0] block_mem_o=block_mem[block_mem_ra[2:0]];
assign comp_numbero[2:0]= block_mem_o[2:0];
assign comp_firsto= block_mem_o[3];
assign comp_coloro= block_mem_o[4];
// assign first_blocko= block_mem_o[5];
assign comp_lastinmbo= block_mem_o[5];
assign lasto= block_mem_o[6];
always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, /*first_blocki,*/ comp_colori,comp_firsti,comp_numberi[2:0]};
if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
if (stb && first_blocki) block_mem_wa_save[2:0] <= block_mem_wa[2:0];
if (!en) block_mem_ra[2:0] <= 3'h0;
else if (zds) block_mem_ra[2:0] <= first_blockz?block_mem_wa_save[2:0]:(block_mem_ra[2:0] +1);
end
assign rll_out= ((val_r[12] && !val_r[14]) || (ac_in[11:0]!=12'b0)) && (rll_cntr[5:0]!=6'b0);
assign pre_dv=rll_out || val_r[14] || was_nonzero_AC;
always @ (posedge clk) begin
val_r[14:0] <={ DC_tosend?
{en,
comp_coloro,
comp_lastinmbo && lasto, // last component's in a frame DC coefficient
dc_diff_limited[11:0]}:
{2'b0,
(cntr[5:0]==6'h3f),
ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0;
else cntr[5:0] <=cntr[5:0]+1;
end
always @ (posedge clk) begin
zdi_d[12:0] <= zdi[12:0];
ac_in[11:0] <= (zdi_d[12]==zdi_d[11])? zdi_d[11:0]:{~zdi_d[11],{11{zdi_d[11]}}}; // always // delay + saturation
if (DC_tosend || !izero || !DCACen) rll_cntr[5:0] <= 6'h0;
else if (DCACen) rll_cntr[5:0] <= rll_cntr[5:0] +1 ;
if (DC_tosend) last <= lasto;
end
// DC components
always @ (posedge clk) begin
zds_d[3:0] <= {zds_d[2:0], zds};
if (zds_d[0]) dc_diff0[12:0] <= comp_firsto?13'b0:dc_mem[comp_numbero[2:0]];
if (zds_d[1]) dc_diff [12:0] <= zdi_d[12:0]-dc_diff0[12:0];
if (zds_d[2]) dc_restored[12:0] <= dc_diff0[12:0] + {dc_diff_limited[11],dc_diff_limited[11:0]};
if (zds_d[3]) dc_mem[comp_numbero[2:0]] <= dc_restored[12:0];
end
// Generate output stream to facilitate huffman encoding. The data will go to FIFO (16x) to compensate for possible long Huffman codes
// and/or zero-byte insertions
// format:
// {2'b11, color,last block, dc[11:0]} - DC data
// {2'b10, 1'b0, last coeff, ac[11:0]} - AC data (last coeff is set if it is last- 63-rd AC coefficient)
// {2'h00, 2'b00, 6'b0,rll[ 5:0]} - RLL zeroes.
// {2'h00, 2'b01, 6'b0,rll[ 5:0]} - end of block. lower 6 bits will have length that should be ignored
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_2_V
`define SKY130_FD_SC_MS__A41OI_2_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_2_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 2; long long int i, j, n, m, s, ans = 0, cnt = 0; vector<pair<long long int, long long int> > nf; vector<long long int> graph[maxn]; bool foundd[maxn]; void dfs(long long int u, bool found[]) { if (!foundd[u]) ++ans; found[u] = true; vector<long long int>::iterator it; for (it = graph[u].begin(); it != graph[u].end(); ++it) { if (!found[*it]) dfs(*it, found); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m >> s; bool found[5200], isreachable[5200]; for (i = 0; i < m; ++i) { long long int u, v; cin >> u >> v; graph[u].push_back(v); } memset(found, false, sizeof(found)); dfs(s, found); for (i = 1; i <= n; ++i) foundd[i] = found[i]; for (i = 1; i <= n; ++i) { if (!foundd[i]) { bool found1[5001]; memset(found1, false, sizeof(found1)); ans = 0; dfs(i, found1); nf.push_back(make_pair(ans, i)); } } sort(nf.begin(), nf.end(), greater<pair<long long int, long long int> >()); for (i = 0; i < nf.size(); ++i) { if (!foundd[nf[i].second]) { bool found1[5001]; memset(found1, false, sizeof(found1)); dfs(nf[i].second, found1); ++cnt; for (j = 1; j <= n; ++j) if (found1[j]) foundd[j] = true; } } cout << cnt; } |
#include <bits/stdc++.h> using namespace std; int main() { pair<long long, int> p[400005]; int n, m; cin >> n; for (int i = 0; i < n; i++) { cin >> p[i].first; p[i].second = 1; } cin >> m; for (int i = 0; i < m; i++) { cin >> p[i + n].first; p[i + n].second = 2; } int x = n * 3; int y = m * 3; sort(p, p + n + m); int u = x, v = y; for (int i = 0; i < n + m; i++) { if (p[i].second == 1) x--; else y--; if (x - y > u - v) { u = x; v = y; } } cout << u << : << v << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; char a[N], b[N]; int s[N][26]; void init() { int n = strlen(a + 1); memset(s, 0, sizeof(s)); for (int i = n; i >= 1; i--) { for (int j = 0; j < 26; j++) { s[i - 1][j] = s[i][j]; } s[i - 1][a[i] - a ] = i; } } int main() { int T; cin >> T; while (T--) { scanf( %s %s , a + 1, b + 1); init(); int flg = 0; int p = 0; int ans = 1; for (int i = 1; i <= strlen(b + 1); i++) { int t = b[i] - a ; int tt = s[p][t]; if (tt == 0 && p == 0) { flg = 1; break; } if (tt == 0) { i--; ans++; p = 0; } else { p = tt; } } if (flg == 1) { printf( -1 n ); continue; } printf( %d n , ans); } return 0; } |
`define Alu_NOP 4'h0
`define Alu_LDI 4'h1
`define Alu_ADD 4'h2
`define Alu_SUB 4'h3
`define Alu_NOT 4'h4
`define Alu_AND 4'h5
`define Alu_IOR 4'h6
`define Alu_XOR 4'h7
`define Alu_SHL 4'h8
`define Alu_SHR 4'h9
`define Alu_EQL 4'hA
`define Alu_NEQ 4'hB
`define Alu_LTS 4'hC
`define Alu_LTE 4'hD
`define Alu_GTS 4'hE
`define Alu_GTE 4'hF
`define Alu_State_Reset 2'h0
`define Alu_State_Ready 2'h1
`define Alu_State_Error 2'h2
module Alu(clock,reset,inst,inst_en,result);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [7:0] result;
reg [1:0] s_State;
reg [7:0] s_Accum;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign result = s_Accum;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
always @ (posedge clock) begin
if (reset) begin
s_State <= `Alu_State_Reset;
s_Accum <= 0;
end
else begin
case (s_State)
`Alu_State_Reset: begin
s_State <= `Alu_State_Ready;
s_Accum <= 0;
end
`Alu_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`Alu_NOP: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum;
end
`Alu_LDI: begin
s_State <= `Alu_State_Ready;
s_Accum <= w_InstImm;
end
`Alu_ADD: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum + w_InstImm;
end
`Alu_SUB: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum - w_InstImm;
end
`Alu_NOT: begin
s_State <= `Alu_State_Ready;
s_Accum <= ~s_Accum;
end
`Alu_AND: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum & w_InstImm;
end
`Alu_IOR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum | w_InstImm;
end
`Alu_XOR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum ^ w_InstImm;
end
`Alu_SHL: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum << 1;
end
`Alu_SHR: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum >> 1;
end
`Alu_EQL: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum == w_InstImm;
end
`Alu_NEQ: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum != w_InstImm;
end
`Alu_LTS: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum < w_InstImm;
end
`Alu_LTE: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum <= w_InstImm;
end
`Alu_GTS: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum > w_InstImm;
end
`Alu_GTE: begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum >= w_InstImm;
end
default: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `Alu_State_Ready;
s_Accum <= s_Accum;
end // else: !if(inst_en)
end // case: `Alu_State_Ready
`Alu_State_Error: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
default: begin
s_State <= `Alu_State_Error;
s_Accum <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`Alu_NOP: begin
$sformat(d_Input,"EN NOP");
end
`Alu_LDI: begin
$sformat(d_Input,"EN (LDI %2X)",w_InstImm);
end
`Alu_ADD: begin
$sformat(d_Input,"EN (ADD %2X)",w_InstImm);
end
`Alu_SUB: begin
$sformat(d_Input,"EN (SUB %2X)",w_InstImm);
end
`Alu_NOT: begin
$sformat(d_Input,"EN NOT");
end
`Alu_AND: begin
$sformat(d_Input,"EN (AND %2X)",w_InstImm);
end
`Alu_IOR: begin
$sformat(d_Input,"EN (IOR %2X)",w_InstImm);
end
`Alu_XOR: begin
$sformat(d_Input,"EN (XOR %2X)",w_InstImm);
end
`Alu_SHL: begin
$sformat(d_Input,"EN SHL");
end
`Alu_SHR: begin
$sformat(d_Input,"EN SHR");
end
`Alu_EQL: begin
$sformat(d_Input,"EN (EQL %2X)",w_InstImm);
end
`Alu_NEQ: begin
$sformat(d_Input,"EN (NEQ %2X)",w_InstImm);
end
`Alu_LTS: begin
$sformat(d_Input,"EN (LTS %2X)",w_InstImm);
end
`Alu_LTE: begin
$sformat(d_Input,"EN (LTE %2X)",w_InstImm);
end
`Alu_GTS: begin
$sformat(d_Input,"EN (GTS %2X)",w_InstImm);
end
`Alu_GTE: begin
$sformat(d_Input,"EN (GTE %2X)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`Alu_State_Reset: begin
$sformat(d_State,"X");
end
`Alu_State_Ready: begin
$sformat(d_State,"R %2X",s_Accum);
end
`Alu_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // Alu
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:13:59 09/03/2013
// Design Name:
// Module Name: display_time_parameters
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display_time_parameters(
input bitA,
input bitB,
input bitC,
input bitD,
output seg_a,
output seg_b,
output seg_c,
output seg_d,
output seg_e,
output seg_f,
output seg_g,
output s_seg1,
output s_seg2,
output s_seg3,
output s_seg4
);
assign s_seg1 = 0;
assign s_seg2 = 0;
assign s_seg3 = 1;
assign s_seg4 = 1;
assign seg_a = !((!bitB&!bitD)|(!bitA&bitC)|(!bitA&bitB&bitD)|(bitB&bitC)|(bitA&!bitD)|(bitA&!bitB&!bitC));
assign seg_b = !((bitA&!bitC&bitD)|(!bitB&!bitD)|(!bitA&!bitC&!bitD)|(!bitA&bitC&bitD)|(!bitA&!bitB));
assign seg_c = !((!bitC&bitD)|(!bitA&bitB)|(bitA&!bitB)|(!bitA&!bitC)|(!bitA&bitD));
assign seg_d = !((bitB&!bitC&bitD)|(!bitB&bitC&bitD)|(bitB&bitC&!bitD)|(bitA&!bitC)|(!bitA&!bitB&!bitD));
assign seg_e = !((!bitB&!bitD)|(bitC&!bitD)|(bitA&bitC)|(bitA&bitB));
assign seg_f = !((!bitC&!bitD)|(bitB&!bitD)|(!bitA&bitB&!bitC)|(bitA&!bitB)|(bitA&bitC));
assign seg_g = !((!bitB&bitC)|(bitA&!bitB)|(bitA&bitD)|(bitC&!bitD)|(!bitA&bitB&!bitC));
endmodule
|
#include <bits/stdc++.h> int K; int main() { scanf( %d , &K); if (K % 2) { puts( YES ); if (K == 1) { puts( 2 1 n1 2 ); return 0; } int i, j, N = (K << 1) + 4, M = (3 * K - 2 + (K - 1) * (K - 2) / 2 - K / 2) * 2 + 1, tmp1 = K + 1, tmp2 = K + 2; printf( %d %d n , N, M); for (i = 1; i < K; i++) printf( %d %d n%d %d n%d %d n%d %d n%d %d n%d %d n , K, i, K + tmp2, i + tmp2, tmp1, i, tmp1 + tmp2, i + tmp2, tmp2, i, tmp2 << 1, i + tmp2); printf( %d %d n%d %d n , tmp1, tmp2, tmp1 + tmp2, tmp2 << 1); int lim = K - 1; for (i = 1, tmp1 = K >> 1; i < lim; i++) for (j = i + 1; j < K; j++) if (j != i + tmp1) printf( %d %d n%d %d n , i, j, i + tmp2, j + tmp2); printf( %d %d n , K, K + tmp2); } else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void tk_input(vector<T> &arr) { for (T &i : arr) cin >> i; } void solve() { int n, k; cin >> n >> k; string s; cin >> s; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > pq; int sc = 0, ls = 0, ls_i = 0, f_i = n, l_i = -1; for (int i = 0; i <= n - 1; i++) { if (s[i] == W ) { if ((ls > 0) && (f_i != n)) pq.push(pair<int, int>(ls, ls_i)); f_i = min(f_i, i); l_i = max(l_i, i); ls_i = i + 1; ls = 0; } else { ls++; } } while ((!pq.empty()) && (k > 0)) { auto tp = pq.top(); pq.pop(); for (int i = tp.second; i <= tp.first + tp.second - 1; i++) { if (k == 0) break; s[i] = W ; k--; } } for (int i = f_i - 1; i >= 0; i--) { if (k == 0) break; s[i] = W ; k--; } if (l_i != -1) { for (int i = l_i + 1; i <= n - 1; i++) { if (k == 0) break; s[i] = W ; k--; } } sc += (s[0] == W ); for (int i = 1; i <= n - 1; i++) { sc += ((s[i] == W ) * (1 + (s[i - 1] == W ))); } cout << sc << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int _t; cin >> _t; while (_t--) solve(); } |
//////////////////////////////////////////////////////////////////////////////////
// InterChannelELPBuffer.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <>
// Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: InterChannelELPBuffer
// File Name: InterChannelELPBuffer.v
//
// Version: v1.0.0
//
// Description: Error location polynomial (ELP) coefficient buffer array
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module InterChannelELPBuffer
#(
parameter Channel = 4,
parameter Multi = 2,
parameter MaxErrorCountBits = 9,
parameter GaloisFieldDegree = 12,
parameter ELPCoefficients = 15
)
(
iClock ,
iReset ,
iChannelSel ,
iKESEnd ,
iKESFail ,
iClusterCorrectionEnd ,
iCorrectedChunkNumber ,
iChunkErrorCount ,
oBufferReady ,
iELPCoefficient000 ,
iELPCoefficient001 ,
iELPCoefficient002 ,
iELPCoefficient003 ,
iELPCoefficient004 ,
iELPCoefficient005 ,
iELPCoefficient006 ,
iELPCoefficient007 ,
iELPCoefficient008 ,
iELPCoefficient009 ,
iELPCoefficient010 ,
iELPCoefficient011 ,
iELPCoefficient012 ,
iELPCoefficient013 ,
iELPCoefficient014 ,
iCSAvailable ,
oIntraSharedKESEnd ,
oErroredChunk ,
oCorrectionFail ,
oClusterErrorCount ,
oELPCoefficients
);
input iClock ;
input iReset ;
input [3:0] iChannelSel ;
input iKESEnd ;
input iKESFail ;
input iClusterCorrectionEnd ;
input iCorrectedChunkNumber ;
input [3:0] iChunkErrorCount ;
output oBufferReady ;
input [GaloisFieldDegree - 1:0] iELPCoefficient000 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient001 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient002 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient003 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient004 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient005 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient006 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient007 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient008 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient009 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient010 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient011 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient012 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient013 ;
input [GaloisFieldDegree - 1:0] iELPCoefficient014 ;
input [Channel - 1:0] iCSAvailable ;
output [Channel - 1:0] oIntraSharedKESEnd ;
output [Channel*Multi - 1:0] oErroredChunk ;
output [Channel*Multi - 1:0] oCorrectionFail ;
output [Channel*Multi*MaxErrorCountBits - 1:0] oClusterErrorCount ;
output [Channel*Multi*GaloisFieldDegree*ELPCoefficients - 1:0] oELPCoefficients ;
reg rChannelSel ;
wire [Channel - 1:0] wKESEnd ;
wire [Channel - 1:0] wBufferReady ;
assign wKESEnd = (iKESEnd) ? iChannelSel : 0;
genvar c;
generate
for (c = 0; c < Channel; c = c + 1)
d_KES_CS_buffer
#(
.Multi(2),
.GaloisFieldDegree(12),
.MaxErrorCountBits(9),
.ELPCoefficients(15)
)
Inst_PageDecoderCSBuffer
(
.i_clk (iClock ),
.i_RESET (iReset ),
.i_stop_dec (1'b0 ),
.i_exe_buf (wKESEnd[c] ),
.i_kes_fail (iKESFail ),
.i_buf_sequence_end (iClusterCorrectionEnd ),
.i_chunk_number (iCorrectedChunkNumber ),
.i_error_count (iChunkErrorCount ),
.i_v_000 (iELPCoefficient000 ),
.i_v_001 (iELPCoefficient001 ),
.i_v_002 (iELPCoefficient002 ),
.i_v_003 (iELPCoefficient003 ),
.i_v_004 (iELPCoefficient004 ),
.i_v_005 (iELPCoefficient005 ),
.i_v_006 (iELPCoefficient006 ),
.i_v_007 (iELPCoefficient007 ),
.i_v_008 (iELPCoefficient008 ),
.i_v_009 (iELPCoefficient009 ),
.i_v_010 (iELPCoefficient010 ),
.i_v_011 (iELPCoefficient011 ),
.i_v_012 (iELPCoefficient012 ),
.i_v_013 (iELPCoefficient013 ),
.i_v_014 (iELPCoefficient014 ),
.i_cs_available (iCSAvailable[c] ),
.o_buf_available (wBufferReady[c] ),
.o_exe_cs (oIntraSharedKESEnd[c] ),
.o_kes_sequence_end (oErroredChunk[(c+1)*Multi - 1: c*Multi] ),
.o_kes_fail (oCorrectionFail[(c+1)*Multi - 1: c*Multi] ),
.o_error_count (oClusterErrorCount[(c+1)*Multi*MaxErrorCountBits - 1: c*Multi*MaxErrorCountBits] ),
.o_ELP_coef (oELPCoefficients[(c+1)*Multi*GaloisFieldDegree*ELPCoefficients - 1: c*Multi*GaloisFieldDegree*ELPCoefficients] )
);
endgenerate
assign oBufferReady = (iChannelSel == 4'b0001) ? wBufferReady[0] :
(iChannelSel == 4'b0010) ? wBufferReady[1] :
(iChannelSel == 4'b0100) ? wBufferReady[2] :
(iChannelSel == 4'b1000) ? wBufferReady[3] : 1'b0;
endmodule |
#include <bits/stdc++.h> int main(void) { int n; int i, i2; int a[100000] = {0}; int flag = 0; int max = -1000001; int min = 1000001; int sum = 0; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a[i]); if (a[i] > 0) { if (a[i] < min && a[i] % 2 != 0) { min = a[i]; } sum += a[i]; } else { if (a[i] > max && a[i] % 2 != 0) { max = a[i]; } } } if (min == 1000001) { printf( %d , sum + max); return 0; } if (sum % 2 == 0) { if (min > (-max)) { printf( %d , sum + max); } else { printf( %d , sum - min); } } else { printf( %d , sum); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int count = 0; while ((count * (count + 1)) / 2 <= n) { ++count; } --count; int val = (count * (count + 1)) / 2; int diff = n - val; cout << count << n ; for (int i = 1; i <= count; ++i) { if (i == count) { cout << count + diff << ; break; } cout << i << ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:26:11 07/23/2010
// Design Name:
// Module Name: dac_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac(
input clkin,
input sysclk,
input we,
input[10:0] pgm_address,
input[7:0] pgm_data,
input[7:0] volume,
input vol_latch,
input [2:0] vol_select,
input [8:0] dac_address_ext,
input play,
input reset,
input palmode,
output sdout,
output mclk_out,
output lrck_out,
output sclk_out,
output DAC_STATUS
);
reg[8:0] dac_address_r;
reg[8:0] dac_address_r_sync;
wire[8:0] dac_address = dac_address_r_sync;
wire[31:0] dac_data;
assign DAC_STATUS = dac_address_r[8];
reg[10:0] vol_reg;
reg[10:0] vol_target_reg;
reg[1:0] vol_latch_reg;
reg vol_valid;
reg[2:0] sysclk_sreg;
wire sysclk_rising = (sysclk_sreg[2:1] == 2'b01);
always @(posedge clkin) begin
sysclk_sreg <= {sysclk_sreg[1:0], sysclk};
end
dac_buf snes_dac_buf (
.clka(clkin),
.wea(~we), // Bus [0 : 0]
.addra(pgm_address), // Bus [10 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(dac_address), // Bus [8 : 0]
.doutb(dac_data)); // Bus [31 : 0]
reg [10:0] cnt;
reg [15:0] smpcnt;
reg [1:0] samples;
reg [15:0] smpshift;
wire mclk = cnt[2]; // mclk = clk/8
wire lrck = cnt[8]; // lrck = mclk/64
wire sclk = cnt[3]; // sclk = lrck*32
reg [2:0] mclk_sreg;
reg [2:0] lrck_sreg;
reg [1:0] sclk_sreg;
assign mclk_out = ~mclk_sreg[2];
assign lrck_out = lrck_sreg[2];
assign sclk_out = sclk_sreg[1];
wire lrck_rising = ({lrck_sreg[0],lrck} == 2'b01);
wire lrck_falling = ({lrck_sreg[0],lrck} == 2'b10);
wire sclk_rising = ({sclk_sreg[0],sclk} == 2'b01);
wire sclk_falling = ({sclk_sreg[0],sclk} == 2'b10);
wire vol_latch_rising = (vol_latch_reg[1:0] == 2'b01);
reg sdout_reg;
assign sdout = sdout_reg;
reg play_r;
initial begin
cnt = 9'h100;
smpcnt = 16'b0;
lrck_sreg = 2'b00;
sclk_sreg = 2'b00;
mclk_sreg = 2'b00;
dac_address_r = 9'b0;
vol_valid = 1'b0;
vol_latch_reg = 1'b0;
vol_reg = 9'h000;
vol_target_reg = 9'h000;
samples <= 2'b00;
end
/*
21477272.727272... / 37500 * 1232 = 44100 * 16
21281370 / 709379 * 23520 = 44100 * 16
*/
reg [19:0] phaseacc = 0;
wire [14:0] phasemul = (palmode ? 23520 : 1232);
wire [19:0] phasediv = (palmode ? 709379 : 37500);
reg [3:0] subcount = 0;
reg int_strobe = 0, comb_strobe = 0;
always @(posedge clkin) begin
int_strobe <= 0;
comb_strobe <= 0;
if(reset) begin
dac_address_r <= dac_address_ext;
phaseacc <= 0;
subcount <= 0;
end else if(sysclk_rising) begin
if(phaseacc >= phasediv) begin
phaseacc <= phaseacc - phasediv + phasemul;
subcount <= subcount + 1;
int_strobe <= 1;
if (subcount == 0) begin
comb_strobe <= 1;
dac_address_r <= dac_address_r + play_r;
end
end else begin
phaseacc <= phaseacc + phasemul;
end
end
end
parameter ST0_IDLE = 10'b1000000000;
parameter ST1_COMB1 = 10'b0000000001;
parameter ST2_COMB2 = 10'b0000000010;
parameter ST3_COMB3 = 10'b0000000100;
parameter ST4_INT1 = 10'b0000010000;
parameter ST5_INT2 = 10'b0000100000;
parameter ST6_INT3 = 10'b0001000000;
reg [63:0] ci[2:0], co[2:0], io[2:0];
reg [9:0] cicstate = 10'h200;
wire [63:0] bufi = {{16{dac_data[31]}}, dac_data[31:16], {16{dac_data[15]}}, dac_data[15:0]};
always @(posedge clkin) begin
if(reset) begin
cicstate <= ST0_IDLE;
{ci[2], ci[1], ci[0]} <= 192'h0;
{co[2], co[1], co[0]} <= 192'h0;
{io[2], io[1], io[0]} <= 192'h0;
end else if(int_strobe) begin
if(comb_strobe) cicstate <= ST1_COMB1;
else cicstate <= ST4_INT1;
end else begin
case(cicstate)
/****** COMB STAGES ******/
ST1_COMB1: begin
cicstate <= ST2_COMB2;
ci[0] <= bufi;
co[0][63:32] <= bufi[63:32] - ci[0][63:32];
co[0][31:0] <= bufi[31:0] - ci[0][31:0];
end
ST2_COMB2: begin
cicstate <= ST3_COMB3;
ci[1] <= co[0];
co[1][63:32] <= co[0][63:32] - ci[1][63:32];
co[1][31:0] <= co[0][31:0] - ci[1][31:0];
end
ST3_COMB3: begin
cicstate <= ST4_INT1;
ci[2] <= co[1];
co[2][63:32] <= co[1][63:32] - ci[2][63:32];
co[2][31:0] <= co[1][31:0] - ci[2][31:0];
end
/****** INTEGRATOR STAGES ******/
ST4_INT1: begin
io[0][63:32] <= co[2][63:32] + io[0][63:32];
io[0][31:0] <= co[2][31:0] + io[0][31:0];
cicstate <= ST5_INT2;
end
ST5_INT2: begin
io[1][63:32] <= io[0][63:32] + io[1][63:32];
io[1][31:0] <= io[0][31:0] + io[1][31:0];
cicstate <= ST6_INT3;
end
ST6_INT3: begin
io[2][63:32] <= io[1][63:32] + io[2][63:32];
io[2][31:0] <= io[1][31:0] + io[2][31:0];
cicstate <= ST0_IDLE;
end
default: begin
cicstate <= ST0_IDLE;
end
endcase
end
end
always @(posedge clkin) begin
cnt <= cnt + 1;
mclk_sreg <= {mclk_sreg[1:0], mclk};
lrck_sreg <= {lrck_sreg[1:0], lrck};
sclk_sreg <= {sclk_sreg[0], sclk};
vol_latch_reg <= {vol_latch_reg[0], vol_latch};
play_r <= play;
end
wire [9:0] vol_orig = volume + volume[7];
wire [9:0] vol_3db = volume + volume[7:1] + volume[7];
wire [9:0] vol_6db = {1'b0, volume, volume[7]} + volume[7];
wire [9:0] vol_9db = {1'b0, volume, 1'b0} + volume + volume[7:6];
wire [9:0] vol_12db = {volume, volume[7:6]};
reg [9:0] vol_scaled;
always @* begin
case(vol_select)
3'b000: vol_scaled = vol_orig;
3'b001: vol_scaled = vol_3db;
3'b010: vol_scaled = vol_6db;
3'b011: vol_scaled = vol_9db;
3'b100: vol_scaled = vol_12db;
default: vol_scaled = vol_orig;
endcase
end
always @(posedge clkin) begin
vol_target_reg <= vol_scaled;
end
always @(posedge clkin) begin
if (lrck_rising) begin
dac_address_r_sync <= dac_address_r;
end
end
// ramp volume only on sample boundaries
always @(posedge clkin) begin
if (lrck_rising) begin
if(vol_reg > vol_target_reg)
vol_reg <= vol_reg - 1;
else if(vol_reg < vol_target_reg)
vol_reg <= vol_reg + 1;
end
end
wire signed [15:0] dac_data_ch = lrck ? io[2][59:44] : io[2][27:12];
wire signed [25:0] vol_sample;
wire signed [15:0] vol_sample_sat;
assign vol_sample = dac_data_ch * $signed({1'b0, vol_reg});
assign vol_sample_sat = ((vol_sample[25:23] == 3'b000 || vol_sample[25:23] == 3'b111) ? vol_sample[23:8]
: vol_sample[25] ? 16'sh8000
: 16'sh7fff);
always @(posedge clkin) begin
if (sclk_falling) begin
smpcnt <= smpcnt + 1;
sdout_reg <= smpshift[15];
if (lrck_rising | lrck_falling) begin
smpshift <= vol_sample_sat;
end else begin
smpshift <= {smpshift[14:0], 1'b0};
end
end
end
endmodule
|
//rgmii-gmii,gmii-139,rx check,rx gen
`timescale 1ns/1ns
module rx_tx_1000(
clk_125m_core,
clk_25m_core,
clk_25m_tx,//100M RGMII TX CLK
clk_125m_tx,//1000M RGMII TX CLK
reset,
rgmii_txd,
rgmii_tx_ctl,
rgmii_tx_clk,
rgmii_rxd,
rgmii_rx_ctl,
rgmii_rx_clk,
crc_data_valid,//rx data fifo
crc_data,
pkt_usedw,
pkt_valid_wrreq,
pkt_valid,
crc_gen_to_txfifo_wrreq,//tx fifo;
crc_gen_to_txfifo_data,
txfifo_data_usedw,
pkt_output_valid_wrreq,
pkt_output_valid,
port_receive,
port_discard,
port_send,
port_pream
);
input clk_125m_core;
input clk_25m_core;
input clk_25m_tx;
input clk_125m_tx;
input reset;
output [3:0]rgmii_txd;
output rgmii_tx_ctl;
output rgmii_tx_clk;
input [3:0]rgmii_rxd;
input rgmii_rx_ctl;
input rgmii_rx_clk;
output crc_data_valid;//to data fifo(crc check module);
output [138:0] crc_data;
input [7:0]pkt_usedw;
output pkt_valid_wrreq;//a full pkt,to flag fifo;
output pkt_valid;
input crc_gen_to_txfifo_wrreq;//data to txfifo;
input [138:0]crc_gen_to_txfifo_data;
output [7:0]txfifo_data_usedw;//data fifo usedw;
input pkt_output_valid_wrreq;//flag to flagfifo;
input pkt_output_valid;
output port_receive;
output port_discard;
output port_send;
output port_pream;
wire [3:0]rgmii_txd;
wire rgmii_tx_ctl;
wire rgmii_tx_clk;
wire [7:0]gmii_txd;
wire gmii_txen;
wire gmii_txer;
//wire gmii_txclk;//gmii input clk;
wire [7:0]gmii_rxd;
wire gmii_rxen;
wire gmii_rxer;
wire gmii_rx_clk;//gmii output clk;
wire crc_data_valid;//to data fifo(crc check module);
wire [138:0] crc_data;
wire pkt_valid_wrreq;//a full pkt,to flag fifo;
wire pkt_valid;
wire [7:0]txfifo_data_usedw;
wire port_receive;
wire port_discard;
wire port_send;
//wire SPEED_IS_100_1000;
wire port_pream;
gmii_139_1000 gmii_139(
.clk(rgmii_rx_clk),
.reset(reset),
.gmii_rxd(gmii_rxd),
.gmii_rxdv(gmii_rxen),
.gmii_rxer(gmii_rxer),
.crc_data_valid(crc_data_valid),
.crc_data(crc_data),
.pkt_usedw(pkt_usedw),
.pkt_valid_wrreq(pkt_valid_wrreq),
.pkt_valid(pkt_valid),
.port_receive(port_receive),
.port_discard(port_discard),
.port_pream(port_pream)
);
rgmii_gmii rgmii_gmii(
.reset_n(reset),
// RGMII Interface
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_rx_clk(rgmii_rx_clk),
// GMII Interface
.GTX_CLK(clk_125m_core),
.GMII_TXD_FROM_CORE(gmii_txd),
.GMII_TX_EN_FROM_CORE(gmii_txen),
.GMII_TX_ER_FROM_CORE(gmii_txer),
// .GRX_CLK(gmii_rx_clk),
.GMII_RXD_TO_CORE(gmii_rxd),
.GMII_RX_DV_TO_CORE(gmii_rxen),
.GMII_RX_ER_TO_CORE(gmii_rxer),
.clk_tx(clk_125m_tx),
.SPEED_IS_10_100(1'b0)//1£º100M 0:1000M
);
tx139_gmii_1000 tx139_gmii(
.clk(clk_125m_core),//system clk;
.reset(reset),
.gmii_txclk(clk_125m_core),
.crc_gen_to_txfifo_wrreq(crc_gen_to_txfifo_wrreq),
.crc_gen_to_txfifo_data(crc_gen_to_txfifo_data),
.pkt_output_valid_wrreq(pkt_output_valid_wrreq),
.pkt_output_valid(pkt_output_valid),
.gmii_txd(gmii_txd),
.gmii_txen(gmii_txen),
.gmii_txer(gmii_txer),
.txfifo_data_usedw(txfifo_data_usedw),//output_data_usedw0;
.port_send(port_send)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_SYMBOL_V
`define SKY130_FD_SC_LS__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output wire [ 7:0 ] z
);
assign z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output reg [ 7:0 ] z
);
wire [7:0] zi;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
#include <bits/stdc++.h> int main() { int t, n, *arr, i, a, odd, even; scanf( %d , &t); while (t--) { scanf( %d , &n); arr = (int*)malloc(n * sizeof(int)); for (i = 0; i < n; i++) scanf( %d , &arr[i]); even = 0; odd = 0; for (i = 0; i < n; i++) { if (arr[i] % 2 == 0) even++; else odd++; } a = 0; if (n % 2 == 0) { if (even == odd) { for (i = 0; i < n; i++) { if ((i % 2) != (arr[i] % 2)) a++; } printf( %d n , a / 2); } else printf( %d n , -1); } else { if (odd == (even - 1)) { for (i = 0; i < n; i++) { if ((i % 2) != (arr[i] % 2)) a++; } printf( %d n , a / 2); } else printf( %d n , -1); } } return 0; } |
#include <bits/stdc++.h> const int mod = 1e9 + 7; const int N = 3e5 + 1; using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << ; err(++it, args...); } long long arr[N], brr[N]; long long n, m, k, q, a, b; long long binpow(long long a, long long n) { long long res = 1; while (n) { if (n & 1) res = res * a; a = a * a; n /= 2; } return res; } void solve() { cin >> n; vector<long long> arr(n); vector<long long> v; for (int i = 0; i < n; i++) cin >> arr[i]; long long x = arr[0]; arr[0] = 0; for (int k = 0; k + 1 < n; k++) { x = min(max(0LL, arr[k + 1] - arr[k]), x); arr[k + 1] -= x; } bool ok = true; for (int k = 0; k + 1 < n; k++) { if (arr[k + 1] - arr[k] < 0) ok = false; } n = v.size(); for (int i = 0; i < n; i++) if (v[i] < 0) ok = false; if (ok) cout << yes ; else cout << no ; cout << n ; cerr << n ; } int main() { int t; t = 1; cin >> t; int a = 0; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long A = 100000000000000LL, N = 300005; long long p, d, limit; long long cal(long long p) { int x = 0; if (p % 10 != 9) return 0; while (p % 10 == 9) { x++; p /= 10; } return x; } int main() { cin >> p >> d; limit = p - d; long long j = p; long long length = log10(p) + 1; long long initial = cal(p); int i = 0; long long powerr = 10; while (true) { j = p - p % powerr - 1; if (j == -1) break; if (j < limit) break; powerr *= 10; } powerr /= 10; j = p - p % powerr - 1; if (j < limit) j = p; if (j >= limit and powerr == 1) j = p; if (initial >= (log10(powerr))) j = p; cout << j; } |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// A synchronization module for resets. Output resets are held for
// RSTDELAY+1 cycles, RSTDELAY >= 0. Reset assertion is asynchronous,
// while deassertion is synchronized to the clock.
module SyncResetA (
IN_RST_N,
CLK,
OUT_RST_N
);
parameter RSTDELAY = 1 ; // Width of reset shift reg
input CLK ;
input IN_RST_N ;
output OUT_RST_N ;
reg [RSTDELAY:0] reset_hold ;
assign OUT_RST_N = reset_hold[RSTDELAY] ;
always @( posedge CLK or negedge IN_RST_N )
begin
if (IN_RST_N == 0)
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY 0 ;
end
else
begin
reset_hold <= `BSV_ASSIGNMENT_DELAY ( reset_hold << 1 ) | 'b1 ;
end
end // always @ ( posedge CLK or negedge IN_RST_N )
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
#0 ;
// initialize out of reset forcing the designer to do one
reset_hold = {(RSTDELAY + 1) {1'b1}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // SyncResetA
|
#include <bits/stdc++.h> long double PI = 3.141592653589793238462643383279502884197; using namespace std; int b[1001][1001]; int r[1001][1001], rn[1001][1001]; int c[1001][1001], cn[1001][1001]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , &b[i][j]); r[i][j] = c[j][i] = b[i][j]; } } for (int i = 0; i < n; i++) { sort(r[i], r[i] + m); rn[i][0] = 1; for (int j = 1; j < m; j++) rn[i][j] = rn[i][j - 1] + (r[i][j] == r[i][j - 1] ? 0 : 1); } for (int i = 0; i < m; i++) { sort(c[i], c[i] + n); cn[i][0] = 1; for (int j = 1; j < n; j++) cn[i][j] = cn[i][j - 1] + (c[i][j] == c[i][j - 1] ? 0 : 1); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int ii = lower_bound(r[i], r[i] + m, b[i][j]) - r[i]; int jj = lower_bound(c[j], c[j] + n, b[i][j]) - c[j]; if (rn[i][ii] > cn[j][jj]) printf( %d , max(rn[i][m - 1], cn[j][n - 1] + rn[i][ii] - cn[j][jj])); else printf( %d , max(cn[j][n - 1], rn[i][m - 1] + cn[j][jj] - rn[i][ii])); } printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[11][1001], a[11], b[11], c[11], d[11], n, m; int main() { a[0] = 100000, b[0] = 0; scanf( %d %d %d %d , &n, &m, &c[0], &d[0]); for (int i = 1; i <= m; i++) scanf( %d %d %d %d , &a[i], &b[i], &c[i], &d[i]); for (int i = 0; i <= m; i++) dp[i][0] = 0; for (int j = 0; j <= n; j++) dp[0][j] = (j / c[0]) * d[0]; for (int i = 1; i <= m; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = dp[i - 1][j]; for (int k = 1; k * c[i] <= j && k * b[i] <= a[i]; k++) { dp[i][j] = max(dp[i][j], dp[i - 1][j - k * c[i]] + k * d[i]); } } } printf( %d , dp[m][n]); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; namespace IO { inline char gc() { static char buf[1000000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> inline void read(T &x) { x = (T)0; T f = 1; char ssd = gc(); while (ssd < 0 || ssd > 9 ) f = ssd == - ? -1 : 1, ssd = gc(); while (ssd >= 0 && ssd <= 9 ) x = (x << 3) + (x << 1) + (ssd - 0 ), ssd = gc(); x = x * f; } char OUT[1000000], *S = OUT, *T = OUT + 1000000; char Num[1000000]; int toP; inline void out() { fwrite(OUT, sizeof(char), S - OUT, stdout); S = OUT; } inline void pc(char ssd) { *S++ = ssd; if (S == T) out(); } template <typename T> inline void write(T x) { if (x == 0) pc( 0 ); if (x < 0) x = -x, pc( - ); toP = 0; while (x) Num[++toP] = x % 10 + 0 , x /= 10; while (toP) pc(Num[toP--]); } }; // namespace IO const int maxn = 4e5 + 10; namespace SGT { int sum[maxn << 5]; int ls[maxn << 5], rs[maxn << 5], Node; inline void pushup(int NODE) { sum[NODE] = sum[ls[NODE]] + sum[rs[NODE]]; } void change(int &NODE, int l, int r, int id) { if (!NODE) NODE = ++Node; if (l == r) { sum[NODE] += 1; return; } int mid = (l + r) >> 1; if (mid >= id) change(ls[NODE], l, mid, id); else change(rs[NODE], mid + 1, r, id); pushup(NODE); } int query(int NODE, int l, int r, int L, int R) { if (L > R) return 0; if (!NODE || (L <= l && r <= R)) return sum[NODE]; int re = 0; int mid = (l + r) >> 1; if (mid >= L) re += query(ls[NODE], l, mid, L, R); if (mid < R) re += query(rs[NODE], mid + 1, r, L, R); return re; } int merge(int root1, int root2, int l, int r) { if (!root1 || !root2) return root1 + root2; int New = ++Node; if (l == r) { sum[New] = sum[root1] + sum[root2]; return New; } else { int mid = (l + r) >> 1; ls[New] = merge(ls[root1], ls[root2], l, mid); rs[New] = merge(rs[root1], rs[root2], mid + 1, r); pushup(New); return New; } } } // namespace SGT namespace Tham { int root[maxn]; int len[maxn], fa[maxn], son[maxn][26], end = 1, tnt = 1; inline int insert(int C, int last) { end = ++tnt; len[end] = len[last] + 1; while (last && son[last][C] == 0) son[last][C] = end, last = fa[last]; if (!last) { fa[end] = 1; return end; } register int c = son[last][C]; if (len[last] + 1 == len[c]) { fa[end] = c; return end; } len[++tnt] = len[last] + 1; for (register int i = 0; i < 26; i += 1) son[tnt][i] = son[c][i]; fa[tnt] = fa[c], fa[c] = tnt; fa[end] = tnt; while (son[last][C] == c) son[last][C] = tnt, last = fa[last]; return end; } } // namespace Tham int Len; char ssd[maxn], S[maxn]; int head[maxn], to[maxn], nxt[maxn], tot; inline void add(int x, int y) { nxt[++tot] = head[x]; head[x] = tot; to[tot] = y; } void dfs(int now) { for (register int i = head[now]; i; i = nxt[i]) { dfs(to[i]); Tham::root[now] = SGT::merge(Tham::root[now], Tham::root[to[i]], 1, Len); } } int pos[maxn], id[maxn]; int main() { scanf( %s , S + 1); Len = strlen(S + 1); id[0] = pos[0] = 1; for (register int i = 1; i <= Len; i += 1) pos[i] = Tham::insert(S[i] - a , pos[i - 1]), SGT::change(Tham::root[pos[i]], 1, Len, i); for (register int i = 2; i <= Tham::tnt; i += 1) add(Tham::fa[i], i); dfs(1); int T; scanf( %d , &T); while (T--) { int l, r; scanf( %d %d %s , &l, &r, ssd + 1); int LL = strlen(ssd + 1), match = 0; for (register int i = 1; i <= LL; i += 1) { if (Tham::son[id[i - 1]][ssd[i] - a ]) id[i] = Tham::son[id[i - 1]][ssd[i] - a ], match += 1; else break; } bool ccf = false; for (register int i = match; i >= 0; i -= 1) { for (register int color = (i < LL ? ssd[i + 1] - a + 1 : 0); color < 26; color += 1) if (Tham::son[id[i]][color]) { int nxt = Tham::son[id[i]][color]; if (SGT::query(Tham::root[nxt], 1, Len, l + i, r)) { for (register int j = 1; j <= i; j += 1) printf( %c , ssd[j]); printf( %c n , char(color + 97)); ccf = true; break; } } if (ccf) break; } if (!ccf) puts( -1 ); } return 0; } |
module main(H0,H1,H2,H3,H4,H5,H6,H7,SW,KEY,LED);
input wire [3:0]KEY;
input wire [17:0]SW;
output wire [6:0]H0;
output wire [6:0]H1;
output wire [6:0]H2;
output wire [6:0]H3;
output wire [6:0]H4;
output wire [6:0]H5;
output wire [6:0]H6;
output wire [6:0]H7;
output wire [17:0]LED;
//CANCEL USELESS PINS
assign H1[5:0]=6'b111111;
assign H2=7'b1111111;
assign H3=7'b1111111;
assign H5=7'b1111111;
assign H7=7'b1111111;
//DEFINE INPUTS
wire [3:0]A;
wire [3:0]B;
wire [3:0]S;
wire CIN,COUT;
assign A[3:0]=SW[3:0];
assign B[3:0]=SW[7:4];
assign CIN=KEY[0];
//LINK OUTPUT
assign LED[3:0]=S[3:0];
assign LED[4]=COUT;
assign LED[17]=SW[17];
assign LED[16]=SW[16];
//PROGRAM START
wire [14:0]temp;
//RippieAdder u0(A,B,CIN,temp[3:0],temp[4]);
SuperAdder u1(A,B,CIN,temp[8:5],temp[9]);
Subtractor u2(A,B,temp[13:10],temp[14]);
//MUX3bit3to1(temp[3:0],temp[8:5],temp[13:10],SW[17:16],S);
//MUX1bit3to1(temp[4],temp[9],temp[14],SW[17:16],COUT);
assign H1[6]=~(SW[17]&&~COUT);
//OUTPUTDISPLAY
//translator t0(SW[3:0],H4);
//translator t1(SW[7:4],H6);
//translator t2(S,H0);
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream pipeline register
*/
module axis_pipeline_register #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// Register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter REG_TYPE = 2,
// Number of registers in pipeline
parameter LENGTH = 2
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
wire [DATA_WIDTH-1:0] axis_tdata[0:LENGTH];
wire [KEEP_WIDTH-1:0] axis_tkeep[0:LENGTH];
wire axis_tvalid[0:LENGTH];
wire axis_tready[0:LENGTH];
wire axis_tlast[0:LENGTH];
wire [ID_WIDTH-1:0] axis_tid[0:LENGTH];
wire [DEST_WIDTH-1:0] axis_tdest[0:LENGTH];
wire [USER_WIDTH-1:0] axis_tuser[0:LENGTH];
assign axis_tdata[0] = s_axis_tdata;
assign axis_tkeep[0] = s_axis_tkeep;
assign axis_tvalid[0] = s_axis_tvalid;
assign s_axis_tready = axis_tready[0];
assign axis_tlast[0] = s_axis_tlast;
assign axis_tid[0] = s_axis_tid;
assign axis_tdest[0] = s_axis_tdest;
assign axis_tuser[0] = s_axis_tuser;
assign m_axis_tdata = axis_tdata[LENGTH];
assign m_axis_tkeep = axis_tkeep[LENGTH];
assign m_axis_tvalid = axis_tvalid[LENGTH];
assign axis_tready[LENGTH] = m_axis_tready;
assign m_axis_tlast = axis_tlast[LENGTH];
assign m_axis_tid = axis_tid[LENGTH];
assign m_axis_tdest = axis_tdest[LENGTH];
assign m_axis_tuser = axis_tuser[LENGTH];
generate
genvar i;
for (i = 0; i < LENGTH; i = i + 1) begin : pipe_reg
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(REG_TYPE)
)
reg_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_tdata[i]),
.s_axis_tkeep(axis_tkeep[i]),
.s_axis_tvalid(axis_tvalid[i]),
.s_axis_tready(axis_tready[i]),
.s_axis_tlast(axis_tlast[i]),
.s_axis_tid(axis_tid[i]),
.s_axis_tdest(axis_tdest[i]),
.s_axis_tuser(axis_tuser[i]),
// AXI output
.m_axis_tdata(axis_tdata[i+1]),
.m_axis_tkeep(axis_tkeep[i+1]),
.m_axis_tvalid(axis_tvalid[i+1]),
.m_axis_tready(axis_tready[i+1]),
.m_axis_tlast(axis_tlast[i+1]),
.m_axis_tid(axis_tid[i+1]),
.m_axis_tdest(axis_tdest[i+1]),
.m_axis_tuser(axis_tuser[i+1])
);
end
endgenerate
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int const maxn = (int)2e6 + 1, inf = (int)2e9 + 1; map<char, int> pidr; int n, m, ans, cur, sz, a[maxn], b, l[maxn], r[maxn], x[maxn]; bool used[maxn]; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= m; i++) { cin >> l[i] >> r[i] >> x[i]; } for (int i = 1; i <= m; i++) { cur = 0; for (int j = l[i]; j <= r[i]; j++) if (a[j] < a[x[i]]) cur++; if (l[i] + cur == x[i]) cout << Yes << endl; else cout << No << endl; } return 0; } |
// nios_dut_mm_interconnect_0_avalon_st_adapter_011.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_011 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_011_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X , nand0_out, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); ; int n, m; cin >> n >> m; set<long long> s; long long ans = 0; long long a[n]; long long b[m]; long long mx = 0; map<long long, long long> mp; bool f = true; set<long long> st; for (int i = 0; i < n; i++) { cin >> a[i]; mx = max(mx, a[i]); s.insert(a[i]); ans += m * a[i]; st.insert(a[i]); mp[a[i]] += m - 1; } for (int i = 0; i < m; i++) { cin >> b[i]; if (b[i] < mx) f = false; } if (!f) { cout << -1 << endl; return 0; } sort(b, b + m); reverse(b, b + m); for (int i = 0; i < m; i++) { set<long long>::iterator it = s.upper_bound(b[i]); --it; if ((b[i] - *it) > 0 && st.find(b[i]) != st.end()) { continue; } ans += b[i] - (*it); mp[*it]--; if (mp[*it] == 0) s.erase(it); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int f[100010], r[2][100010]; vector<int> mat[2][100010]; void DFS(int a, int x) { r[x][a] = 1; if (x == 1 && f[a] == 1) return; for (int i = 0; i < mat[x][a].size(); i++) { int b = mat[x][a][i]; if (!r[x][b]) DFS(b, x); } } int main() { int n, m, a, b; cin >> n >> m; for (int i = 0; i < n; i++) cin >> f[i]; for (int i = 0; i < m; i++) { cin >> a >> b; a--; b--; mat[0][a].push_back(b); mat[1][b].push_back(a); } for (int i = 0; i < n; i++) if (!r[0][i] && f[i] == 1 && mat[0][i].size()) DFS(i, f[i] - 1); else if (!r[1][i] && f[i] == 2) DFS(i, f[i] - 1); for (int i = 0; i < n; i++) if (r[0][i] && r[1][i]) cout << 1 << ; else cout << 0 << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace ::std; const int V = 1e5 + 25; int arr[V]; map<int, int> mmap; int main() { int n; cin >> n; int mx = INT_MIN; int mn = INT_MAX; for (int i = 0; i < n; i++) { cin >> arr[i]; mx = max(mx, arr[i]); mn = min(mn, arr[i]); mmap[arr[i]]++; } if (mx - mn < 2) { cout << n << endl; for (int i = 0; i < n; i++) { cout << arr[i] << ; } cout << endl; return 0; } int cnt = 0; int a, b, c; int p, q, r; if (mmap.size() == 2) { for (auto x : mmap) { if (cnt == 0) p = x.first, a = x.second; if (cnt == 1) r = x.first, c = x.second; cnt++; } q = p + 1; b = 0; } else { for (auto x : mmap) { if (cnt == 0) p = x.first, a = x.second; if (cnt == 1) q = x.first, b = x.second; if (cnt == 2) r = x.first, c = x.second; cnt++; } } int b1 = b + 2 * min(a, c); int a1 = a - min(a, c); int c1 = c - min(a, c); int b2 = b % 2; int a2 = a + (b - b % 2) / 2; int c2 = c + (b - b % 2) / 2; int lhs = min(a1, a) + min(b1, b) + min(c1, c); int rhs = min(a2, a) + min(b2, b) + min(c2, c); if (lhs <= rhs) { printf( %d n , lhs); for (int i = 0; i < a1; i++) printf( %d , p); for (int i = 0; i < b1; i++) printf( %d , q); for (int i = 0; i < c1; i++) printf( %d , r); } else { printf( %d n , rhs); for (int i = 0; i < a2; i++) printf( %d , p); for (int i = 0; i < b2; i++) printf( %d , q); for (int i = 0; i < c2; i++) printf( %d , r); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, y, Y, it = 1, x1[100001], x2[100001], d[100001], u[100001]; int dist(int x, int y) { return abs(x - y); } int main() { scanf( %d%d%d%d , &n, &m, &y, &Y); for (int i = 1; i <= n; i++) scanf( %d , &x1[i]); for (int i = 1; i <= m; i++) { scanf( %d , &x2[i]); d[i] = 100000000; } x2[0] = -100000000; x2[m + 1] = 100000000; int ans = 0; for (int i = 1; i <= n; i++) { while (dist(x1[i], x2[it]) > dist(x1[i], x2[it + 1])) it++; if (u[it] == 0 || d[it] == dist(x1[i], x2[it])) { ans++; u[it] = 1; } else if (dist(x1[i], x2[it]) == dist(x1[i], x2[it + 1])) { ans++; u[it + 1] = 1; } d[it] = min(d[it], dist(x1[i], x2[it])); d[it + 1] = min(d[it + 1], dist(x1[i], x2[it + 1])); } printf( %d n , n - ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n, greater<int>()); for (int i = 0; i < n; i++) cout << a[i] << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); int ans = 0; if (a == b) { ans++; } else if (b == c) { ans++; } else if (b == d) { ans++; } if (a == c) { ans++; } else if (c == d) { ans++; } if (a == d) { ans++; } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long N, K, dp[501][501]; long long p2[501]; void pre() { long long i; p2[0] = 1; for (i = 1; i < 501; ++i) p2[i] = (p2[i - 1] * 2) % 1000000007; } long long rec(long long maxinc, long long cur) { if (maxinc > K) return 0; if (cur > N) return (maxinc == K); long long last = cur - 1; long long &ret = dp[maxinc][cur]; if (ret != -1) return ret; long long temp, mul = 1; ret = 0; long long cc = cur; for (; cur <= N; ++cur) { mul = (mul * p2[last]) % 1000000007; temp = (rec(maxinc + 1, cur + 1) * (p2[cur - last] - 1)) % 1000000007; ret = (ret + (temp * mul) % 1000000007) % 1000000007; } if (maxinc == K) ret = (ret + mul) % 1000000007; return ret; } int main() { pre(); while (scanf( %I64d %I64d , &N, &K) != EOF) { memset(dp, -1, sizeof(dp)); printf( %I64d n , rec(0, 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, p; char a[20000]; int b[20000]; int main() { cin >> n >> p; scanf( %s , a); memset(b, -1, sizeof(b)); for (int i = 0; i < n; ++i) { if (a[i] == . ) { if (i - p >= 0 && b[i - p] != -1) { b[i] = b[i - p] ^ 1; } } else { b[i] = a[i] - 0 ; ; if (i - p >= 0 && b[i - p] == -1) { b[i - p] = b[i] ^ 1; } } } for (int i = 0; i < n; ++i) { if (b[i] == -1) { if (i - p >= 0) b[i] = b[i - p] ^ 1; else b[i] = 0; } } int fg = 0; for (int i = 0; i < n; ++i) { if (i + p >= n) continue; if (b[i] != b[i + p]) fg = 1; } if (fg == 0) puts( No ); else { for (int i = 0; i < n; ++i) { printf( %d , b[i]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 7; const int M = 22; const long long mod = 1e9 + 7; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long s = 0; while (s * 10 + 9 <= n + n - 1) { s = s * 10 + 9; } if (s == n + n - 1) { cout << 1; } else { long long len = 1; while (len * 1ll * 10 <= 1ll * n + n - 1ll) { len *= 10; } long long i = s; long long ans = 0; for (; i <= n + n - 1; i += len) { if (i <= n + 1) { ans += (i - 1) / 2; } else { long long x = i - n; x = n - x + 1; ans += x / 2; } } cout << ans; } } |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF.v,v 1.9 2009/08/21 23:55:43 harikr Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// End Revision
`timescale 1 ps / 1 ps
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end
endmodule
|
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