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//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_arb_select #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter CKE_ODT_AUX = "FALSE",
parameter nSLOTS = 2,
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [5:0] mc_data_offset_1,
output wire [5:0] mc_data_offset_2,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH-1:0] rnk_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [5:0] col_channel_offset,
input [nBANK_MACHS-1:0] grant_config_r,
input rnk_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd0_row,
input send_cmd0_col,
input send_cmd1_row,
input send_cmd1_col,
input send_cmd2_row,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r = 1'b0;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
// calib_rd_data_offset for currently targeted rank
reg [5:0] rank_rddata_offset_0;
reg [5:0] rank_rddata_offset_1;
reg [5:0] rank_rddata_offset_2;
// Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]
assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;
assign mc_aux_out0[2] = 1'b0;
reg cke_r;
reg cke_ns;
generate
if(CKE_ODT_AUX == "FALSE")begin
always @(posedge clk)
begin
if (rst)
cke_r = 1'b1;
else
cke_r = cke_ns;
end
always @(*)
begin
cke_ns = 1'b1;
if (maint_sre_r & insert_maint_r1)
cke_ns = 1'b0;
else if (cke_r==1'b0)
begin
if (maint_srx_r & insert_maint_r1)
cke_ns = 1'b1;
else
cke_ns = 1'b0;
end
end
end
endgenerate
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ?
sent_col && col_rd_wr_r :
sent_col && col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate calib_rd_data_offset for current rank - only use rank 0 values for now
always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin
rank_rddata_offset_0 = calib_rddata_offset[5:0];
rank_rddata_offset_1 = calib_rddata_offset_1[5:0];
rank_rddata_offset_2 = calib_rddata_offset_2[5:0];
end
// generate data offset
generate
if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
else begin : gen_mc_data_offset_not_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
endgenerate
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
// ZQ, SRX or SRE/REFRESH
(maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK == 2)
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF" || EVEN_CWL_2T_MODE == "ON") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
if(EVEN_CWL_2T_MODE == "ON") begin
assign col_periodic_rd = col_periodic_rd_r;
assign col_ra = col_cmd_r[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_r[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_r[3+:ROW_WIDTH];
assign col_rmw = col_rmw_r;
assign col_rd_wr = col_rd_wr_r;
assign col_size = col_size_r;
assign col_row = col_row_r;
assign col_data_buf_addr = col_data_buf_addr_r;
end
else begin
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0 = {OUT_CMD_WIDTH{1'b1}};
reg cke0;
always @(send_cmd0_row or send_cmd0_col or row_cmd_ns or row_cmd_r or col_cmd_ns or col_cmd_r or cke_ns or cke_r ) begin
cmd0 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd0_row) cmd0 = row_cmd_ns;
if (send_cmd0_row && EVEN_CWL_2T_MODE == "ON" && nCK_PER_CLK == 2) cmd0 = row_cmd_r;
if (send_cmd0_col) cmd0 = col_cmd_ns;
if (send_cmd0_col && EVEN_CWL_2T_MODE == "ON") cmd0 = col_cmd_r;
if (send_cmd0_row) cke0 = cke_ns;
else cke0 = cke_r ;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(send_cmd1_row or send_cmd1_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd1 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_col) cmd1 = col_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(send_cmd2_row or send_cmd2_col or send_cmd2_pre or send_cmd3_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd2 = {OUT_CMD_WIDTH{1'b1}};
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_row) cmd2 = row_cmd_ns;
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd2_pre) cmd2 = pre_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0], mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cmd0;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH], mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cmd1;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH], mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cmd2;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH], mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} =
cmd3;
end
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
assign mc_cke[0] = cke0;
assign mc_cke[1] = cke_ns;
if(nCK_PER_CLK == 4) begin
assign mc_cke[2] = cke_ns;
assign mc_cke[3] = cke_ns;
end
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output rnk_config info.
reg [RANK_WIDTH-1:0] rnk_config_ns;
reg [RANK_WIDTH-1:0] rnk_config_r;
always @(/*AS*/grant_config_r
or rnk_config_r or rnk_config_strobe or req_rank_r or rst) begin
if (rst) rnk_config_ns = {RANK_WIDTH{1'b0}};
else begin
rnk_config_ns = rnk_config_r;
if (rnk_config_strobe)
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) rnk_config_ns = req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH];
end
end
always @(posedge clk) rnk_config_r <= #TCQ rnk_config_ns;
assign rnk_config = rnk_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && col_rd_wr_r :
slot_0_select && col_rd_wr_ns;
wire slot_0_write = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && ~col_rd_wr_r :
slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && col_rd_wr_r :
slot_1_select && col_rd_wr_ns;
wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && ~col_rd_wr_r :
slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
reg[1:0] mc_aux_out_r ;
reg[1:0] mc_aux_out_r_1 ;
reg[1:0] mc_aux_out_r_2 ;
always@(posedge clk) begin
mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;
mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;
mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;
mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;
end
if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];
end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;
end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v4_2_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v4_2_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v4_2_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v4_2_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter nXSDLL = 512,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, insert_maint_r,
// Inputs
clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,
maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,
slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input init_calib_complete;
wire accept_internal_ns = init_calib_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (init_calib_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
reg periodic_rd_cntr_r ;
always @(posedge clk) begin
if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;
else if (periodic_rd_r && periodic_rd_ack_r_lcl)
periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;
end
wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);
// wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Report an overall idle status
output idle;
assign idle = init_calib_complete && &idle_r;
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
mig_7series_v4_2_round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) begin
if (hi_priority)
was_priority <= #TCQ 1'b1;
else
was_priority <= #TCQ 1'b0;
end
// DRAM maintenance (refresh and ZQ) and self-refresh controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input maint_sre_r;
input maint_srx_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
wire start_maint;
wire maint_end;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r && ~periodic_rd_cntr_r) && ~maint_wip_r_lcl;
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer
// below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || (maint_req_r && ~periodic_rd_cntr_r));
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ and self-refresh hit on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear;
reg maint_rdy_r1;
reg maint_srx_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;
assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ, SRE or SRX commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, SRE and SRX, each rank present will receive a command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count
or rst or send_cnt_r or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ
// command until the end of the maintenance operation.
// Compute values for RFC, ZQ and XSDLL periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?
nRFC :
(nCK_PER_CLK == 2) ?
((nRFC/2) + (nRFC%2)) :
// (nCK_PER_CLK == 4)
((nRFC/4) + ((nRFC%4) ? 1 : 0));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?
tZQCS :
(nCK_PER_CLK == 2) ?
((tZQCS/2) + (tZQCS%2)) :
// (nCK_PER_CLK == 4)
((tZQCS/4) + ((tZQCS%4) ? 1 : 0));
localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?
nXSDLL :
(nCK_PER_CLK == 2) ?
((nXSDLL/2) + (nXSDLL%2)) :
// (nCK_PER_CLK == 4)
((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));
localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_xsdll_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r
or rfc_zq_xsdll_timer_r or rst) begin
rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;
if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?
nZQCS_CLKS :
maint_sre_r ?
{RFC_ZQ_TIMER_WIDTH{1'b0}} :
maint_srx_r ?
nXSDLL_CLKS :
nRFC_CLKS;
else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =
rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;
// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_xsdll_timer
endgenerate
endmodule // bank_common
|
//*****************************************************************************
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v4_2_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v4_2_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v4_2_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v4_2_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v4_2_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v4_2_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v4_2_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
//*****************************************************************************
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// Top level memory sequencer structural block. This block
// instantiates the rank, bank, and column machines.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_mc #
(
parameter TCQ = 100, // clk->out delay(sim only)
parameter ADDR_CMD_MODE = "1T", // registered or
// 1Tfered mem?
parameter BANK_WIDTH = 3, // bank address width
parameter BM_CNT_WIDTH = 2, // # BM counter width
// i.e., log2(nBANK_MACHS)
parameter BURST_MODE = "8", // Burst length
parameter CL = 5, // Read CAS latency
// (in clk cyc)
parameter CMD_PIPE_PLUS1 = "ON", // add register stage
// between MC and PHY
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 4, // # of unique CS outputs
parameter CWL = 5, // Write CAS latency
// (in clk cyc)
parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.
// user src/dest buf addr)
parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width
parameter DATA_WIDTH = 64, // Data bus width
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3", // Memory I/F type:
// "DDR3", "DDR2"
parameter ECC = "OFF", // ECC ON/OFF?
parameter ECC_WIDTH = 8, // # of ECC bits
parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)
parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits
parameter nBANK_MACHS = 4, // # of bank machines (BM)
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
// frequency ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs
// per rank
parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in
parameter nSLOTS = 1, // # DIMM slots in system
parameter ORDERING = "NORM", // request ordering mode
parameter PAYLOAD_WIDTH = 64, // Width of data payload
// from PHY
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // row address width
parameter RTT_NOM = "40", // Nominal ODT value
parameter RTT_WR = "120", // Write ODT value
parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0
parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1
parameter STARVE_LIMIT = 2, // max # of times a user
// request is allowed to
// lose arbitration when
// reordering is enabled
parameter tCK = 2500, // memory clk period(ps)
parameter tCKE = 10000, // CKE minimum pulse (ps)
parameter tFAW = 40000, // four activate window(ps)
parameter tRAS = 37500, // ACT->PRE cmd period (ps)
parameter tRCD = 12500, // ACT->R/W delay (ps)
parameter tREFI = 7800000, // average periodic
// refresh interval(ps)
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter tRFC = 110000, // REF->ACT/REF delay (ps)
parameter tRP = 12500, // PRE cmd period (ps)
parameter tRRD = 10000, // ACT->ACT period (ps)
parameter tRTP = 7500, // Read->PRE cmd delay (ps)
parameter tWTR = 7500, // Internal write->read
// delay (ps)
// requiring DLL lock (CKs)
parameter tZQCS = 64, // ZQCS cmd period (CKs)
parameter tZQI = 128_000_000, // ZQCS interval (ps)
parameter tPRDI = 1_000_000, // pS
parameter USER_REFRESH = "OFF" // Whether user manages REF
)
(
// System inputs
input clk,
input rst,
// Physical memory slot presence
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Native Interface
input [2:0] cmd,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,
input hi_priority,
input size,
input [BANK_WIDTH-1:0] bank,
input [COL_WIDTH-1:0] col,
input [RANK_WIDTH-1:0] rank,
input [ROW_WIDTH-1:0] row,
input use_addr,
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept,
output accept_ns,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
output rd_data_en,
output rd_data_end,
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,
output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr /* synthesis syn_maxfan = 30 */,
output reg wr_data_en,
output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset /* synthesis syn_maxfan = 30 */,
output mc_read_idle,
output mc_ref_zq_wip,
// ECC interface
input correct_en,
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [DQS_WIDTH - 1:0] fi_xor_we,
input [DQ_WIDTH -1 :0 ] fi_xor_wrdata,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_single,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
input app_zq_req,
input app_sr_req,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// MC <==> PHY Interface
output reg [nCK_PER_CLK-1:0] mc_ras_n,
output reg [nCK_PER_CLK-1:0] mc_cas_n,
output reg [nCK_PER_CLK-1:0] mc_we_n,
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output reg [1:0] mc_odt,
output reg [nCK_PER_CLK-1:0] mc_cke,
output wire mc_reset_n,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,
output reg mc_wrdata_en,
output wire mc_cmd_wren,
output wire mc_ctl_wren,
output reg [2:0] mc_cmd,
output reg [5:0] mc_data_offset,
output reg [5:0] mc_data_offset_1,
output reg [5:0] mc_data_offset_2,
output reg [1:0] mc_cas_slot,
output reg [3:0] mc_aux_out0,
output reg [3:0] mc_aux_out1,
output reg [1:0] mc_rank_cnt,
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
input phy_rddata_valid,
input init_calib_complete,
input [6*RANKS-1:0] calib_rd_data_offset,
input [6*RANKS-1:0] calib_rd_data_offset_1,
input [6*RANKS-1:0] calib_rd_data_offset_2
);
assign mc_reset_n = 1'b1; // never reset memory
assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)
assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)
// Ensure there is always at least one rank present during operation
`ifdef MC_SVA
ranks_present: assert property
(@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));
`endif
// Reserved. Do not change.
localparam nPHY_WRLAT = 2;
// always delay write data control unless ECC mode is enabled
localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1;
// Ensure that write control is delayed for appropriate CWL
/*`ifdef MC_SVA
delay_wr_data_zero_CWL_le_6: assert property
(@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));
`endif*/
// Never retrieve WR_DATA_ADDR early
localparam EARLY_WR_DATA_ADDR = "OFF";
//***************************************************************************
// Convert timing parameters from time to clock cycles
//***************************************************************************
localparam nCKE = cdiv(tCKE, tCK);
localparam nRP = cdiv(tRP, tCK);
localparam nRCD = cdiv(tRCD, tCK);
localparam nRAS = cdiv(tRAS, tCK);
localparam nFAW = cdiv(tFAW, tCK);
localparam nRFC = cdiv(tRFC, tCK);
// Convert tWR. As per specification, write recover for autoprecharge
// cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12
localparam nWR_CK = cdiv(15000, tCK) ;
localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;
// tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2
localparam nRRD_CK = cdiv(tRRD, tCK);
localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK
: (nRRD_CK < 2) ? 2 : nRRD_CK;
localparam nWTR_CK = cdiv(tWTR, tCK);
localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK
: (nWTR_CK < 2) ? 2 : nWTR_CK;
localparam nRTP_CK = cdiv(tRTP, tCK);
localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK
: (nRTP_CK < 2) ? 2 : nRTP_CK;
// Add a cycle to CL/CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam CL_M = (REG_CTRL == "ON") ? CL + 1 : CL;
// Tuneable delay between read and write data on the DQ bus
localparam DQRD2DQWR_DLY = 4;
// CKE minimum pulse width for self-refresh (SRE->SRX minimum time)
localparam nCKESR = nCKE + 1;
// Delay from SRE to command requiring locked DLL. Currently fixed at 512 for
// all devices per JEDEC spec.
localparam tXSDLL = 512;
//***************************************************************************
// Set up maintenance counter dividers
//***************************************************************************
// CK clock divisor to generate maintenance prescaler period (round down)
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);
// Maintenance prescaler divisor for refresh timer. Essentially, this is
// just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst
// case delay from the time we get a tick from the refresh counter to the
// time that we can actually issue the REF command. Thus, subtract tRCD, CL,
// data burst time and tRP for each implemented bank machine to ensure that
// all transactions can complete before tREFI expires
localparam REFRESH_TIMER_DIV =
USER_REFRESH == "ON" ? 0 :
(tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS)) / MAINT_PRESCALER_PERIOD;
// Periodic read (RESERVED - not currently required or supported in 7 series)
// tPRDI should only be set to 0
// localparam tPRDI = 0; // Do NOT change.
localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;
// Convert maintenance prescaler from ps to ns
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
// Maintenance prescaler divisor for ZQ calibration (ZQCS) timer
localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;
// Bus width required to broadcast a single bit rank signal among all the
// bank machines - 1 bit per rank, per bank
localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;
//***************************************************************************
// Define 2T, CWL-even mode to enable multi-fabric-cycle 2T commands
//***************************************************************************
localparam EVEN_CWL_2T_MODE =
((ADDR_CMD_MODE == "2T") && (!(CWL % 2))) ? "ON" : "OFF";
//***************************************************************************
// Reserved feature control.
//***************************************************************************
// Open page wait mode is reserved.
// nOP_WAIT is the number of states a bank machine will park itself
// on an otherwise inactive open page before closing the page. If
// nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
// the bank machine will remain parked until the pool of idle bank machines
// are less than LOW_IDLE_CNT. At which point parked bank machines
// are selected to exit until the number of idle bank machines exceeds the
// LOW_IDLE_CNT.
localparam nOP_WAIT = 0; // Open page mode
localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold
//***************************************************************************
// Internal wires
//***************************************************************************
wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
wire [ROW_WIDTH-1:0] col_a;
wire [BANK_WIDTH-1:0] col_ba;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
wire col_periodic_rd;
wire [RANK_WIDTH-1:0] col_ra;
wire col_rmw;
wire col_rd_wr;
wire [ROW_WIDTH-1:0] col_row;
wire col_size;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
wire dq_busy_data;
wire ecc_status_valid;
wire [RANKS-1:0] inhbt_act_faw_r;
wire [RANKS-1:0] inhbt_rd;
wire [RANKS-1:0] inhbt_wr;
wire insert_maint_r1;
wire [RANK_WIDTH-1:0] maint_rank_r;
wire maint_req_r;
wire maint_wip_r;
wire maint_zq_r;
wire maint_sre_r;
wire maint_srx_r;
wire periodic_rd_ack_r;
wire periodic_rd_r;
wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
wire rd_rmw;
wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
wire [nBANK_MACHS-1:0] sending_col;
wire [nBANK_MACHS-1:0] sending_row;
wire sent_col;
wire sent_col_r;
wire wr_ecc_buf;
wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
// MC/PHY optional pipeline stage support
wire [nCK_PER_CLK-1:0] mc_ras_n_ns;
wire [nCK_PER_CLK-1:0] mc_cas_n_ns;
wire [nCK_PER_CLK-1:0] mc_we_n_ns;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;
wire [1:0] mc_odt_ns;
wire [nCK_PER_CLK-1:0] mc_cke_ns;
wire [3:0] mc_aux_out0_ns;
wire [3:0] mc_aux_out1_ns;
wire [1:0] mc_rank_cnt_ns = col_ra;
wire [2:0] mc_cmd_ns;
wire [5:0] mc_data_offset_ns;
wire [5:0] mc_data_offset_1_ns;
wire [5:0] mc_data_offset_2_ns;
wire [1:0] mc_cas_slot_ns;
wire mc_wrdata_en_ns;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;
wire wr_data_en_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;
integer i;
// MC Read idle support
wire col_read_fifo_empty;
wire mc_read_idle_ns;
reg mc_read_idle_r;
// MC Maintenance in progress with bus idle indication
wire maint_ref_zq_wip;
wire mc_ref_zq_wip_ns;
reg mc_ref_zq_wip_r;
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Optional pipeline register stage on MC/PHY interface
//***************************************************************************
generate
if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface
always @(posedge clk) begin
mc_address <= #TCQ mc_address_ns;
mc_bank <= #TCQ mc_bank_ns;
mc_cas_n <= #TCQ mc_cas_n_ns;
mc_cs_n <= #TCQ mc_cs_n_ns;
mc_odt <= #TCQ mc_odt_ns;
mc_cke <= #TCQ mc_cke_ns;
mc_aux_out0 <= #TCQ mc_aux_out0_ns;
mc_aux_out1 <= #TCQ mc_aux_out1_ns;
mc_cmd <= #TCQ mc_cmd_ns;
mc_ras_n <= #TCQ mc_ras_n_ns;
mc_we_n <= #TCQ mc_we_n_ns;
mc_data_offset <= #TCQ mc_data_offset_ns;
mc_data_offset_1 <= #TCQ mc_data_offset_1_ns;
mc_data_offset_2 <= #TCQ mc_data_offset_2_ns;
mc_cas_slot <= #TCQ mc_cas_slot_ns;
mc_wrdata_en <= #TCQ mc_wrdata_en_ns;
mc_rank_cnt <= #TCQ mc_rank_cnt_ns;
wr_data_addr <= #TCQ wr_data_addr_ns;
wr_data_en <= #TCQ wr_data_en_ns;
wr_data_offset <= #TCQ wr_data_offset_ns;
end // always @ (posedge clk)
end // block: cmd_pipe_plus
else begin : cmd_pipe_plus0 // don't register interface
always @( mc_address_ns or mc_aux_out0_ns or mc_aux_out1_ns or
mc_bank_ns or mc_cas_n_ns or mc_cmd_ns or mc_cs_n_ns or
mc_odt_ns or mc_cke_ns or mc_data_offset_ns or
mc_data_offset_1_ns or mc_data_offset_2_ns or mc_rank_cnt_ns or
mc_ras_n_ns or mc_we_n_ns or mc_wrdata_en_ns or
wr_data_addr_ns or wr_data_en_ns or wr_data_offset_ns or
mc_cas_slot_ns)
begin
mc_address = #TCQ mc_address_ns;
mc_bank = #TCQ mc_bank_ns;
mc_cas_n = #TCQ mc_cas_n_ns;
mc_cs_n = #TCQ mc_cs_n_ns;
mc_odt = #TCQ mc_odt_ns;
mc_cke = #TCQ mc_cke_ns;
mc_aux_out0 = #TCQ mc_aux_out0_ns;
mc_aux_out1 = #TCQ mc_aux_out1_ns;
mc_cmd = #TCQ mc_cmd_ns;
mc_ras_n = #TCQ mc_ras_n_ns;
mc_we_n = #TCQ mc_we_n_ns;
mc_data_offset = #TCQ mc_data_offset_ns;
mc_data_offset_1 = #TCQ mc_data_offset_1_ns;
mc_data_offset_2 = #TCQ mc_data_offset_2_ns;
mc_cas_slot = #TCQ mc_cas_slot_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
end // always @ (...
end // block: cmd_pipe_plus0
endgenerate
//***************************************************************************
// Indicate when there are no pending reads so that input features can be
// powered down
//***************************************************************************
assign mc_read_idle_ns = col_read_fifo_empty & init_calib_complete;
always @(posedge clk) mc_read_idle_r <= #TCQ mc_read_idle_ns;
assign mc_read_idle = mc_read_idle_r;
//***************************************************************************
// Indicate when there is a refresh in progress and the bus is idle so that
// tap adjustments can be made
//***************************************************************************
assign mc_ref_zq_wip_ns = maint_ref_zq_wip && col_read_fifo_empty;
always @(posedge clk) mc_ref_zq_wip_r <= mc_ref_zq_wip_ns;
assign mc_ref_zq_wip = mc_ref_zq_wip_r;
//***************************************************************************
// Manage rank-level timing and maintanence
//***************************************************************************
mig_7series_v4_2_rank_mach #
(
// Parameters
.BURST_MODE (BURST_MODE),
.CL (CL),
.CWL (CWL),
.CS_WIDTH (CS_WIDTH),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV)
)
rank_mach0
(
// Outputs
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.col_rd_wr (col_rd_wr),
.clk (clk),
.init_calib_complete (init_calib_complete),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.rst (rst),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])
);
//***************************************************************************
// Manage requests, reordering and bank timing
//***************************************************************************
mig_7series_v4_2_bank_mach #
(
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CL (CL_M),
.CWL (CWL_M),
.CKE_ODT_AUX (CKE_ODT_AUX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nOP_WAIT (nOP_WAIT),
.nRAS (nRAS),
.nRCD (nRCD),
.nRFC (nRFC),
.nRP (nRP),
.nRTP (nRTP),
.nSLOTS (nSLOTS),
.nWR (nWR),
.nXSDLL (tXSDLL),
.ORDERING (ORDERING),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.STARVE_LIMIT (STARVE_LIMIT),
.tZQCS (tZQCS)
)
bank_mach0
(
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank_ns),
.mc_address (mc_address_ns),
.mc_ras_n (mc_ras_n_ns),
.mc_cas_n (mc_cas_n_ns),
.mc_we_n (mc_we_n_ns),
.mc_cs_n (mc_cs_n_ns),
.mc_odt (mc_odt_ns),
.mc_cke (mc_cke_ns),
.mc_aux_out0 (mc_aux_out0_ns),
.mc_aux_out1 (mc_aux_out1_ns),
.mc_cmd (mc_cmd_ns),
.mc_data_offset (mc_data_offset_ns),
.mc_data_offset_1 (mc_data_offset_1_ns),
.mc_data_offset_2 (mc_data_offset_2_ns),
.mc_cas_slot (mc_cas_slot_ns),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
// Inputs
.bank (bank[BANK_WIDTH-1:0]),
.calib_rddata_offset (calib_rd_data_offset),
.calib_rddata_offset_1 (calib_rd_data_offset_1),
.calib_rddata_offset_2 (calib_rd_data_offset_2),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.init_calib_complete (init_calib_complete),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.use_addr (use_addr)
);
//***************************************************************************
// Manage DQ bus
//***************************************************************************
mig_7series_v4_2_col_mach #
(
// Parameters
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.nPHY_WRLAT (nPHY_WRLAT),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
col_mach0
(
// Outputs
.mc_wrdata_en (mc_wrdata_en_ns),
.dq_busy_data (dq_busy_data),
.ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),
.ecc_status_valid (ecc_status_valid),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.rd_rmw (rd_rmw),
.wr_data_addr (wr_data_addr_ns),
.wr_data_en (wr_data_en_ns),
.wr_data_offset (wr_data_offset_ns),
.wr_ecc_buf (wr_ecc_buf),
.col_read_fifo_empty (col_read_fifo_empty),
// Inputs
.clk (clk),
.rst (rst),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.sent_col (EVEN_CWL_2T_MODE == "ON" ? sent_col_r : sent_col)
);
//***************************************************************************
// Implement ECC
//***************************************************************************
// Total ECC word length = ECC code width + Data width
localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;
generate
if (ECC == "OFF") begin : ecc_off
assign rd_data = phy_rd_data;
assign mc_wrdata = wr_data;
assign mc_wrdata_mask = wr_data_mask;
assign ecc_single = 4'b0;
assign ecc_multiple = 4'b0;
end
else begin : ecc_on
wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_i;
// Merge and encode
mig_7series_v4_2_ecc_merge_enc #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_merge_enc0
(
// Outputs
.mc_wrdata (mc_wrdata_i),
.mc_wrdata_mask (mc_wrdata_mask),
// Inputs
.clk (clk),
.rst (rst),
.h_rows (h_rows),
.rd_merge_data (rd_merge_data),
.raw_not_ecc (raw_not_ecc),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask)
);
// Decode and fix
mig_7series_v4_2_ecc_dec_fix #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_dec_fix0
(
// Outputs
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_data (rd_data),
// Inputs
.clk (clk),
.rst (rst),
.correct_en (correct_en),
.phy_rddata (phy_rd_data),
.ecc_status_valid (ecc_status_valid),
.h_rows (h_rows)
);
// ECC Buffer
mig_7series_v4_2_ecc_buf #
(
// Parameters
.TCQ (TCQ),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_buf0
(
// Outputs
.rd_merge_data (rd_merge_data),
// Inputs
.clk (clk),
.rst (rst),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_offset (wr_data_offset),
.wr_ecc_buf (wr_ecc_buf)
);
// Generate ECC table
mig_7series_v4_2_ecc_gen #
(
// Parameters
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.ECC_WIDTH (ECC_WIDTH)
)
ecc_gen0
(
// Outputs
.h_rows (h_rows)
);
if (ECC == "ON") begin : gen_fi_xor_inst
reg mc_wrdata_en_r;
wire mc_wrdata_en_i;
always @(posedge clk) begin
mc_wrdata_en_r <= mc_wrdata_en;
end
assign mc_wrdata_en_i = mc_wrdata_en_r;
mig_7series_v4_2_fi_xor #(
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
fi_xor0
(
.clk (clk),
.wrdata_in (mc_wrdata_i),
.wrdata_out (mc_wrdata),
.wrdata_en (mc_wrdata_en_i),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata)
);
end
else begin : gen_wrdata_passthru
assign mc_wrdata = mc_wrdata_i;
end
`ifdef DISPLAY_H_MATRIX
integer i;
always @(negedge rst) begin
$display ("**********************************************");
$display ("H Matrix:");
for (i=0; i<ECC_WIDTH; i=i+1)
$display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]);
$display ("**********************************************");
end
`endif
end
endgenerate
endmodule // mc
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
//periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank || periodic_rd_timer_one)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Block for logic common to all rank machines. Contains
// a clock prescaler, and arbiters for refresh and periodic
// read functions.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_rank_common #
(
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
// Inputs
clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
periodic_rd_request, periodic_rd_ack_r
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Maintenance and periodic read prescaler. Nominally 200 nS.
localparam ONE = 1;
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
input init_calib_complete;
reg maint_prescaler_tick_r_lcl;
generate
begin : maint_prescaler
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns =
(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/init_calib_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~init_calib_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <=
#TCQ maint_prescaler_tick_ns;
end
endgenerate
output wire maint_prescaler_tick_r;
assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
// Refresh timebase. Nominically 7800 nS.
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
wire refresh_tick_lcl;
generate
begin : refresh_timer
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or refresh_tick_lcl or refresh_timer_r) begin
refresh_timer_ns = refresh_timer_r;
if (~init_calib_complete || refresh_tick_lcl)
refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
refresh_timer_ns =
refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
end
always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
assign refresh_tick_lcl = (refresh_timer_r ==
ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
end
endgenerate
output wire refresh_tick;
assign refresh_tick = refresh_tick_lcl;
// ZQ timebase. Nominally 128 mS
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
input app_zq_req;
input insert_maint_r1;
reg maint_zq_r_lcl;
reg zq_request = 1'b0;
generate
if (DRAM_TYPE == "DDR3") begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~init_calib_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
zq_tick = (zq_timer_r ==
ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
reg zq_request_r;
wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) ||
zq_tick ||
(app_zq_req && init_calib_complete));
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/init_calib_complete or zq_request_r)
zq_request = init_calib_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
// Self-refresh control
localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
input app_sr_req;
reg maint_sre_r_lcl;
reg maint_srx_r_lcl;
reg sre_request = 1'b0;
wire inhbt_srx;
generate begin : sr_cntrl
// SRE request. Set request with user request.
begin : sre_request_logic
reg sre_request_r;
wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
always @(init_calib_complete or sre_request_r)
sre_request = init_calib_complete && sre_request_r;
end // sre_request_logic
// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
begin : ckesr_timer
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
ckesr_timer_ns = ckesr_timer_r;
if (insert_maint_r1 && maint_sre_r_lcl)
ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
else if(|ckesr_timer_r)
ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
end
always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
assign inhbt_srx = |ckesr_timer_r;
end // ckesr_timer
end
endgenerate
// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
// DRAM maintenance operations and self-refresh have their own channel in the
// queue. There is also a single, very simple bank machine
// dedicated to these operations. Its assumed that the
// maintenance operations can be completed quickly enough
// to avoid any queuing.
//
// ZQ, refresh and self-refresh requests share a channel into controller.
// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
// appended just below that.
input[RANKS-1:0] refresh_request;
input maint_wip_r;
reg maint_req_r_lcl;
reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
input [7:0] slot_0_present;
input [7:0] slot_1_present;
generate
begin : maintenance_request
// Maintenance request pipeline.
reg upd_last_master_r;
reg new_maint_rank_r;
wire maint_busy = upd_last_master_r || new_maint_rank_r ||
maint_req_r_lcl || maint_wip_r;
wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
//wire upd_last_master_ns = |maint_request && ~maint_busy;
wire upd_last_master_ns = |maint_request && ~maint_wip_r;
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
wire upd_last_master_pls = upd_last_master_r & (~new_maint_rank_r);
// Arbitrate maintenance requests.
wire [RANKS+1:0] maint_grant_ns;
wire [RANKS+1:0] maint_grant_r;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (RANKS+2))
maint_arb0
(.grant_ns (maint_grant_ns),
.grant_r (maint_grant_r),
.upd_last_master (upd_last_master_pls),
.current_master (maint_grant_r),
.req (maint_request),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
// If refresh select the maintenance rank from the winning rank controller.
// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
// or self-refresh requests. The bank machine will enable CS for the number of
// states equal to the the number of occupied slots. This will produce a
// command to every occupied slot, but not in any particular order.
wire [7:0] present = slot_0_present | slot_1_present;
integer i;
reg [RANK_WIDTH-1:0] maint_rank_ns;
wire maint_zq_ns = ~rst && (upd_last_master_pls
? maint_grant_r[RANKS]
: maint_zq_r_lcl);
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
? ~app_sr_req & ~inhbt_srx
: maint_srx_r_lcl && upd_last_master_pls
? maint_grant_r[RANKS+1]
: maint_srx_r_lcl);
wire maint_sre_ns = ~rst && (upd_last_master_pls
? maint_grant_r[RANKS+1]
: maint_sre_r_lcl && ~maint_srx_ns);
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
or maint_sre_ns or maint_srx_ns or present or rst
or upd_last_master_pls) begin
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
else begin
maint_rank_ns = maint_rank_r_lcl;
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
for (i=0; i<8; i=i+1)
if (~present[maint_rank_ns])
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
end
else
if (upd_last_master_pls)
for (i=0; i<RANKS; i=i+1)
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
end
end
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
end // block: maintenance_request
endgenerate
output wire maint_zq_r;
assign maint_zq_r = maint_zq_r_lcl;
output wire maint_sre_r;
assign maint_sre_r = maint_sre_r_lcl;
output wire maint_srx_r;
assign maint_srx_r = maint_srx_r_lcl;
output wire maint_req_r;
assign maint_req_r = maint_req_r_lcl;
output wire [RANK_WIDTH-1:0] maint_rank_r;
assign maint_rank_r = maint_rank_r_lcl;
// Indicate whether self-refresh is active or not.
output app_sr_active;
reg app_sr_active_r;
wire app_sr_active_ns =
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
assign app_sr_active = app_sr_active_r;
// Acknowledge user REF and ZQ Requests
input app_ref_req;
output app_ref_ack;
wire app_ref_ack_ns;
wire app_ref_ns;
reg app_ref_ack_r = 1'b0;
reg app_ref_r = 1'b0;
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
assign app_ref_ack = app_ref_ack_r;
output app_zq_ack;
wire app_zq_ack_ns;
wire app_zq_ns;
reg app_zq_ack_r = 1'b0;
reg app_zq_r = 1'b0;
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
assign app_zq_ack_ns = app_zq_r && ~zq_request;
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
assign app_zq_ack = app_zq_ack_r;
// Periodic reads to maintain PHY alignment.
// Demand insertion of periodic read as soon as
// possible. Since the is a single rank, bank compare mechanism
// must be used, periodic reads must be forced in at the
// expense of not accepting a normal request.
input [RANKS-1:0] periodic_rd_request;
reg periodic_rd_r_lcl;
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
input periodic_rd_ack_r;
output wire [RANKS-1:0] clear_periodic_rd_request;
output wire periodic_rd_r;
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
generate
// This is not needed in 7-Series and should remain disabled
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
// Maintenance request pipeline.
reg periodic_rd_r_cnt;
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
reg upd_last_master_r;
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
wire upd_last_master_ns =
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
wire periodic_rd_ns = init_calib_complete &&
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
always @(posedge clk) begin
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
end
// Arbitrate periodic read requests.
wire [RANKS-1:0] periodic_rd_grant_ns;
reg [RANKS-1:0] periodic_rd_grant_r;
mig_7series_v4_2_round_robin_arb #
(.WIDTH (RANKS))
periodic_rd_arb0
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master_r),
.current_master (periodic_rd_grant_r[RANKS-1:0]),
.req (periodic_rd_request[RANKS-1:0]),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
? periodic_rd_grant_ns
: periodic_rd_grant_r;
// Encode and set periodic read rank into periodic_rd_rank_r.
integer i;
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
or upd_last_master_r) begin
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (periodic_rd_grant_r[i])
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
end
always @(posedge clk) periodic_rd_rank_r_lcl <=
#TCQ periodic_rd_rank_ns;
// Once the request is dropped in the queue, it might be a while before it
// emerges. Can't clear the request based on seeing the read issued.
// Need to clear the request as soon as its made it into the queue.
assign clear_periodic_rd_request =
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
assign periodic_rd_r = periodic_rd_r_lcl;
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
end else begin
// Disable periodic reads
assign clear_periodic_rd_request = {RANKS{1'b0}};
assign periodic_rd_r = 1'b0;
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
end // block: periodic_read_request
endgenerate
// Indicate that a refresh is in progress. The PHY will use this to schedule
// tap adjustments during idle bus time
reg maint_ref_zq_wip_r = 1'b0;
output maint_ref_zq_wip;
always @(posedge clk)
if(rst)
maint_ref_zq_wip_r <= #TCQ 1'b0;
else if((zq_request || |refresh_request) && insert_maint_r1)
maint_ref_zq_wip_r <= #TCQ 1'b1;
else if(~maint_wip_r)
maint_ref_zq_wip_r <= #TCQ 1'b0;
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v4_2_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v4_2_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v4_2_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_dec_fix.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ecc_dec_fix
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_data, ecc_single, ecc_multiple,
// Inputs
clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
);
input clk;
input rst;
// Compute syndromes.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
genvar k;
genvar m;
generate
for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
assign syndrome_ns[k*ECC_WIDTH+m] =
^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
end
end
endgenerate
reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
// Extract payload bits from raw DRAM bits and register.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
genvar i;
generate
for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
end
endgenerate
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
// Regenerate h_matrix from h_rows leaving out the identity part
// since we're not going to correct the ECC bits themselves.
genvar n;
genvar p;
wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
generate
for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
end
end
endgenerate
// Compute flip bits.
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
genvar q;
genvar r;
generate
for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
assign flip_bits[q*DATA_WIDTH+r] =
h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
end
end
endgenerate
// Correct data.
output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
input correct_en;
integer s;
always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
for (s=0; s<2*nCK_PER_CLK; s=s+1)
if (correct_en)
rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
// Copy raw payload bits if ECC_TEST is ON.
localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
genvar t;
generate
if (RAW_BIT_WIDTH > 0)
for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
always @(/*AS*/ecc_rddata_r)
rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
end
endgenerate
// Generate status information.
input ecc_status_valid;
output wire [2*nCK_PER_CLK-1:0] ecc_single;
output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
genvar v;
generate
for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
assign ecc_single[v] = ecc_status_valid && ~zero && odd;
assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module mig_7series_v4_2_ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if (trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : mig_7series_v4_2_axi_fi_xor.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
//*****************************************************************************
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_2_fi_xor #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// External Memory Data Width
parameter integer DQ_WIDTH = 72,
parameter integer DQS_WIDTH = 9,
parameter integer nCK_PER_CLK = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_in ,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] wrdata_out ,
input wire wrdata_en ,
input wire [DQS_WIDTH-1:0] fi_xor_we ,
input wire [DQ_WIDTH-1:0] fi_xor_wrdata
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [DQ_WIDTH-1:0] fi_xor_data = {DQ_WIDTH{1'b0}};
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// Register in the fi_xor_wrdata on a byte width basis
generate
begin
genvar i;
for (i = 0; i < DQS_WIDTH; i = i + 1) begin : assign_fi_xor_data
always @(posedge clk) begin
if (wrdata_en) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= {DQ_PER_DQS{1'b0}};
end
else if (fi_xor_we[i]) begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_wrdata[i*DQ_PER_DQS+:DQ_PER_DQS];
end
else begin
fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS] <= fi_xor_data[i*DQ_PER_DQS+:DQ_PER_DQS];
end
end
end
end
endgenerate
assign wrdata_out[0+:DQ_WIDTH] = wrdata_in[0+:DQ_WIDTH] ^ fi_xor_data[0+:DQ_WIDTH];
// Pass through upper bits
assign wrdata_out[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH] = wrdata_in[DQ_WIDTH+:(2*nCK_PER_CLK-1)*DQ_WIDTH];
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_axi.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:04 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v4_2_ddr3_7Series, xlnx_mig_7_ddr3, 2018.3" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v4_2,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=1, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=COMP, MEMORY_PART=mt41j256m16xx-107, DQ_WIDTH=32, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v4_2_memc_ui_top_axi #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter SKIP_CALIB = "FALSE",
parameter TAPSPERKCLK = 56,
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 30,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// Instatiates register slices before upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Same as C_S_AXI_REG_EN0, but this register is after
// the upsizer
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
parameter FPGA_VOLT_TYPE = "N"
)
(
// Clock and reset ports
input clk,
input clk_div2,
input rst_div2,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o,
output [2*nCK_PER_CLK-1:0] app_ecc_single_err,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// Ports to be used with SKIP_CALIB defined
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
input aresetn,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
// AXI CTRL port
input s_axi_ctrl_awvalid,
output s_axi_ctrl_awready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
// Slave Interface Write Data Ports
input s_axi_ctrl_wvalid,
output s_axi_ctrl_wready,
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
// Slave Interface Write Response Ports
output s_axi_ctrl_bvalid,
input s_axi_ctrl_bready,
output [1:0] s_axi_ctrl_bresp,
// Slave Interface Read Address Ports
input s_axi_ctrl_arvalid,
output s_axi_ctrl_arready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
// Slave Interface Read Data Ports
output s_axi_ctrl_rvalid,
input s_axi_ctrl_rready,
output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output [1:0] s_axi_ctrl_rresp,
// Interrupt output
output interrupt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output [1023:0] dbg_poc
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
localparam INTERFACE = "AXI4";
// Port Interface.
// # = UI - User Interface,
// = AXI4 - AXI4 Interface.
localparam C_FAMILY = "virtex7";
localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire app_correct_en;
wire app_correct_en_i;
wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_rd_data_to_axi;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_hi_pri;
wire app_sz;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o;
wire app_wdf_wren;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
reg init_calib_complete_r;
//***************************************************************************
// Added a single register stage for the calib_done to fix timing
//***************************************************************************
always @(posedge clk)
init_calib_complete_r <= init_calib_complete;
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v4_2_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
mem_intfc0
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
// skip calibration i/f
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.dbg_poc (dbg_poc[1023:0])
);
genvar o;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(o=0;o<8;o=o+1) begin
assign app_wdf_data[o*72+:72] = {app_wdf_data_axi_o[o*64+:8],app_wdf_data_axi_o[o*64+:64]} ;
assign app_wdf_mask[o*9+:9] = {app_wdf_mask_axi_o[o*8],app_wdf_mask_axi_o[o*8+:8]} ;
end
end else begin
end
end else begin
assign app_wdf_data = app_wdf_data_axi_o ;
assign app_wdf_mask = app_wdf_mask_axi_o ;
end
endgenerate
genvar e;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(e=0;e<8;e=e+1) begin
assign app_rd_data_to_axi[e*64+:64] = app_rd_data[e*72+:64];
end
end
end else begin
assign app_rd_data_to_axi = app_rd_data;
end
endgenerate
mig_7series_v4_2_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
// ECC ports
.app_raw_not_ecc (app_raw_not_ecc),
.app_ecc_multiple_err (app_ecc_multiple_err_o),
.app_ecc_single_err (app_ecc_single_err),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
mig_7series_v4_2_axi_mc #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL),
.C_MC_ADDR_WIDTH (ADDR_WIDTH),
.C_MC_BURST_MODE (BURST_MODE),
.C_MC_nCK_PER_CLK (nCK_PER_CLK),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_ECC (ECC)
)
u_axi_mc
(
.aclk (clk),
.aresetn (aresetn),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// MC Master Interface
//CMD PORT
.mc_app_en (app_en),
.mc_app_cmd (app_cmd),
.mc_app_sz (app_sz),
.mc_app_addr (app_addr),
.mc_app_hi_pri (app_hi_pri),
.mc_app_rdy (app_rdy),
.mc_init_complete (init_calib_complete_r),
//DATA PORT
.mc_app_wdf_wren (app_wdf_wren),
.mc_app_wdf_mask (app_wdf_mask_axi_o),
.mc_app_wdf_data (app_wdf_data_axi_o),
.mc_app_wdf_end (app_wdf_end),
.mc_app_wdf_rdy (app_wdf_rdy),
.mc_app_rd_valid (app_rd_data_valid),
.mc_app_rd_data (app_rd_data_to_axi),
.mc_app_rd_end (app_rd_data_end),
.mc_app_ecc_multiple_err (app_ecc_multiple_err_o)
);
generate
if (ECC == "ON") begin : gen_axi_ctrl_top
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r;
mig_7series_v4_2_axi_ctrl_top #
(
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) ,
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) ,
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) ,
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) ,
.C_ECC_TEST (ECC_TEST) ,
.C_DQ_WIDTH (DQ_WIDTH) ,
.C_ECC_WIDTH (ECC_WIDTH) ,
.C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) ,
.C_BANK_WIDTH (BANK_WIDTH) ,
.C_ROW_WIDTH (ROW_WIDTH) ,
.C_COL_WIDTH (COL_WIDTH) ,
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) ,
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) ,
.C_NCK_PER_CLK (nCK_PER_CLK) ,
.C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH)
)
axi_ctrl_top_0
(
.aclk (clk) ,
.aresetn (aresetn) ,
.s_axi_awvalid (s_axi_ctrl_awvalid) ,
.s_axi_awready (s_axi_ctrl_awready) ,
.s_axi_awaddr (s_axi_ctrl_awaddr) ,
.s_axi_wvalid (s_axi_ctrl_wvalid) ,
.s_axi_wready (s_axi_ctrl_wready) ,
.s_axi_wdata (s_axi_ctrl_wdata) ,
.s_axi_bvalid (s_axi_ctrl_bvalid) ,
.s_axi_bready (s_axi_ctrl_bready) ,
.s_axi_bresp (s_axi_ctrl_bresp) ,
.s_axi_arvalid (s_axi_ctrl_arvalid) ,
.s_axi_arready (s_axi_ctrl_arready) ,
.s_axi_araddr (s_axi_ctrl_araddr) ,
.s_axi_rvalid (s_axi_ctrl_rvalid) ,
.s_axi_rready (s_axi_ctrl_rready) ,
.s_axi_rdata (s_axi_ctrl_rdata) ,
.s_axi_rresp (s_axi_ctrl_rresp) ,
.interrupt (interrupt) ,
.init_complete (init_calib_complete_r) ,
.ecc_single (ecc_single) ,
.ecc_multiple (ecc_multiple) ,
.ecc_err_addr (ecc_err_addr) ,
.app_correct_en (app_correct_en) ,
.dfi_rddata (dbg_rddata_r) ,
.fi_xor_we (fi_xor_we) ,
.fi_xor_wrdata (fi_xor_wrdata)
);
// dbg_rddata delayed one cycle to match ecc_*
always @(posedge clk) begin
dbg_rddata_r <= dbg_rddata;
end
//if(ECC_TEST == "ON") begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}};
// assign app_correct_en_i = 'b0 ;
//end else begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
// assign app_correct_en_i = app_correct_en ;
//end
assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
assign app_correct_en_i = app_correct_en ;
end
else begin : gen_no_axi_ctrl_top
assign s_axi_ctrl_awready = 1'b0;
assign s_axi_ctrl_wready = 1'b0;
assign s_axi_ctrl_bvalid = 1'b0;
assign s_axi_ctrl_bresp = 2'b0;
assign s_axi_ctrl_arready = 1'b0;
assign s_axi_ctrl_rvalid = 1'b0;
assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}};
assign s_axi_ctrl_rresp = 2'b0;
assign interrupt = 1'b0;
assign app_correct_en = 1'b1;
assign app_raw_not_ecc = 4'b0;
assign fi_xor_we = {DQ_WIDTH/8{1'b0}};
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}};
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mem_intfc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_mem_intfc #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "1T",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane
// data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 4, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter ORDERING = "NORM",
parameter PHASE_DETECT = "OFF" , // to phy_top
parameter IBUF_LPWR_MODE = "OFF", // to phy_top
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG", //to phy_top
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH" , // to phy_top
parameter REG_CTRL = "OFF" , // to phy_top
parameter RTT_NOM = "60" , // to phy_top
parameter RTT_WR = "120" , // to phy_top
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF" , // to phy_top
parameter DEBUG_PORT = "OFF" , // to phy_top
parameter CAL_WIDTH = "HALF" , // to phy_top
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter nDQS_COL0 = DQS_WIDTH,
parameter nDQS_COL1 = 0,
parameter nDQS_COL2 = 0,
parameter nDQS_COL3 = 0,
parameter DQS_LOC_COL0 = 144'h11100F0E0D0C0B0A09080706050403020100,
parameter DQS_LOC_COL1 = 0,
parameter DQS_LOC_COL2 = 0,
parameter DQS_LOC_COL3 = 0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter USER_REFRESH = "OFF", // Choose whether MC or User manages REF
parameter TEMP_MON_EN = "ON", // Enable/disable temperature monitoring
parameter IDELAY_ADJ = "ON", // Adjust IDELAY value (-1)
parameter FINE_PER_BIT = "ON", // Use finedelay per-bit de-skew
parameter CENTER_COMP_MODE = "ON", // Use Center compensation table for PI
parameter PI_VAL_ADJ = "ON", // Adjust PI final value (-1)
parameter TAPSPERKCLK = 56,
parameter SKIP_CALIB = "FALSE", // default value "FALSE"
parameter FPGA_VOLT_TYPE = "N"
)
(
input clk_ref,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input poc_sample_pd,
input error,
input reset,
output rst_tg_mc,
input [BANK_WIDTH-1:0] bank, // To mc0 of mc.v
input clk ,
input clk_div2, // mem_refclk divided by 2 for PI incdec
input rst_div2, // reset in clk_div2 domain
input [2:0] cmd, // To mc0 of mc.v
input [COL_WIDTH-1:0] col, // To mc0 of mc.v
input correct_en,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, // To mc0 of mc.v
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input hi_priority, // To mc0 of mc.v
input [RANK_WIDTH-1:0] rank, // To mc0 of mc.v
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [ROW_WIDTH-1:0] row, // To mc0 of mc.v
input rst, // To mc0 of mc.v, ...
input size, // To mc0 of mc.v
input [7:0] slot_0_present, // To mc0 of mc.v
input [7:0] slot_1_present, // To mc0 of mc.v
input use_addr, // To mc0 of mc.v
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept, // From mc0 of mc.v
output accept_ns, // From mc0 of mc.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From mc0 of mc.v
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [ROW_WIDTH-1:0] ddr_addr, // From phy_top0 of phy_top.v
output [BANK_WIDTH-1:0] ddr_ba, // From phy_top0 of phy_top.v
output ddr_cas_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck , // From phy_top0 of phy_top.v
output [CKE_WIDTH-1:0] ddr_cke, // From phy_top0 of phy_top.v
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, // From phy_top0 of phy_top.v
output [DM_WIDTH-1:0] ddr_dm, // From phy_top0 of phy_top.v
output [ODT_WIDTH-1:0] ddr_odt, // From phy_top0 of phy_top.v
output ddr_ras_n, // From phy_top0 of phy_top.v
output ddr_reset_n, // From phy_top0 of phy_top.v
output ddr_parity,
output ddr_we_n, // From phy_top0 of phy_top.v
output init_calib_complete,
output init_wrcal_complete,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
output [2*nCK_PER_CLK-1:0] ecc_single,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
// From mc0 of mc.v
output rd_data_en, // From mc0 of mc.v
output rd_data_end, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, // From mc0 of mc.v
output [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr, // From mc0 of mc.v
output wr_data_en, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset, // From mc0 of mc.v
// Ports to be used for SKIP_CALIB="TRUE"
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
inout [DQ_WIDTH-1:0] ddr_dq, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs_n, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs // To/From phy_top0 of phy_top.v
,input [11:0] device_temp
//phase shift clock control
,output psen
,output psincdec
,input psdone
,input [DQ_WIDTH/8-1:0] fi_xor_we
,input [DQ_WIDTH-1:0] fi_xor_wrdata
,input dbg_sel_pi_incdec
,input dbg_sel_po_incdec
,input [DQS_CNT_WIDTH:0] dbg_byte_sel
,input dbg_pi_f_inc
,input dbg_pi_f_dec
,input dbg_po_f_inc
,input dbg_po_f_stg23_sel
,input dbg_po_f_dec
,output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt
,output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt
,output dbg_rddata_valid
,output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt
,output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt
,output [255:0] dbg_phy_wrlvl
,output [5:0] dbg_pi_counter_read_val
,output [8:0] dbg_po_counter_read_val
,output ref_dll_lock
,input rst_phaser_ref
,input iddr_rst
,output [6*RANKS-1:0] dbg_rd_data_offset
,output [255:0] dbg_phy_init
,output [255:0] dbg_prbs_rdlvl
,output [255:0] dbg_dqs_found_cal
,output dbg_pi_phaselock_start
,output dbg_pi_phaselocked_done
,output dbg_pi_phaselock_err
,output dbg_pi_dqsfound_start
,output dbg_pi_dqsfound_done
,output dbg_pi_dqsfound_err
,output dbg_wrcal_start
,output dbg_wrcal_done
,output dbg_wrcal_err
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [6*RANKS-1:0] dbg_calib_rd_data_offset_1
,output [6*RANKS-1:0] dbg_calib_rd_data_offset_2
,output [5:0] dbg_data_offset
,output [5:0] dbg_data_offset_1
,output [5:0] dbg_data_offset_2
,output dbg_oclkdelay_calib_start
,output dbg_oclkdelay_calib_done
,output [255:0] dbg_phy_oclkdelay_cal
,output [DRAM_WIDTH*16 -1:0]dbg_oclkdelay_rd_data
,output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r
,output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps
,output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
,output [1023:0] dbg_poc
);
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam SLOT_0_CONFIG_MC = (nSLOTS == 2)? 8'b0000_0101 : 8'b0000_1111;
localparam SLOT_1_CONFIG_MC = (nSLOTS == 2)? 8'b0000_1010 : 8'b0000_0000;
// 8*tREFI in ps is divided by fabric clock period also in ps. 270 is the number
// of fabric clock cycles that accounts for the Writes, read, and PRECHARGE time
localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270;
reg [7:0] slot_0_present_mc;
reg [7:0] slot_1_present_mc;
reg user_periodic_rd_req = 1'b0;
reg user_ref_req = 1'b0;
reg user_zq_req = 1'b0;
// MC/PHY interface
wire [nCK_PER_CLK-1:0] mc_ras_n;
wire [nCK_PER_CLK-1:0] mc_cas_n;
wire [nCK_PER_CLK-1:0] mc_we_n;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank;
wire [nCK_PER_CLK-1 :0] mc_cke ;
wire [1:0] mc_odt ;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n;
wire mc_reset_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
wire mc_wrdata_en;
wire mc_ref_zq_wip;
wire tempmon_sample_en;
wire idle;
wire mc_cmd_wren;
wire mc_ctl_wren;
wire [2:0] mc_cmd;
wire [1:0] mc_cas_slot;
wire [5:0] mc_data_offset;
wire [5:0] mc_data_offset_1;
wire [5:0] mc_data_offset_2;
wire [3:0] mc_aux_out0;
wire [3:0] mc_aux_out1;
wire [1:0] mc_rank_cnt;
wire phy_mc_ctl_full;
wire phy_mc_cmd_full;
wire phy_mc_data_full;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data;
wire phy_rddata_valid;
wire [6*RANKS-1:0] calib_rd_data_offset_0;
wire [6*RANKS-1:0] calib_rd_data_offset_1;
wire [6*RANKS-1:0] calib_rd_data_offset_2;
wire init_calib_complete_w;
wire init_wrcal_complete_w;
wire mux_rst;
wire mux_calib_complete;
// assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything
// about CWL. There is also nCWL parameter. Need to clean it up.
localparam CWL_T = (DRAM_TYPE == "DDR3") ? CWL : CL-1;
assign init_calib_complete = init_calib_complete_w;
assign init_wrcal_complete = init_wrcal_complete_w;
assign mux_calib_complete = (PRE_REV3ES == "OFF") ? init_calib_complete_w :
(init_calib_complete_w | init_wrcal_complete_w);
assign mux_rst = (PRE_REV3ES == "OFF") ? rst : reset;
assign dbg_calib_rd_data_offset_1 = calib_rd_data_offset_1;
assign dbg_calib_rd_data_offset_2 = calib_rd_data_offset_2;
assign dbg_data_offset = mc_data_offset;
assign dbg_data_offset_1 = mc_data_offset_1;
assign dbg_data_offset_2 = mc_data_offset_2;
// Enable / disable temperature monitoring
assign tempmon_sample_en = TEMP_MON_EN == "OFF" ? 1'b0 : mc_ref_zq_wip;
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @ (slot_0_present or slot_1_present) begin
slot_0_present_mc = slot_0_present;
slot_1_present_mc = slot_1_present;
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_1_present[0] or slot_1_present[1]) begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
//Two slot configuration, one slot present, single rank
4'b1000: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0000;
end
4'b0010: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_0010;
end
// Two slot configuration, one slot present, dual rank
4'b1100: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0000;
end
4'b0011: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_1010;
end
// Two slot configuration, one rank per slot
4'b1010: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - One slot with dual rank and the other with single rank
4'b1011: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_1010;
end
4'b1110: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - two ranks per slot
4'b1111: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_1010;
end
endcase
end
end
endgenerate
mig_7series_v4_2_mc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nSLOTS (nSLOTS),
.CL (CL),
.nCS_PER_RANK (nCS_PER_RANK),
.CWL (CWL_T),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.STARVE_LIMIT (STARVE_LIMIT),
.SLOT_0_CONFIG (SLOT_0_CONFIG_MC),
.SLOT_1_CONFIG (SLOT_1_CONFIG_MC),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.tPRDI (tPRDI),
.USER_REFRESH (USER_REFRESH))
mc0
(.app_periodic_rd_req (1'b0),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cke (mc_cke),
.mc_odt (mc_odt),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_cas_slot (mc_cas_slot),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.rd_data (rd_data),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.mc_read_idle (idle),
.mc_ref_zq_wip (mc_ref_zq_wip),
// Inputs
.init_calib_complete (mux_calib_complete),
.calib_rd_data_offset (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.correct_en (correct_en),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.hi_priority (hi_priority),
.rank (rank[RANK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1 :0]),
.row (row[ROW_WIDTH-1:0]),
.rst (mux_rst),
.size (size),
.slot_0_present (slot_0_present_mc[7:0]),
.slot_1_present (slot_1_present_mc[7:0]),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.use_addr (use_addr));
// following calculations should be moved inside PHY
// odt bus should be added to PHY.
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
localparam nCL = CL;
localparam nCWL = CWL_T;
`ifdef MC_SVA
ddr2_improper_CL: assert property
(@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL > 6) || (CL < 3)))));
// Not needed after the CWL fix for DDR2
// ddr2_improper_CWL: assert property
// (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1))));
`endif
mig_7series_v4_2_ddr_phy_top #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.REFCLK_FREQ (REFCLK_FREQ),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CA_MIRROR (CA_MIRROR),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.nCS_PER_RANK (nCS_PER_RANK),
.CS_WIDTH (CS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.CKE_WIDTH (CKE_WIDTH),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DRAM_TYPE (DRAM_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.ROW_WIDTH (ROW_WIDTH),
.AL (AL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (nCL),
.CWL (nCWL),
.tRFC (tRFC),
.tREFI (tREFI),
.tCK (tCK),
.OUTPUT_DRV (OUTPUT_DRV),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.WRLVL (WRLVL),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
// Prevent the following simulation-related parameters from
// being overridden for synthesis - for synthesis only the
// default values of these parameters should be used
// synthesis translate_off
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
// synthesis translate_on
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DEBUG_PORT (DEBUG_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
ddr_phy_top0
(
// Outputs
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_dm (ddr_dm),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.init_calib_complete (init_calib_complete_w),
.init_wrcal_complete (init_wrcal_complete_w),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cke (mc_cke),
.mc_odt (mc_odt),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cas_slot (mc_cas_slot),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
.idle (idle),
.mem_refclk (mem_refclk),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
// Inouts
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
// Inputs
.clk_ref (clk_ref),
.freq_refclk (freq_refclk),
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)
,.device_temp (device_temp)
,.tempmon_sample_en (tempmon_sample_en)
,.psen (psen)
,.psincdec (psincdec)
,.psdone (psdone)
,.calib_tap_req (calib_tap_req)
,.calib_tap_addr (calib_tap_addr)
,.calib_tap_load (calib_tap_load)
,.calib_tap_val (calib_tap_val)
,.calib_tap_load_done (calib_tap_load_done)
,.dbg_sel_pi_incdec (dbg_sel_pi_incdec)
,.dbg_sel_po_incdec (dbg_sel_po_incdec)
,.dbg_byte_sel (dbg_byte_sel)
,.dbg_pi_f_inc (dbg_pi_f_inc)
,.dbg_po_f_inc (dbg_po_f_inc)
,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel)
,.dbg_pi_f_dec (dbg_pi_f_dec)
,.dbg_po_f_dec (dbg_po_f_dec)
,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt)
,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt)
,.dbg_rddata_valid (dbg_rddata_valid)
,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt)
,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt)
,.dbg_phy_wrlvl (dbg_phy_wrlvl)
,.ref_dll_lock (ref_dll_lock)
,.rst_phaser_ref (rst_phaser_ref)
,.iddr_rst (iddr_rst)
,.dbg_rd_data_offset (dbg_rd_data_offset)
,.dbg_phy_init (dbg_phy_init)
,.dbg_prbs_rdlvl (dbg_prbs_rdlvl)
,.dbg_dqs_found_cal (dbg_dqs_found_cal)
,.dbg_po_counter_read_val (dbg_po_counter_read_val)
,.dbg_pi_counter_read_val (dbg_pi_counter_read_val)
,.dbg_pi_phaselock_start (dbg_pi_phaselock_start)
,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done)
,.dbg_pi_phaselock_err (dbg_pi_phaselock_err)
,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start)
,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done)
,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err)
,.dbg_wrcal_start (dbg_wrcal_start)
,.dbg_wrcal_done (dbg_wrcal_done)
,.dbg_wrcal_err (dbg_wrcal_err)
,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal)
,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start)
,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
,.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r)
,.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps)
,.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps)
,.dbg_poc (dbg_poc[1023:0])
);
endmodule
|
/*****************************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $
// $Author: $
// $DateTime: $
// $Change: $
// Description:
// This verilog file is a paramertizable I/O termination for
// the single byte lane.
// to create a N byte-lane wide phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
//////////////////////////////////////////////////////////////////
*****************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_byte_group_io #(
// bit lane existance
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter PO_DATA_CTL = "FALSE",
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter real TCK = 2500.0,
// local usage only, don't pass down
parameter BUS_WIDTH = 12,
parameter SYNTHESIS = "FALSE"
)
(
input [9:0] mem_dq_in,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input mem_dqs_in,
output mem_dqs_out,
output mem_dqs_ts,
output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used
output dqs_to_phaser,
input iserdes_clk,
input iserdes_clkb,
input iserdes_clkdiv,
input phy_clk,
input rst,
input oserdes_rst,
input iserdes_rst,
input [1:0] oserdes_dqs,
input [1:0] oserdes_dqsts,
input [(4*BUS_WIDTH)-1:0] oserdes_dq,
input [1:0] oserdes_dqts,
input oserdes_clk,
input oserdes_clk_delayed,
input oserdes_clkdiv,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input idelayctrl_refclk,
input [29:0] fine_delay ,
input fine_delay_sel
);
/// INSTANCES
localparam ISERDES_DQ_DATA_RATE = "DDR";
localparam ISERDES_DQ_DATA_WIDTH = 4;
localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE";
localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE";
localparam ISERDES_DQ_INIT_Q1 = 1'b0;
localparam ISERDES_DQ_INIT_Q2 = 1'b0;
localparam ISERDES_DQ_INIT_Q3 = 1'b0;
localparam ISERDES_DQ_INIT_Q4 = 1'b0;
localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3";
localparam ISERDES_NUM_CE = 2;
localparam ISERDES_DQ_IOBDELAY = "IFD";
localparam ISERDES_DQ_OFB_USED = "FALSE";
localparam ISERDES_DQ_SERDES_MODE = "MASTER";
localparam ISERDES_DQ_SRVAL_Q1 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q2 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q3 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q4 = 1'b0;
localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE";
wire [BUS_WIDTH-1:0] data_in_dly;
wire [BUS_WIDTH-1:0] oserdes_dq_buf;
wire [BUS_WIDTH-1:0] oserdes_dqts_buf;
wire oserdes_dqs_buf;
wire oserdes_dqsts_buf;
wire [9:0] data_in;
wire tbyte_out;
reg [29:0] fine_delay_r;
assign mem_dq_out = oserdes_dq_buf;
assign mem_dq_ts = oserdes_dqts_buf;
assign data_in = mem_dq_in;
assign mem_dqs_out = oserdes_dqs_buf;
assign mem_dqs_ts = oserdes_dqsts_buf;
assign dqs_to_phaser = mem_dqs_in;
reg iserdes_clk_d;
always @(*)
iserdes_clk_d = iserdes_clk;
reg idelay_ld_rst;
reg rst_r1;
reg rst_r2;
reg rst_r3;
reg rst_r4;
always @(posedge phy_clk) begin
rst_r1 <= #1 rst;
rst_r2 <= #1 rst_r1;
rst_r3 <= #1 rst_r2;
rst_r4 <= #1 rst_r3;
end
always @(posedge phy_clk) begin
if (rst)
idelay_ld_rst <= #1 1'b1;
else if (rst_r4)
idelay_ld_rst <= #1 1'b0;
end
always @ (posedge phy_clk) begin
if(rst)
fine_delay_r <= #1 1'b0;
else if(fine_delay_sel)
fine_delay_r <= #1 fine_delay;
end
genvar i;
generate
for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_
if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_
ISERDESE2 #(
.DATA_RATE ( ISERDES_DQ_DATA_RATE),
.DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),
.DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),
.INIT_Q1 ( ISERDES_DQ_INIT_Q1),
.INIT_Q2 ( ISERDES_DQ_INIT_Q2),
.INIT_Q3 ( ISERDES_DQ_INIT_Q3),
.INIT_Q4 ( ISERDES_DQ_INIT_Q4),
.INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),
.NUM_CE ( ISERDES_NUM_CE),
.IOBDELAY ( ISERDES_DQ_IOBDELAY),
.OFB_USED ( ISERDES_DQ_OFB_USED),
.SERDES_MODE ( ISERDES_DQ_SERDES_MODE),
.SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),
.SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),
.SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),
.SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)
)
iserdesdq
(
.O (),
.Q1 (iserdes_dout[4*i + 3]),
.Q2 (iserdes_dout[4*i + 2]),
.Q3 (iserdes_dout[4*i + 1]),
.Q4 (iserdes_dout[4*i + 0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iserdes_clk_d),
.CLKB (!iserdes_clk_d),
.CLKDIVP (iserdes_clkdiv),
.CLKDIV (),
.DDLY (data_in_dly[i]),
.D (data_in[i]), // dedicated route to iob for debugging
// or as needed, select with IOBDELAY
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
// NOTE: OCLK is not used in this design, but is required to meet
// a design rule check in map and bitgen. Do not disconnect it.
.OCLK (oserdes_clk),
.OCLKB (),
.OFB (),
.RST (1'b0),
// .RST (iserdes_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
localparam IDELAYE2_DELAY_SRC = "IDATAIN";
localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE";
localparam IDELAYE2_PIPE_SEL = "FALSE";
localparam IDELAYE2_ODELAY_TYPE = "FIXED";
localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 :
(FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0;
localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY";
if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYE2_FINEDELAY #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.FINEDELAY ( IDELAYE2_FINEDELAY_IN),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (5'b00000),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.IFDLY (fine_delay_r[i*3+:3]),
.INC (idelay_inc),
.LD (idelay_ld | idelay_ld_rst),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end else begin : idelay_dq
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYE2 #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (5'b00000),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.INC (idelay_inc),
.LD (idelay_ld | idelay_ld_rst),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end
end // iserdes_dq
else begin
assign iserdes_dout[4*i + 3] = 0;
assign iserdes_dout[4*i + 2] = 0;
assign iserdes_dout[4*i + 1] = 0;
assign iserdes_dout[4*i + 0] = 0;
end
end // input_
endgenerate // iserdes_dq_
localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;
localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;
localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;
localparam OSERDES_DQ_INIT_OQ = 1'b1;
localparam OSERDES_DQ_INIT_TQ = 1'b1;
localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT";
localparam OSERDES_DQ_ODELAY_USED = 0;
localparam OSERDES_DQ_SERDES_MODE = "MASTER";
localparam OSERDES_DQ_SRVAL_OQ = 1'b1;
localparam OSERDES_DQ_SRVAL_TQ = 1'b1;
// note: obuf used in control path case, no ts input so width irrelevant
localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1;
localparam OSERDES_DQS_DATA_RATE_OQ = "DDR";
localparam OSERDES_DQS_DATA_RATE_TQ = "DDR";
localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr
localparam OSERDES_DQS_DATA_WIDTH = 4;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam OSERDES_TBYTE_CTL = "TRUE";
generate
localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH;
if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("TRUE")
)
oserdes_slave_ts
(
.OFB (),
.OQ (),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (),
.D2 (),
.D3 (),
.D4 (),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TCE (1'b1),
.TBYTEOUT (tbyte_out),
.TBYTEIN (tbyte_out)
);
end // slave_ts
for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_
if ( BITLANES[i]) begin : oserdes_dq_
if ( PO_DATA_CTL == "TRUE" ) begin : ddr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL (OSERDES_TBYTE_CTL),
.TBYTE_SRC ("FALSE")
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (oserdes_dqts_buf[i]),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (/*oserdes_dqts[0]*/),
.T2 (/*oserdes_dqts[0]*/),
.T3 (/*oserdes_dqts[1]*/),
.T4 (/*oserdes_dqts[1]*/),
.TCE (1'b1),
.TBYTEIN (tbyte_out)
);
end
else begin : sdr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH)
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (),
.T2 (),
.T3 (),
.T4 (),
.TCE (1'b1),
.TBYTEIN ()
);
end // ddr
end // oserdes_dq_
end // output_
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqs
(
.Q (oserdes_dqs_buf),
.D1 (oserdes_dqs[0]),
.D2 (oserdes_dqs[1]),
.C (oserdes_clk_delayed),
.R (1'b0),
.S (),
.CE (1'b1)
);
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqsts
( .Q (oserdes_dqsts_buf),
.D1 (oserdes_dqsts[0]),
.D2 (oserdes_dqsts[0]),
.C (oserdes_clk_delayed),
.R (),
.S (1'b0),
.CE (1'b1)
);
end // sdr rate
else begin:null_dqs
end
endgenerate
endmodule // byte_group_io
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_lane.v#4 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
//`include "phy.vh"
module mig_7series_v4_2_ddr_byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b1111_1111_1111,
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter RCLK_SELECT_LANE = "B",
parameter PC_CLK_RATIO = 4,
parameter USE_PRE_POST_FIFO = "FALSE",
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "FALSE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SEL_CLK_OFFSET = 0,
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_BYPASS = "FALSE",
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
// OSERDES
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
//IDELAY
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
// local constants, do not pass in from above
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8,
parameter PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1
,parameter CKE_ODT_AUX = "FALSE"
,parameter PI_DIV2_INCDEC = "FALSE"
)(
input rst,
input phy_clk,
input rst_pi_div2,
input clk_div2,
input freq_refclk,
input mem_refclk,
input idelayctrl_refclk,
input sync_pulse,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
output [11:0] ddr_ck_out,
output rclk,
input if_empty_def,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output pre_fifo_a_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input if_rst,
input [2:0] byte_rd_en_oth_lanes,
input [1:0] byte_rd_en_oth_banks,
output byte_rd_en,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
(PO_DATA_CTL == "FALSE" || PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE :
(PC_CLK_RATIO == 2) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_4_X_8";
localparam L_OSERDES_DATA_RATE = (OSERDES_DATA_RATE != "UNDECLARED") ? OSERDES_DATA_RATE : ((PO_DATA_CTL == "FALSE" && PC_CLK_RATIO == 4) ? "SDR" : "DDR") ;
localparam L_OSERDES_DATA_WIDTH = (OSERDES_DATA_WIDTH != "UNDECLARED") ? OSERDES_DATA_WIDTH : 4;
localparam real L_FREQ_REF_PERIOD_NS = (TCK >= 2500.0) ? (TCK/(PI_FREQ_REF_DIV == "DIV2" ? 2 : 1)/1000.0) : TCK/1000.0; // DIV2 change
localparam real L_MEM_REF_PERIOD_NS = TCK/1000.0;
localparam real L_PHASE_REF_PERIOD_NS = TCK/1000.0;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam PO_DCD_CORRECTION = "ON";
localparam [2:0] PO_DCD_SETTING = (PO_DCD_CORRECTION == "ON") ? 3'b111 : 3'b000;
localparam DQS_AUTO_RECAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? 1 : 0; // DIV2 change
localparam DQS_FIND_PATTERN = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && TCK >= 2500)) ? "001" : "000"; // DIV2 change
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire iserdes_clk;
wire iserdes_clkdiv;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire po_oserdes_rst;
wire empty_post_fifo;
reg [3:0] if_empty_r /* synthesis syn_maxfan = 3 */;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
reg ififo_rst = 1'b1;
reg ofifo_rst = 1'b1;
wire of_wren_pre;
wire [79:0] pre_fifo_dout;
wire pre_fifo_full;
wire pre_fifo_rden;
wire [5:0] ddr_ck_out_q;
wire ififo_rd_en_in /* synthesis syn_maxfan = 10 */;
wire oserdes_clkdiv;
wire oserdes_clk_delayed;
wire po_rd_enable;
always @(posedge phy_clk) begin
ififo_rst <= #1 pi_rst_dqs_find | if_rst ;
// reset only data o-fifos on reset of dqs_found
ofifo_rst <= #1 (pi_rst_dqs_find & PO_DATA_CTL == "TRUE") | rst;
end
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
//assign #(25) phy_rd_en_ = phy_rd_en;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = empty_post_fifo;
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
assign byte_rd_en = 1'b1;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign ififo_rd_en_in = !if_empty_def ? ((&byte_rd_en_oth_banks) && (&byte_rd_en_oth_lanes) && byte_rd_en) :
((|byte_rd_en_oth_banks) || (|byte_rd_en_oth_lanes) || byte_rd_en);
if (USE_PRE_POST_FIFO == "TRUE") begin : if_post_fifo_gen
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
if_empty_r[0] <= #(025) if_empty_;
if_empty_r[1] <= #(025) if_empty_;
if_empty_r[2] <= #(025) if_empty_;
if_empty_r[3] <= #(025) if_empty_;
end
mig_7series_v4_2_ddr_if_post_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (4), //2 // depth - account for up to 2 cycles of skew
.WIDTH (80) // width
)
u_ddr_if_post_fifo
(
.clk (phy_clk),
.rst (ififo_rst),
.empty_in (if_empty_r),
.rd_en_in (ififo_rd_en_in),
.d_in (rd_data_r),
.empty_out (empty_post_fifo),
.byte_rd_en (byte_rd_en),
.d_out (phy_din)
);
end
else begin : phy_din_gen
assign phy_din = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
assign empty_post_fifo = if_empty_;
end
end
endgenerate
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
generate
if ( USE_PRE_POST_FIFO == "TRUE" ) begin : of_pre_fifo_gen
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = pre_fifo_dout;
mig_7series_v4_2_ddr_of_pre_fifo #
(
.TCQ (25), // simulation CK->Q delay
.DEPTH (9), // depth - set to 9 to accommodate flow control
.WIDTH (80) // width
)
u_ddr_of_pre_fifo
(
.clk (phy_clk),
.rst (ofifo_rst),
.full_in (of_full),
.wr_en_in (phy_wr_en),
.d_in (phy_dout),
.wr_en_out (of_wren_pre),
.d_out (pre_fifo_dout),
.afull (pre_fifo_a_full)
);
end
else begin
// wire direct to ofifo
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
assign of_wren_pre = phy_wr_en;
end
endgenerate
///////////////////////////////////////////////////////////////////////////////
// Synchronize pi_phase_locked to phy_clk domain
///////////////////////////////////////////////////////////////////////////////
wire pi_phase_locked_w;
wire pi_dqs_found_w;
wire [5:0] pi_counter_read_val_w;
generate
if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_clk
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r1;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r2;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_r3;
reg pi_phase_locked_r4;
(* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r1;
(* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r2;
(* ASYNC_REG = "TRUE" *) reg pi_dqs_found_r3;
reg pi_dqs_found_r4;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r1;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r2;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_counter_read_val_r3;
reg [5:0] pi_counter_read_val_r4;
always @ (posedge phy_clk) begin
pi_phase_locked_r1 <= pi_phase_locked_w;
pi_phase_locked_r2 <= pi_phase_locked_r1;
pi_phase_locked_r3 <= pi_phase_locked_r2;
pi_dqs_found_r1 <= pi_dqs_found_w;
pi_dqs_found_r2 <= pi_dqs_found_r1;
pi_dqs_found_r3 <= pi_dqs_found_r2;
pi_counter_read_val_r1 <= pi_counter_read_val_w;
pi_counter_read_val_r2 <= pi_counter_read_val_r1;
pi_counter_read_val_r3 <= pi_counter_read_val_r2;
end
always @ (posedge phy_clk) begin
if (rst)
pi_phase_locked_r4 <= 1'b0;
else if (pi_phase_locked_r2 == pi_phase_locked_r3)
pi_phase_locked_r4 <= pi_phase_locked_r3;
end
always @ (posedge phy_clk) begin
if (rst)
pi_dqs_found_r4 <= 1'b0;
else if (pi_dqs_found_r2 == pi_dqs_found_r3)
pi_dqs_found_r4 <= pi_dqs_found_r3;
end
always @ (posedge phy_clk) begin
if (rst)
pi_counter_read_val_r4 <= 1'b0;
else if (pi_counter_read_val_r2 == pi_counter_read_val_r3)
pi_counter_read_val_r4 <= pi_counter_read_val_r3;
end
assign pi_phase_locked = pi_phase_locked_r4;
assign pi_dqs_found = pi_dqs_found_r4;
assign pi_counter_read_val = pi_counter_read_val_r4;
end else begin: pahser_in_div4_clk
assign pi_phase_locked = pi_phase_locked_w;
assign pi_dqs_found = pi_dqs_found_w;
assign pi_counter_read_val = pi_counter_read_val_w;
end
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" || ((RCLK_SELECT_LANE==ABCD) && (CKE_ODT_AUX =="TRUE"))) begin : phaser_in_gen
//if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2_sys_clk
if (PI_DIV2_INCDEC == "TRUE") begin
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found_w),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked_w),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val_w),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst_pi_div2),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (clk_div2)
);
end
else begin
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.DQS_AUTO_RECAL ( DQS_AUTO_RECAL),
.DQS_FIND_PATTERN ( DQS_FIND_PATTERN),
.SEL_CLK_OFFSET ( PI_SEL_CLK_OFFSET),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( L_PHASE_REF_PERIOD_NS)
) phaser_in (
.DQSFOUND (pi_dqs_found_w),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked_w),
.ISERDESRST (pi_iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val_w),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
end
else begin
assign pi_dqs_found_w = 1'b1;
// assign pi_dqs_out_of_range = 1'b0;
assign pi_phase_locked_w = 1'b1;
end
endgenerate
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
PHASER_OUT_PHY #(
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_BYPASS ( PO_COARSE_BYPASS ),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.PHASEREFCLK_PERIOD ( 1), // dummy, not used
.PO ( PO_DCD_SETTING ),
.MEMREFCLK_PERIOD ( L_MEM_REF_PERIOD_NS)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (po_oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
generate
if (PO_DATA_CTL == "TRUE") begin : in_fifo_gen
IN_FIFO #(
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (if_d0),
.D1 (if_d1),
.D2 (if_d2),
.D3 (if_d3),
.D4 (if_d4),
.D5 ({dummy_i5,if_d5}),
.D6 ({dummy_i6,if_d6}),
.D7 (if_d7),
.D8 (if_d8),
.D9 (if_d9),
.RDCLK (phy_clk),
.RDEN (phy_rd_en_),
.RESET (ififo_rst),
.WRCLK (iserdes_clkdiv),
.WREN (ififo_wr_enable)
);
end
endgenerate
OUT_FIFO #(
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (ofifo_rst),
.WRCLK (phy_clk),
.WREN (of_wren_pre)
);
mig_7series_v4_2_ddr_byte_group_io #
(
.PO_DATA_CTL (PO_DATA_CTL),
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (L_OSERDES_DATA_RATE),
.OSERDES_DATA_WIDTH (L_OSERDES_DATA_WIDTH),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.TCK (TCK),
.SYNTHESIS (SYNTHESIS)
)
ddr_byte_group_io
(
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (po_oserdes_rst),
.iserdes_rst (pi_iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.idelayctrl_refclk (idelayctrl_refclk),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]}),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
genvar i;
generate
for (i = 0; i <= 5; i = i+1) begin : ddr_ck_gen_loop
if (PO_DATA_CTL== "FALSE" && (BYTELANES_DDR_CK[i*4+PHASER_INDEX])) begin : ddr_ck_gen
ODDR #(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
ddr_ck (
.C (oserdes_clk),
.R (1'b0),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q[i])
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q[i]), .O(ddr_ck_out[i*2]), .OB(ddr_ck_out[i*2+1]));
end // ddr_ck_gen
else begin : ddr_ck_null
assign ddr_ck_out[i*2+1:i*2] = 2'b0;
end
end // ddr_ck_gen_loop
endgenerate
endmodule // byte_lane
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
**$Date: 2011/06/02 08:35:06 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter tCK = 2500, // DDR3 SDRAM clock period
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter TEST_AL = "0", // Additive Latency for internal use
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter tREFI = 7800000, // pS Refresh-to-Refresh delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter WRLVL = "OFF", // Enable write leveling
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter POC_USE_METASTABLE_SAMP = "FALSE",
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter CKE_ODT_AUX = "FALSE",
parameter IDELAY_ADJ = "ON",
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON",
parameter TAPSPERKCLK = 56,
parameter DEBUG_PORT = "OFF", // Enable debug port
parameter SKIP_CALIB = "FALSE",
parameter PI_DIV2_INCDEC = "TRUE"
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [nCK_PER_CLK -1:0] calib_cke,
output [1:0] calib_odt,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset_0,
output [5:0] calib_data_offset_1,
output [5:0] calib_data_offset_2,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
output reg calib_in_common/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output phy_if_empty_def,
output reg phy_if_reset,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
input [5:0] pi_counter_read_val,
// To DQS Phaser_In
output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
output idelay_ld,
// To DQS Phaser_Out
output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
output po_counter_load_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
input [4:0] idelaye2_init_val,
input [5:0] oclkdelay_init_val,
input tg_err,
output rst_tg_mc,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output calib_writes,
(* max_fanout = 50 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
output init_wrcal_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
input pd_out,
// input mmcm_ps_clk, //phase shift clock
// input oclkdelay_fb_clk, //Write DQS feedback clk
//phase shift clock control
output psen,
output psincdec,
input psdone,
input poc_sample_pd,
// Ports to be used when SKIP_CALIB="TRUE"
output reg calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// Debug Port
output dbg_pi_phaselock_start,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
// Delay control
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top, // General PHY debug
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [1023:0] dbg_poc,
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output reg [DQS_CNT_WIDTH:0] byte_sel_cnt,
output [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
output fine_delay_sel
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK >= 2500) || (SKIP_CALIB == "TRUE")) ? "OFF" : "ON"; //DIV2 change
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
// the add,ctl & data phaser out fine delays will be adjusted.
// In DDR3 only the add/ctrl lane delays will be adjusted
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK >= 2500)) ? "LEFT" : "RIGHT"; // DIV2 change IO Bank used for Memory I/F: "LEFT", "RIGHT"
localparam FIXED_VICTIM = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE";
localparam VCCO_PAT_EN = 1; // Enable VCCO pattern during calibration
localparam VCCAUX_PAT_EN = 1; // Enable VCCAUX pattern during calibration
localparam ISI_PAT_EN = 1; // Enable VCCO pattern during calibration
//Per-bit deskew for higher freqency (>800Mhz)
//localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF";
//BYPASS
localparam BYPASS_COMPLEX_RDLVL = ((tCK > 2500) || (SKIP_CALIB == "TRUE")) ? "TRUE": "FALSE"; //"TRUE";
localparam BYPASS_COMPLEX_OCAL = "TRUE";
//localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE";
// 8*tREFI in ps is divided by the fabric clock period in ps
// 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times
localparam REFRESH_TIMER = (8*tREFI/(tCK*nCK_PER_CLK)) - 270;
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER);
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
//wire [2*8*nCK_PER_CLK-1:0] prbs_out;
wire [8*DQ_WIDTH-1:0] prbs_out;
wire [7:0] prbs_rise0;
wire [7:0] prbs_fall0;
wire [7:0] prbs_rise1;
wire [7:0] prbs_fall1;
wire [7:0] prbs_rise2;
wire [7:0] prbs_fall2;
wire [7:0] prbs_rise3;
wire [7:0] prbs_fall3;
//wire [2*8*nCK_PER_CLK-1:0] prbs_o;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
wire dqsfound_retry;
wire dqsfound_retry_done;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire rdlvl_assrt_common;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ck_addr_cmd_delay_done;
wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset_0;
wire [5:0] rd_data_offset_1;
wire [5:0] rd_data_offset_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
wire cmd_po_stg2_f_incdec;
wire cmd_po_stg2_incdec_ddr2_c;
wire cmd_po_en_stg2_f;
wire cmd_po_en_stg2_ddr2_c;
wire cmd_po_stg2_c_incdec;
wire cmd_po_en_stg2_c;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [N_CTL_LANES-1:0] ctl_lane_sel;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
wire pi_fine_dly_dec_done;
wire rdlvl_pi_stg2_f_incdec;
wire rdlvl_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
//reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire phy_ctl_rdy_dly;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
reg po_dly_req_r;
wire wrcal_read_req;
wire wrcal_act_req;
wire temp_wrcal_done;
wire tg_timer_done;
wire no_rst_tg_mc;
wire calib_complete;
reg reset_if_r1;
reg reset_if_r2;
reg reset_if_r3;
reg reset_if_r4;
reg reset_if_r5;
reg reset_if_r6;
reg reset_if_r7;
reg reset_if_r8;
reg reset_if_r9;
reg reset_if;
wire phy_if_reset_w;
wire pi_phaselock_start;
reg dbg_pi_f_inc_r;
reg dbg_pi_f_en_r;
reg dbg_sel_pi_incdec_r;
reg dbg_po_f_inc_r;
reg dbg_po_f_stg23_sel_r;
reg dbg_po_f_en_r;
reg dbg_sel_po_incdec_r;
reg tempmon_pi_f_inc_r;
reg tempmon_pi_f_en_r;
reg tempmon_sel_pi_incdec_r;
reg ck_addr_cmd_delay_done_r1;
reg ck_addr_cmd_delay_done_r2;
reg ck_addr_cmd_delay_done_r3;
reg ck_addr_cmd_delay_done_r4;
reg ck_addr_cmd_delay_done_r5;
reg ck_addr_cmd_delay_done_r6;
// wire oclk_init_delay_start;
wire oclk_prech_req;
wire oclk_calib_resume;
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt;
wire oclkdelay_calib_start;
wire oclkdelay_calib_done;
wire complex_oclk_prech_req;
wire complex_oclk_calib_resume;
wire complex_oclkdelay_calib_start;
wire complex_oclkdelay_calib_done;
wire complex_ocal_num_samples_inc;
wire complex_ocal_num_samples_done_r;
wire [2:0] complex_ocal_rd_victim_sel;
wire complex_ocal_ref_req;
wire complex_ocal_ref_done;
wire [6*DQS_WIDTH-1:0] oclkdelay_left_edge_val;
wire [6*DQS_WIDTH-1:0] oclkdelay_right_edge_val;
wire wrlvl_final;
wire complex_wrlvl_final;
reg wrlvl_final_mux;
wire wrlvl_final_if_rst;
wire wrlvl_byte_redo;
wire wrlvl_byte_done;
wire early1_data;
wire early2_data;
wire po_stg23_sel;
wire po_stg23_incdec;
wire po_en_stg23;
wire complex_po_stg23_sel;
wire complex_po_stg23_incdec;
wire complex_po_en_stg23;
wire mpr_rdlvl_done;
wire mpr_rdlvl_start;
wire mpr_last_byte_done;
wire mpr_rnk_done;
wire mpr_end_if_reset;
wire mpr_rdlvl_err;
wire rdlvl_err;
wire prbs_rdlvl_start;
wire prbs_rdlvl_done;
wire prbs_rdlvl_done_complex;
reg prbs_rdlvl_done_r1;
wire prbs_last_byte_done;
wire prbs_rdlvl_prech_req;
wire prbs_pi_stg2_f_incdec;
wire prbs_pi_stg2_f_en;
wire complex_sample_cnt_inc;
wire complex_sample_cnt_inc_ocal;
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
wire prbs_gen_clk_en;
wire prbs_gen_oclk_clk_en;
wire rd_data_offset_cal_done;
wire fine_adjust_done;
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
wire ck_po_stg2_f_indec;
wire ck_po_stg2_f_en;
wire dqs_found_prech_req;
wire tempmon_pi_f_inc;
wire tempmon_pi_f_dec;
wire tempmon_sel_pi_incdec;
wire wrcal_sanity_chk;
wire wrcal_sanity_chk_done;
wire wrlvl_done_w;
wire wrlvl_rank_done;
wire done_dqs_tap_inc;
wire [2:0] rd_victim_sel;
wire [2:0] victim_sel;
wire [DQS_CNT_WIDTH:0] victim_byte_cnt;
wire complex_wr_done;
wire complex_victim_inc;
wire reset_rd_addr;
wire complex_ocal_reset_rd_addr;
wire oclkdelay_center_calib_start;
wire poc_error;
wire prbs_ignore_first_byte;
wire prbs_ignore_last_bytes;
//stg3 tap values
// wire [6*DQS_WIDTH-1:0] oclkdelay_center_val;
//byte selection
// wire [DQS_CNT_WIDTH:0] oclkdelay_center_cnt;
//INC/DEC for stg3 taps
// wire ocal_ctr_po_stg23_sel;
// wire ocal_ctr_po_stg23_incdec;
// wire ocal_ctr_po_en_stg23;
//Write resume for DQS toggling
wire oclk_center_write_resume;
wire oclkdelay_center_calib_done;
//Write request to toggle DQS for limit module
wire lim2init_write_request;
wire lim_done;
// Bypass complex ocal
wire complex_oclkdelay_calib_start_w;
wire complex_oclkdelay_calib_done_w;
wire [2:0] complex_ocal_rd_victim_sel_w;
wire complex_wrlvl_final_w;
wire [255:0] dbg_ocd_lim;
//with MMCM phase detect logic
//wire mmcm_edge_detect_rdy; // ready for MMCM detect
//wire ktap_at_rightedge; // stg3 tap at right edge
//wire ktap_at_leftedge; // stg3 tap at left edge
//wire mmcm_tap_at_center; // indicate stg3 tap at center
//wire mmcm_ps_clkphase_ok; // ps clkphase is OK
//wire mmcm_edge_detect_done; // mmcm edge detect is done
//wire mmcm_lbclk_edges_aligned; // mmcm edge detect is done
//wire reset_mmcm; //mmcm detect logic reset per byte
// wire [255:0] dbg_phy_oclkdelay_center_cal;
//PI inc/dec prevention during READ
wire rdlvl_pi_incdec;
wire complex_act_start;
wire complex_pi_incdec_done;
wire num_samples_done_r;
wire complex_init_pi_dec_done;
wire calib_tap_inc_start;
wire calib_tap_inc_done;
wire calib_tap_end_if_reset;
wire [5:0] calib_tap_inc_byte_cnt;
wire calib_po_f_en;
wire calib_po_f_incdec;
wire calib_po_sel_stg2stg3;
wire calib_po_c_en;
wire calib_po_c_inc;
wire calib_pi_f_en;
wire calib_pi_f_incdec;
wire calib_idelay_ce;
wire calib_idelay_inc;
wire coarse_dec_err;
reg skip_cal_tempmon_samp_en;
wire tempmon_done_skip;
wire skip_cal_po_pi_dec_done;
reg [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt;
reg [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt;
reg [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt;
reg [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt;
reg [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt;
reg [11:0] calib_device_temp;
wire [127:0] dbg_skip_cal;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
// synthesis translate_off
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
// synthesis translate_on
//***************************************************************************
// Debug
//***************************************************************************
reg if_empty_reg;
reg pi_stg2_en_reg;
assign prbs_rdlvl_done = (SIM_CAL_OPTION == "FAST_CAL")? rdlvl_stg1_done : prbs_rdlvl_done_complex;
assign dbg_pi_phaselock_start = pi_phaselock_start;
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
assign dbg_wrcal_start = wrcal_start;
assign dbg_wrcal_done = wrcal_done;
// Unused for now - use these as needed to bring up lower level signals
//assign dbg_calib_top = dbg_ocd_lim;
assign dbg_calib_top[0] = pi_stg2_en_reg ;
assign dbg_calib_top[1] = if_empty_reg ;
assign dbg_calib_top[3] = coarse_dec_err;
assign dbg_calib_top[4] = calib_tap_inc_start;
assign dbg_calib_top[5] = calib_tap_inc_done;
assign dbg_calib_top[6+:63] = dbg_skip_cal;
always @ (posedge clk) begin
if_empty_reg <= #TCQ phy_if_empty;
pi_stg2_en_reg <= #TCQ pi_en_stg2_f;
end
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// Read Level debug observation ports
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
(po_ck_addr_cmd_delay_done
&& pi_fine_dly_dec_done) ;
generate
if((WRLVL == "ON") && (BYPASS_COMPLEX_OCAL=="FALSE")) begin: complex_oclk_calib
assign complex_oclkdelay_calib_start_w = complex_oclkdelay_calib_start;
assign complex_oclkdelay_calib_done_w = complex_oclkdelay_calib_done;
assign complex_ocal_rd_victim_sel_w = complex_ocal_rd_victim_sel;
assign complex_wrlvl_final_w = complex_wrlvl_final;
end else begin: bypass_complex_ocal
assign complex_oclkdelay_calib_start_w = 1'b0;
assign complex_oclkdelay_calib_done_w = prbs_rdlvl_done;
assign complex_ocal_rd_victim_sel_w = 'd0;
assign complex_wrlvl_final_w = 1'b0;
end
endgenerate
generate
genvar i;
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
assign po_sel_stg2stg3[i] = ((ck_addr_cmd_delay_done && ~oclkdelay_calib_done && mpr_rdlvl_done) ? po_stg23_sel :
(complex_oclkdelay_calib_start_w&&~complex_oclkdelay_calib_done_w? po_stg23_sel : 1'b0 )
// (~oclkdelay_center_calib_done? ocal_ctr_po_stg23_sel:1'b0))
) || calib_po_sel_stg2stg3 || dbg_po_f_stg23_sel_r;
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
cmd_po_stg2_incdec_ddr2_c ||
calib_po_c_inc ||
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
cmd_po_en_stg2_ddr2_c ||
calib_po_c_en ||
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
cmd_po_stg2_f_incdec ||
ck_po_stg2_f_indec ||
po_stg23_incdec ||
calib_po_f_incdec ||
// complex_po_stg23_incdec ||
// ocal_ctr_po_stg23_incdec ||
dbg_po_f_inc_r;
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
cmd_po_en_stg2_f ||
ck_po_stg2_f_en ||
po_en_stg23 ||
calib_po_f_en ||
// complex_po_en_stg23 ||
// ocal_ctr_po_en_stg23 ||
dbg_po_f_en_r;
end
endgenerate
assign pi_stg2_f_incdec = (calib_pi_f_incdec | dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
assign pi_en_stg2_f = (calib_pi_f_en | dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
assign idelay_ce = (idelay_ce_r2 | calib_idelay_ce);
assign idelay_inc = (idelay_inc_r2 | calib_idelay_inc);
assign po_counter_load_en = 1'b0;
assign complex_oclkdelay_calib_cnt = oclkdelay_calib_cnt;
assign complex_oclk_calib_resume = oclk_calib_resume;
assign complex_ocal_ref_req = oclk_prech_req;
// Added single stage flop to meet timing
always @(posedge clk) begin
if (SKIP_CALIB == "FALSE")
init_calib_complete <= calib_complete;
else
init_calib_complete <= tempmon_done_skip;
end
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
assign rst_tg_mc = 1'b0;
//Restart WRLVL after oclkdealy cal
always @ (posedge clk)
wrlvl_final_mux <= #TCQ complex_oclkdelay_calib_start_w? complex_wrlvl_final_w: wrlvl_final;
always @(posedge clk)
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
reset_if | wrlvl_final_if_rst | calib_tap_end_if_reset);
//***************************************************************************
// Phaser_IN inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_pi_f_inc_r <= #TCQ 1'b0;
dbg_pi_f_en_r <= #TCQ 1'b0;
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
end
end
//***************************************************************************
// Phaser_OUT inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_po_f_inc_r <= #TCQ 1'b0;
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
dbg_po_f_en_r <= #TCQ 1'b0;
dbg_sel_po_incdec_r <= #TCQ 1'b0;
end else begin
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
end
end
//***************************************************************************
// Phaser_IN inc dec control for temperature tracking
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
tempmon_pi_f_inc_r <= #TCQ 1'b0;
tempmon_pi_f_en_r <= #TCQ 1'b0;
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
end
end
//***************************************************************************
// OCLKDELAY calibration signals
//***************************************************************************
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
// and increment/decrement of Phaser_Out stage 3 delay
always @(posedge clk) begin
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
end
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
generate
if (SKIP_CALIB == "TRUE") begin: gen_byte_sel_skip_calib
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~skip_cal_po_pi_dec_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~calib_tap_inc_done) begin
byte_sel_cnt <= #TCQ calib_tap_inc_byte_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (tCK >= 2500) begin: gen_byte_sel_div2 // DIV2 change
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done) && (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else begin: gen_byte_sel_div1
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~complex_oclkdelay_calib_done_w && prbs_rdlvl_done) begin
byte_sel_cnt <= #TCQ complex_oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end
endgenerate
// verilint STARC-2.2.3.3 off
always @(posedge clk) begin
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done) || ~skip_cal_po_pi_dec_done) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if (~dqs_po_dec_done && (WRLVL != "ON"))
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
if(WRLVL =="ON") begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
calib_sel[5:3] <= #TCQ CTL_BANK;
if (|pi_rst_stg1_cal) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end else begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
end
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin // if (WRLVL =="ON")
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if(~ck_addr_cmd_delay_done)
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end // else: !if(WRLVL =="ON")
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
rdlvl_assrt_common) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (tempmon_sel_pi_incdec) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
if (~calib_in_common) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
end else
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end
end
// verilint STARC-2.2.3.3 on
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
reset_if_r1 <= #TCQ reset_if;
reset_if_r2 <= #TCQ reset_if_r1;
reset_if_r3 <= #TCQ reset_if_r2;
reset_if_r4 <= #TCQ reset_if_r3;
reset_if_r5 <= #TCQ reset_if_r4;
reset_if_r6 <= #TCQ reset_if_r5;
reset_if_r7 <= #TCQ reset_if_r6;
reset_if_r8 <= #TCQ reset_if_r7;
reset_if_r9 <= #TCQ reset_if_r8;
end
always @(posedge clk) begin
if (rst || reset_if_r9)
reset_if <= #TCQ 1'b0;
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
reset_if <= #TCQ 1'b1;
end
assign phy_if_empty_def = 1'b0;
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// Delay all Outputs using Phaser_Out fine taps
//***************************************************************************
assign init_wrcal_complete = 1'b0;
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
assign prbs_seed = 64'h9966aa559966aa55;
// A single PRBS generator
// writes 64-bits every 4to1 fabric clock cycle and
// write 32-bits every 2to1 fabric clock cycle
// used for complex read leveling and complex oclkdealy calib
mig_7series_v4_2_ddr_prbs_gen #
(
.TCQ (TCQ),
.PRBS_WIDTH (2*8*nCK_PER_CLK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.VCCO_PAT_EN (VCCO_PAT_EN),
.VCCAUX_PAT_EN (VCCAUX_PAT_EN),
.ISI_PAT_EN (ISI_PAT_EN),
.FIXED_VICTIM (FIXED_VICTIM)
)
u_ddr_prbs_gen
(.prbs_ignore_first_byte (prbs_ignore_first_byte),
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
.clk_i (clk),
.clk_en_i (prbs_gen_clk_en | prbs_gen_oclk_clk_en),
.rst_i (rst),
.prbs_o (prbs_out),
.prbs_seed_i (prbs_seed),
.phy_if_empty (phy_if_empty),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.complex_wr_done (complex_wr_done),
.victim_sel (victim_sel),
.byte_cnt (victim_byte_cnt),
.dbg_prbs_gen (),
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr)
);
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
// Rise2, Fall2, Rise3, Fall3 data
generate
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbs_o = prbs_out;
/*assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_rise2 = prbs_out[39:32];
assign prbs_fall2 = prbs_out[47:40];
assign prbs_rise3 = prbs_out[55:48];
assign prbs_fall3 = prbs_out[63:56];
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
end else begin :gen_ck_per_clk2
assign prbs_o = prbs_out[4*DQ_WIDTH-1:0];
/*assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};*/
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
mig_7series_v4_2_ddr_phy_init #
(
.tCK (tCK),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.REFRESH_TIMER (REFRESH_TIMER),
.REFRESH_TIMER_WIDTH (REFRESH_TIMER_WIDTH),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PRE_REV3ES (PRE_REV3ES),
.TEST_AL (TEST_AL),
.FIXED_VICTIM (FIXED_VICTIM),
.BYPASS_COMPLEX_OCAL(BYPASS_COMPLEX_OCAL),
.SKIP_CALIB (SKIP_CALIB)
)
u_ddr_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
.delay_incdec_done (ck_addr_cmd_delay_done),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_phaselock_start (pi_phaselock_start),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.calib_cmd (calib_cmd),
.calib_cke (calib_cke),
.calib_odt (calib_odt),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_byte_done (wrlvl_byte_done),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_final (wrlvl_final_mux),
.wrlvl_final_if_rst (wrlvl_final_if_rst),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.lim_wr_req (lim2init_write_request),
.lim_done (lim_done),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done_w),
.complex_oclk_calib_resume (complex_oclk_calib_resume),
.complex_oclkdelay_calib_cnt (complex_oclkdelay_calib_cnt),
.complex_sample_cnt_inc_ocal (complex_sample_cnt_inc_ocal),
.complex_ocal_num_samples_inc (complex_ocal_num_samples_inc),
.complex_ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
.complex_ocal_reset_rd_addr (complex_ocal_reset_rd_addr),
.complex_ocal_ref_req (complex_ocal_ref_req),
.complex_ocal_ref_done (complex_ocal_ref_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.mpr_end_if_reset (mpr_end_if_reset),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prbs_rdlvl_start (prbs_rdlvl_start),
.complex_wr_done (complex_wr_done),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.complex_victim_inc (complex_victim_inc),
.rd_victim_sel (rd_victim_sel),
.complex_ocal_rd_victim_sel (complex_ocal_rd_victim_sel),
.pi_stg2_prbs_rdlvl_cnt(pi_stg2_prbs_rdlvl_cnt),
.victim_sel (victim_sel),
.victim_byte_cnt (victim_byte_cnt),
.prbs_gen_clk_en (prbs_gen_clk_en),
.prbs_gen_oclk_clk_en (prbs_gen_oclk_clk_en),
.complex_sample_cnt_inc(complex_sample_cnt_inc),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.wrcal_sanity_chk (wrcal_sanity_chk),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.tg_timer_done (tg_timer_done),
.no_rst_tg_mc (no_rst_tg_mc),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.calib_writes (calib_writes),
.init_calib_complete (calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid),
.dbg_phy_init (dbg_phy_init),
.reset_rd_addr (reset_rd_addr | complex_ocal_reset_rd_addr),
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
.oclk_center_write_resume (oclk_center_write_resume),
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
.rdlvl_pi_incdec (rdlvl_pi_incdec),
.complex_act_start (complex_act_start),
.complex_pi_incdec_done (complex_pi_incdec_done),
.complex_init_pi_dec_done (complex_init_pi_dec_done),
.num_samples_done_r (num_samples_done_r),
.calib_tap_inc_start (calib_tap_inc_start),
.calib_tap_end_if_reset (calib_tap_end_if_reset),
.calib_tap_inc_done (calib_tap_inc_done)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
mig_7series_v4_2_ddr_phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_sanity_chk (wrcal_sanity_chk),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.prech_done (prech_done),
.rd_data (phy_rddata),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.phy_if_reset (phy_if_reset_w),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_byte_done (wrlvl_byte_done),
.early1_data (early1_data),
.early2_data (early2_data),
.idelay_ld (idelay_ld),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if ((WRLVL == "ON") && (SKIP_CALIB == "FALSE")) begin: mb_wrlvl_inst
mig_7series_v4_2_ddr_phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrcal_cnt (po_stg2_wrcal_cnt),
.early1_data (early1_data),
.early2_data (early2_data),
.wrlvl_final (wrlvl_final_mux),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.wrlvl_byte_done (wrlvl_byte_done),
.oclkdelay_calib_done (oclkdelay_calib_done),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state (),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl)
);
mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else if ((WRLVL == "ON") && (SKIP_CALIB == "TRUE")) begin: wrlvl_on_skip_calib
mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (skip_cal_po_pi_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign dqs_po_dec_done = 1'b1;
assign wrlvl_byte_done = 1'b1;
assign wrlvl_rank_done = 1'b1;
assign phy_ctl_rdy_dly = 1'b1;
assign done_dqs_tap_inc = 1'b1;
assign po_stg2_wl_cnt = 'h0;
assign wl_po_coarse_cnt = 'h0;
assign wl_po_fine_cnt = 'h0;
assign dbg_tap_cnt_during_wrlvl = 'h0;
assign dbg_wl_edge_detect_valid = 'h0;
assign dbg_rd_data_edge_detect = 'h0;
assign dbg_wrlvl_fine_tap_cnt = 'h0;
assign dbg_wrlvl_coarse_tap_cnt = 'h0;
assign dbg_phy_wrlvl = 'h0;
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else begin: mb_wrlvl_off
mig_7series_v4_2_ddr_phy_wrlvl_off_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.PO_INITIAL_DLY(60),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.N_CTL_LANES (N_CTL_LANES)
)
u_phy_wrlvl_off_delay
(
.clk (clk),
.rst (rst),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.cmd_delay_start (phy_ctl_ready),
.ctl_lane_cnt (ctl_lane_cnt),
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
.po_en_s2_f (cmd_po_en_stg2_f),
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
.po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
);
assign wrlvl_byte_done = 1'b1;
assign wrlvl_rank_done = 1'b1;
assign po_stg2_wl_cnt = 'h0;
assign wl_po_coarse_cnt = 'h0;
assign wl_po_fine_cnt = 'h0;
assign dbg_tap_cnt_during_wrlvl = 'h0;
assign dbg_wl_edge_detect_valid = 'h0;
assign dbg_rd_data_edge_detect = 'h0;
assign dbg_wrlvl_fine_tap_cnt = 'h0;
assign dbg_wrlvl_coarse_tap_cnt = 'h0;
assign dbg_phy_wrlvl = 'h0;
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign cmd_po_stg2_c_incdec = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_en_stg2_c = 1'b0;
end
endgenerate
generate
if((WRLVL == "ON") && (OCAL_EN == "ON")) begin: oclk_calib
localparam SAMPCNTRWIDTH = 17;
localparam SAMPLES = (SIM_CAL_OPTION=="NONE") ? 512 : 4; //MG from 2048
localparam TAPCNTRWIDTH = clogb2(TAPSPERKCLK);
localparam MMCM_SAMP_WAIT = (SIM_CAL_OPTION=="NONE") ? 256 : 10;
localparam OCAL_SIMPLE_SCAN_SAMPS = (SIM_CAL_OPTION=="NONE") ? 512 : 1; //MG from 2048
localparam POC_PCT_SAMPS_SOLID = 80;
localparam SCAN_PCT_SAMPS_SOLID = 95;
mig_7series_v4_2_ddr_phy_oclkdelay_cal #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
//.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
//.OCAL_EN (OCAL_EN),
.OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),
.PCT_SAMPS_SOLID (POC_PCT_SAMPS_SOLID),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL)
//.tCK (tCK)
)
u_ddr_phy_oclkdelay_cal
(/*AUTOINST*/
// Outputs
.prbs_ignore_first_byte (prbs_ignore_first_byte),
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data[16*DRAM_WIDTH-1:0]),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal[255:0]),
.lim2init_write_request (lim2init_write_request),
.lim_done (lim_done),
.oclk_calib_resume (oclk_calib_resume),
.oclk_prech_req (oclk_prech_req),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.oclkdelay_calib_done (oclkdelay_calib_done),
.po_en_stg23 (po_en_stg23),
.po_stg23_incdec (po_stg23_incdec),
.po_stg23_sel (po_stg23_sel),
.psen (psen),
.psincdec (psincdec),
.wrlvl_final (wrlvl_final),
.rd_victim_sel (complex_ocal_rd_victim_sel),
.ocal_num_samples_done_r (complex_ocal_num_samples_done_r),
.complex_wrlvl_final (complex_wrlvl_final),
.poc_error (poc_error),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start_w),
.metaQ (pd_out),
//.oclk_init_delay_start (oclk_init_delay_start),
.po_counter_read_val (po_counter_read_val),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
.poc_sample_pd (poc_sample_pd),
.phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.phy_rddata_en (phy_rddata_en),
.prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.prech_done (prech_done),
.psdone (psdone),
.rst (rst),
.wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]),
.ocal_num_samples_inc (complex_ocal_num_samples_inc),
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
.oclk_center_write_resume (oclk_center_write_resume),
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
.dbg_ocd_lim (dbg_ocd_lim),
.dbg_poc (dbg_poc[1023:0]) );
end else begin : oclk_calib_disabled
assign wrlvl_final = 'b0;
assign psen = 'b0;
assign psincdec = 'b0;
assign po_stg23_sel = 'b0;
assign po_stg23_incdec = 'b0;
assign po_en_stg23 = 'b0;
assign oclkdelay_calib_cnt = 'b0;
assign oclk_prech_req = 'b0;
assign oclk_calib_resume = 'b0;
assign oclkdelay_calib_done = 1'b1;
assign dbg_phy_oclkdelay_cal = 'h0;
assign dbg_oclkdelay_rd_data = 'h0;
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
generate
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
mig_7series_v4_2_ddr_phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end else begin: dqsfind_calib_left
mig_7series_v4_2_ddr_phy_dqs_found_cal_hr #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal_hr
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end
endgenerate
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
generate
if (SKIP_CALIB == "FALSE") begin:ddr_phy_rdlvl_gen
mig_7series_v4_2_ddr_phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE),
.OCAL_EN (OCAL_EN),
.IDELAY_ADJ (IDELAY_ADJ),
.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_phy_rdlvl
(
.clk (clk),
.rst (rst),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.mpr_rdlvl_err (mpr_rdlvl_err),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.rdlvl_assrt_common (rdlvl_assrt_common),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.idelaye2_init_val (idelaye2_init_val),
.rd_data (phy_rddata),
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.dqs_po_dec_done (dqs_po_dec_done),
.pi_counter_read_val (pi_counter_read_val),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.idelay_ld (idelay_ld),
.wrcal_cnt (po_stg2_wrcal_cnt),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.rdlvl_pi_incdec (rdlvl_pi_incdec),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
end else begin:ddr_phy_rdlvl_off
assign mpr_rdlvl_done = 1'b1;
assign mpr_last_byte_done = 1'b1;
assign mpr_rnk_done = 1'b1;
assign rdlvl_stg1_done = 1'b1;
assign rdlvl_stg1_rank_done = 1'b1;
assign rdlvl_last_byte_done = 1'b1;
assign pi_fine_dly_dec_done = 1'b1;
assign rdlvl_prech_req = 1'b0;
assign rdlvl_stg1_err = 1'b0;
assign mpr_rdlvl_err = 1'b0;
assign rdlvl_err = 1'b0;
assign rdlvl_assrt_common = 1'b0;
assign rdlvl_pi_stg2_f_en = 1'b0;
assign rdlvl_pi_stg2_f_incdec = 1'b0;
assign pi_stg2_rdlvl_cnt = 'h0;
assign idelay_ce_int = 1'b0;
assign idelay_inc_int = 1'b0;
assign rdlvl_pi_incdec = 1'b0;
assign dbg_phy_rdlvl = 'h0;
assign dbg_cpt_first_edge_cnt = 'h0;
assign dbg_cpt_second_edge_cnt = 'h0;
assign dbg_cpt_tap_cnt = 'h0;
assign dbg_dq_idelay_tap_cnt = 'h0;
end
endgenerate
generate
if((DRAM_TYPE == "DDR3") && (nCK_PER_CLK == 4) && (BYPASS_COMPLEX_RDLVL=="FALSE")) begin:ddr_phy_prbs_rdlvl_gen
mig_7series_v4_2_ddr_phy_prbs_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.PRBS_WIDTH (PRBS_WIDTH),
.FIXED_VICTIM (FIXED_VICTIM),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ)
)
u_ddr_phy_prbs_rdlvl
(
.clk (clk),
.rst (rst),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done_complex),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.complex_sample_cnt_inc (complex_sample_cnt_inc),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.compare_data (prbs_o),
.pi_counter_read_val (pi_counter_read_val),
.pi_en_stg2_f (prbs_pi_stg2_f_en),
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt),
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.rd_victim_sel (rd_victim_sel),
.complex_victim_inc (complex_victim_inc),
.reset_rd_addr (reset_rd_addr),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel),
.complex_act_start (complex_act_start),
.num_samples_done_r (num_samples_done_r),
.complex_pi_incdec_done (complex_pi_incdec_done),
.complex_init_pi_dec_done (complex_init_pi_dec_done)
);
end else begin:ddr_phy_prbs_rdlvl_off
assign prbs_rdlvl_done_complex = rdlvl_stg1_done ;
//assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
assign prbs_last_byte_done = rdlvl_stg1_done;
assign reset_rd_addr = 1'b0;
assign prbs_rdlvl_prech_req = 1'b0 ;
assign prbs_pi_stg2_f_en = 1'b0 ;
assign prbs_pi_stg2_f_incdec = 1'b0 ;
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
assign dbg_prbs_rdlvl = 'h0 ;
assign prbs_final_dqs_tap_cnt_r = {(6*DQS_WIDTH*RANKS){1'b0}};
assign dbg_prbs_first_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
assign dbg_prbs_second_edge_taps = {(6*DQS_WIDTH*RANKS){1'b0}};
assign complex_pi_incdec_done = 'b0;
assign complex_init_pi_dec_done = 'b1;
assign num_samples_done_r = 'b0;
end
endgenerate
//***************************************************************************
// Inc/Dec Phaser_Out, Phaser_In, and IDELAY taps to match calibration values
//***************************************************************************
generate
if (SKIP_CALIB == "TRUE") begin: gen_skip_calib_tap
// Generate request to get calibration tap values per byte
always @(posedge clk) begin
if (rst)
calib_tap_req <= #TCQ 1'b0;
else if (phy_ctl_ready)
calib_tap_req <= #TCQ 1'b1;
end
// Store calibration values to registers
always @(posedge clk) begin
if (rst) begin
calib_po_coarse_tap_cnt <= #TCQ 'd0;
calib_po_stage3_tap_cnt <= #TCQ 'd0;
calib_po_stage2_tap_cnt <= #TCQ 'd0;
calib_pi_stage2_tap_cnt <= #TCQ 'd0;
calib_idelay_tap_cnt <= #TCQ 'd0;
calib_device_temp <= #TCQ 'd0;
end else if (calib_tap_load) begin
case (calib_tap_addr[2:0])
3'b000:
calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0];
3'b001:
calib_po_stage3_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];
3'b010:
calib_po_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];
3'b011:
calib_pi_stage2_tap_cnt[6*calib_tap_addr[6:3]+:6] <= #TCQ calib_tap_val[5:0];
3'b100:
calib_idelay_tap_cnt[5*calib_tap_addr[6:3]+:5] <= #TCQ calib_tap_val[4:0];
3'b110:
if (&calib_tap_addr[6:3])
calib_device_temp[7:0] <= #TCQ calib_tap_val[7:0];
3'b111:
if (&calib_tap_addr[6:3])
calib_device_temp[11:8] <= #TCQ calib_tap_val[3:0];
default:
calib_po_coarse_tap_cnt[3*calib_tap_addr[6:3]+:3] <= #TCQ calib_tap_val[2:0];
endcase
end
end
mig_7series_v4_2_ddr_skip_calib_tap #
(
.TCQ (TCQ),
.DQS_WIDTH (DQS_WIDTH)
)
u_ddr_skip_calib_tap
(
.rst (rst),
.clk (clk),
.phy_ctl_ready (phy_ctl_ready),
.load_done (calib_tap_load_done),
.calib_tap_inc_start (calib_tap_inc_start),
.calib_tap_inc_done (calib_tap_inc_done),
.calib_tap_inc_byte_cnt (calib_tap_inc_byte_cnt),
.calib_po_stage2_tap_cnt (calib_po_stage2_tap_cnt),
.calib_po_stage3_tap_cnt (calib_po_stage3_tap_cnt),
.calib_po_coarse_tap_cnt (calib_po_coarse_tap_cnt),
.calib_pi_stage2_tap_cnt (calib_pi_stage2_tap_cnt),
.calib_idelay_tap_cnt (calib_idelay_tap_cnt),
.po_counter_read_val (po_counter_read_val),
.pi_counter_read_val (pi_counter_read_val),
.calib_po_f_en (calib_po_f_en),
.calib_po_f_incdec (calib_po_f_incdec),
.calib_po_sel_stg2stg3 (calib_po_sel_stg2stg3),
.calib_po_c_en (calib_po_c_en),
.calib_po_c_inc (calib_po_c_inc),
.calib_pi_f_en (calib_pi_f_en),
.calib_pi_f_incdec (calib_pi_f_incdec),
.calib_idelay_ce (calib_idelay_ce),
.calib_idelay_inc (calib_idelay_inc),
.skip_cal_po_pi_dec_done (skip_cal_po_pi_dec_done),
.coarse_dec_err (coarse_dec_err),
.dbg_skip_cal (dbg_skip_cal)
);
// Generate tempmon_sample_en pulses for temperature adjustment
reg [8:0] samp_en_cnt;
always @ (posedge clk) begin
if (rst || tempmon_done_skip || (samp_en_cnt == 'd0))
samp_en_cnt <= #TCQ 'd267;
else if (calib_complete && (samp_en_cnt > 'd0))
samp_en_cnt <= #TCQ samp_en_cnt - 1;
end
always @ (posedge clk) begin
if (rst || tempmon_done_skip)
skip_cal_tempmon_samp_en <= #TCQ 1'b0;
else if (samp_en_cnt == 'd260)
skip_cal_tempmon_samp_en <= #TCQ 1'b1;
else
skip_cal_tempmon_samp_en <= #TCQ 1'b0;
end
end else begin: skip_calib_tap_off
assign calib_po_f_en = 1'b0;
assign calib_po_f_incdec = 1'b0;
assign calib_po_sel_stg2stg3 = 1'b0;
assign calib_po_c_en = 1'b0;
assign calib_po_c_inc = 1'b0;
assign calib_pi_f_en = 1'b0;
assign calib_pi_f_incdec = 1'b0;
assign calib_idelay_ce = 1'b0;
assign calib_idelay_inc = 1'b0;
assign calib_tap_inc_done = 1'b0;
assign calib_tap_inc_byte_cnt = 'd0;
assign skip_cal_po_pi_dec_done = 1'b1;
always @(posedge clk) begin
calib_tap_req <= #TCQ 1'b0;
calib_device_temp <= #TCQ 'd0;
skip_cal_tempmon_samp_en <= #TCQ 1'b0;
end
end
endgenerate
//***************************************************************************
// Temperature induced PI tap adjustment logic
//***************************************************************************
mig_7series_v4_2_ddr_phy_tempmon #
(
.SKIP_CALIB (SKIP_CALIB),
.TCQ (TCQ)
)
ddr_phy_tempmon_0
(
.rst (rst),
.clk (clk),
.calib_complete (calib_complete),
.tempmon_pi_f_inc (tempmon_pi_f_inc),
.tempmon_pi_f_dec (tempmon_pi_f_dec),
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
.device_temp (device_temp),
.calib_device_temp (calib_device_temp),
.tempmon_sample_en (tempmon_sample_en | skip_cal_tempmon_samp_en),
.tempmon_done_skip (tempmon_done_skip)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;
(* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
// Register duplication to reduce the fan out
(* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full[1]})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);
my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 5'b00000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_full[0] <= #TCQ 1'b0;
my_full[1] <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty[1], my_full[1]);
rd_ptr <= #TCQ 2'bxx;
rd_ptr_timing <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 5'b11111;
my_full <= #TCQ 2'b00;
rd_ptr <= #TCQ 'b0;
rd_ptr_timing <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem[rd_ptr_timing];
endmodule
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
,parameter PI_DIV2_INCDEC = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input clk_div2,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v4_2_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.clk_div2 (clk_div2),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v4_2_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.clk_div2 (clk_div2),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v4_2_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.clk_div2 (clk_div2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8,
parameter PI_DIV2_INCDEC = "FALSE"
)
(
input rst,
input iddr_rst,
input clk,
input clk_div2,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
//localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK >= 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";//DIV2 change
localparam PO_OCLKDELAY_INV = (tCK >= 2500) ? "FALSE" : "TRUE";//DIV2 change
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK >= 2500 ? "DIV2": "NONE";//DIV2 change
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ? // DIV2 change
((tCK >= 2500) ? 0 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
(tCK >= 2500) ? 0 : MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
wire iddr_rst_i;
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
assign iddr_rst_i = iddr_rst;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v4_2_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst_i),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v4_2_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst_i),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v4_2_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v4_2_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v4_2_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v4_2_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* KEEP = "TRUE", max_fanout = 50 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 50 *) wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module mig_7series_v4_2_ddr_phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter USE_PRE_POST_FIFO = "FALSE",
parameter RCLK_SELECT_LANE = "B",
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
parameter PI_SEL_CLK_OFFSET = 0,
// phy_control paramter used in other paramsters
parameter PC_CLK_RATIO = 4,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
,parameter CKE_ODT_AUX = "FALSE"
,parameter PI_DIV2_INCDEC = "FALSE"
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input clk_div2,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input phyGo,
input input_sink,
output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output byte_rd_en,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
input [1:0] byte_rd_en_oth_banks,
output [AUXOUT_WIDTH-1:0] aux_out,
output reg rst_out = 0,
output reg mcGo=0,
output phy_ctl_ready,
output ref_dll_lock,
input if_rst,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input [HIGHEST_LANE-1:0] calib_zero_lanes,
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_pi_rst_dqs_find;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg A_idelay_ld;
reg [29:0] A_fine_delay;
reg A_fine_delay_sel;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_pi_rst_dqs_find;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg B_idelay_ld;
reg [29:0] B_fine_delay;
reg B_fine_delay_sel;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
reg C_idelay_ld;
reg D_idelay_ld;
reg C_pi_rst_dqs_find;
reg D_pi_rst_dqs_find;
reg [29:0] C_fine_delay;
reg [29:0] D_fine_delay;
reg C_fine_delay_sel;
reg D_fine_delay_sel;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_byte_rd_en;
wire B_byte_rd_en;
wire C_byte_rd_en;
wire D_byte_rd_en;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
//wire A_if_full;
//wire B_if_full;
//wire C_if_full;
//wire D_if_full;
//wire A_of_empty;
//wire B_of_empty;
//wire C_of_empty;
//wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_pre_fifo_a_full;
wire B_pre_fifo_a_full;
wire C_pre_fifo_a_full;
wire D_pre_fifo_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire A_pre_data_a_full;
wire B_pre_data_a_full;
wire C_pre_data_a_full;
wire D_pre_data_a_full;
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
wire [3:0] dummy_data;
wire [31:0] _phy_ctl_wd;
wire [1:0] phy_encalib;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
// which is combined into another signals such that
// the other signal isn't changed. The purpose
// is to fake the tools into ignoring dangling inputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives=0;
reg A_rst_primitives=0;
reg B_rst_primitives=0;
reg C_rst_primitives=0;
reg D_rst_primitives=0;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
genvar i;
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
endgenerate
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
assign pi_phase_locked_lanes =
{(! PRESENT_DATA_D[0] | D_pi_phase_locked),
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
(! PRESENT_DATA_A[0] | A_pi_phase_locked)};
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
// this block scrubs X from rclk_delay[11]
reg rclk_delay_11;
always @(rclk_delay[11]) begin : rclk_delay_11_blk
if ( rclk_delay[11])
rclk_delay_11 = 1;
else
rclk_delay_11 = 0;
end
always @(posedge phy_clk or posedge rst ) begin
// scrub 4-state values from rclk_delay[11]
if ( rst) begin
rst_out <= #1 0;
end
else begin
if ( rclk_delay_11)
rst_out <= #1 1;
end
end
always @(posedge phy_clk ) begin
// phy_ctl_ready drives reset of the system
rst_primitives <= !phy_ctl_ready ;
A_rst_primitives <= rst_primitives ;
B_rst_primitives <= rst_primitives ;
C_rst_primitives <= rst_primitives ;
D_rst_primitives <= rst_primitives ;
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
mcGo <= #1 rst_out ;
end
//reset synchronized to clk_div2
(* ASYNC_REG = "TRUE" *) reg A_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg B_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg C_pi_rst_div2;
(* ASYNC_REG = "TRUE" *) reg D_pi_rst_div2;
generate
if (PI_DIV2_INCDEC == "TRUE") begin: phaser_in_div2
(* ASYNC_REG = "TRUE" *) reg pi_rst_div2r1;
(* ASYNC_REG = "TRUE" *) reg pi_rst_div2r2;
always @(posedge clk_div2) begin
pi_rst_div2r1 <= rst_primitives;
pi_rst_div2r2 <= pi_rst_div2r1;
A_pi_rst_div2 <= pi_rst_div2r2;
B_pi_rst_div2 <= pi_rst_div2r2;
C_pi_rst_div2 <= pi_rst_div2r2;
D_pi_rst_div2 <= pi_rst_div2r2;
end
end else begin: phaser_in_div4
always @ (*) begin
A_pi_rst_div2 <= 1'b0;
B_pi_rst_div2 <= 1'b0;
C_pi_rst_div2 <= 1'b0;
D_pi_rst_div2 <= 1'b0;
end
end
endgenerate
generate
if (BYTE_LANES[0]) begin
assign dummy_data[0] = 0;
end
else begin
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
end
if (BYTE_LANES[1]) begin
assign dummy_data[1] = 0;
end
else begin
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
end
if (BYTE_LANES[2]) begin
assign dummy_data[2] = 0;
end
else begin
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
end
if (BYTE_LANES[3]) begin
assign dummy_data[3] = 0;
end
else begin
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
end
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
assign A_pre_data_a_full = A_pre_fifo_a_full;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
assign A_pre_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
assign B_pre_data_a_full = B_pre_fifo_a_full;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
assign B_pre_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
assign C_pre_data_a_full = C_pre_fifo_a_full;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
assign C_pre_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
assign D_pre_data_a_full = D_pre_fifo_a_full;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
assign D_pre_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd = phy_ctl_wd;
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v4_2_ddr_byte_lane #
(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (A_rst_primitives),
.rst_pi_div2 (A_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*A_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*A_of_empty*/),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.pre_fifo_a_full (A_pre_fifo_a_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (A_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (A_idelay_ld),
.pi_rst_dqs_find (A_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked),
.fine_delay (A_fine_delay),
.fine_delay_sel (A_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_pre_fifo_a_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_byte_rd_en = 1'b1;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v4_2_ddr_byte_lane #
(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (B_rst_primitives),
.rst_pi_div2 (B_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*B_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*B_of_empty*/),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.pre_fifo_a_full (B_pre_fifo_a_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (B_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (B_idelay_ld),
.pi_rst_dqs_find (B_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked),
.fine_delay (B_fine_delay),
.fine_delay_sel (B_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_pre_fifo_a_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_byte_rd_en = 1'b1;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v4_2_ddr_byte_lane #
(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (C_rst_primitives),
.rst_pi_div2 (C_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*C_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*C_of_empty*/),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.pre_fifo_a_full (C_pre_fifo_a_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (C_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (C_idelay_ld),
.pi_rst_dqs_find (C_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked),
.fine_delay (C_fine_delay),
.fine_delay_sel (C_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_pre_fifo_a_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_byte_rd_en = 1'b1;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v4_2_ddr_byte_lane #
(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
,.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
ddr_byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (D_rst_primitives),
.rst_pi_div2 (D_pi_rst_div2),
.phy_clk (phy_clk),
.clk_div2 (clk_div2),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*D_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*D_of_empty*/),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.pre_fifo_a_full (D_pre_fifo_a_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (D_idelay_ld),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (D_byte_rd_en),
// calibration signals
.pi_rst_dqs_find (D_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked),
.fine_delay (D_fine_delay),
.fine_delay_sel (D_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_pre_fifo_a_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_byte_rd_en = 1'b1;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk ) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
wire B_mux_ctrl;
wire C_mux_ctrl;
wire D_mux_ctrl;
generate
if (HIGHEST_LANE > 1)
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
else
assign B_mux_ctrl = 0;
if (HIGHEST_LANE > 2)
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
else
assign C_mux_ctrl = 0;
if (HIGHEST_LANE > 3)
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
else
assign D_mux_ctrl = 0;
endgenerate
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
if ( B_mux_ctrl) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
if ( C_mux_ctrl) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
if ( D_mux_ctrl) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST ( ! pll_lock)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_dqs_found_cal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 3) || (HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_init.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has an interface for providing control/address and write
// data to the PHY Control Block during initialization/calibration.
// Once initialization and calibration are complete, control is passed to the MC.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_init.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_init.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_init #
(
parameter tCK = 1500, // DDRx SDRAM clock period
parameter TCQ = 100,
parameter nCK_PER_CLK = 4, // # of memory clocks per CLK
parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter DDR3_VDD_OP_VOLT = "150", // Voltage mode used for DDR3
// 150 - 1.50 V
// 135 - 1.35 V
// 125 - 1.25 V
parameter VREF = "EXTERNAL", // Internal or external Vref
parameter PRBS_WIDTH = 8, // PRBS sequence = 2^PRBS_WIDTH
parameter BANK_WIDTH = 2,
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10,
parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
// component I/F with CS_WIDTH=1,
// nCS_PER_RANK=# of components
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter ROW_WIDTH = 14,
parameter CS_WIDTH = 1,
parameter RANKS = 1, // # of memory ranks in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DRAM_TYPE = "DDR3",
parameter REG_CTRL = "ON",
parameter ADDR_CMD_MODE= "1T",
// calibration Address
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
// parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay (in ps)
parameter REFRESH_TIMER = 1553, // Refresh interval in fabrci cycles between 8 posted refreshes
parameter REFRESH_TIMER_WIDTH = 8,
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter RTT_NOM = "60", // Nominal ODT termination value
parameter RTT_WR = "60", // Write ODT termination value
parameter WRLVL = "ON", // Enable write leveling
// parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
parameter SIM_CAL_OPTION = "NONE", // "NONE", "FAST_CAL", "SKIP_CAL"
parameter CKE_ODT_AUX = "FALSE",
parameter PRE_REV3ES = "OFF", // Enable TG error detection during calibration
parameter TEST_AL = "0", // Internal use for ICM verification
parameter FIXED_VICTIM = "TRUE",
parameter BYPASS_COMPLEX_OCAL = "FALSE",
parameter SKIP_CALIB = "FALSE"
)
(
input clk,
input rst,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o,
input delay_incdec_done,
input ck_addr_cmd_delay_done,
input pi_phase_locked_all,
input pi_dqs_found_done,
input dqsfound_retry,
input dqs_found_prech_req,
output reg pi_phaselock_start,
output pi_phase_locked_err,
output pi_calib_done,
input phy_if_empty,
// Read/write calibration interface
input wrlvl_done,
input wrlvl_rank_done,
input wrlvl_byte_done,
input wrlvl_byte_redo,
input wrlvl_final,
output reg wrlvl_final_if_rst,
input oclkdelay_calib_done,
input oclk_prech_req,
input oclk_calib_resume,
input lim_done,
input lim_wr_req,
output reg oclkdelay_calib_start,
//complex oclkdelay calibration
input complex_oclkdelay_calib_done,
input complex_oclk_prech_req,
input complex_oclk_calib_resume,
output reg complex_oclkdelay_calib_start,
input [DQS_CNT_WIDTH:0] complex_oclkdelay_calib_cnt, // same as oclkdelay_calib_cnt
output reg complex_ocal_num_samples_inc,
input complex_ocal_num_samples_done_r,
input [2:0] complex_ocal_rd_victim_sel,
output reg complex_ocal_reset_rd_addr,
input complex_ocal_ref_req,
output reg complex_ocal_ref_done,
input done_dqs_tap_inc,
input [5:0] rd_data_offset_0,
input [5:0] rd_data_offset_1,
input [5:0] rd_data_offset_2,
input [6*RANKS-1:0] rd_data_offset_ranks_0,
input [6*RANKS-1:0] rd_data_offset_ranks_1,
input [6*RANKS-1:0] rd_data_offset_ranks_2,
input pi_dqs_found_rank_done,
input wrcal_done,
input wrcal_prech_req,
input wrcal_read_req,
input wrcal_act_req,
input temp_wrcal_done,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
output reg wl_sm_start,
output reg wr_lvl_start,
output reg wrcal_start,
output reg wrcal_rd_wait,
output reg wrcal_sanity_chk,
output reg tg_timer_done,
output reg no_rst_tg_mc,
input rdlvl_stg1_done,
input rdlvl_stg1_rank_done,
output reg rdlvl_stg1_start,
output reg pi_dqs_found_start,
output reg detect_pi_found_dqs,
// rdlvl stage 1 precharge requested after each DQS
input rdlvl_prech_req,
input rdlvl_last_byte_done,
input wrcal_resume,
input wrcal_sanity_chk_done,
// MPR read leveling
input mpr_rdlvl_done,
input mpr_rnk_done,
input mpr_last_byte_done,
output reg mpr_rdlvl_start,
output reg mpr_end_if_reset,
// PRBS Read Leveling
input prbs_rdlvl_done,
input prbs_last_byte_done,
input prbs_rdlvl_prech_req,
input complex_victim_inc,
input [2:0] rd_victim_sel,
input [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,
output reg [2:0] victim_sel,
output reg [DQS_CNT_WIDTH:0]victim_byte_cnt,
output reg prbs_rdlvl_start,
output reg prbs_gen_clk_en,
output reg prbs_gen_oclk_clk_en,
output reg complex_sample_cnt_inc,
output reg complex_sample_cnt_inc_ocal,
output reg complex_wr_done,
// Signals shared btw multiple calibration stages
output reg prech_done,
// Data select / status
output reg init_calib_complete,
// Signal to mask memory model error for Invalid latching edge
output reg calib_writes,
// PHY address/control
// 2 commands to PHY Control Block per div 2 clock in 2:1 mode
// 4 commands to PHY Control Block per div 4 clock in 4:1 mode
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output reg [nCK_PER_CLK-1:0] phy_ras_n,
output reg [nCK_PER_CLK-1:0] phy_cas_n,
output reg [nCK_PER_CLK-1:0] phy_we_n,
output reg phy_reset_n,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
// Hard PHY Interface signals
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
output reg calib_ctl_wren,
output reg calib_cmd_wren,
output reg [1:0] calib_seq,
output reg write_calib,
output reg read_calib,
// PHY_Ctl_Wd
output reg [2:0] calib_cmd,
// calib_aux_out used for CKE and ODT
output reg [3:0] calib_aux_out,
output reg [1:0] calib_odt ,
output reg [nCK_PER_CLK-1:0] calib_cke ,
output [1:0] calib_rank_cnt,
output reg [1:0] calib_cas_slot,
output reg [5:0] calib_data_offset_0,
output reg [5:0] calib_data_offset_1,
output reg [5:0] calib_data_offset_2,
// PHY OUT_FIFO
output reg calib_wrdata_en,
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,
// PHY Read
output phy_rddata_en,
output phy_rddata_valid,
output [255:0] dbg_phy_init,
input reset_rd_addr,
//OCAL centering calibration
input oclkdelay_center_calib_start,
input oclk_center_write_resume,
input oclkdelay_center_calib_done,
input rdlvl_pi_incdec, //rdlvl pi dec
input complex_pi_incdec_done,
input num_samples_done_r,
input complex_init_pi_dec_done,
output reg complex_act_start,
output reg calib_tap_inc_start,
output reg calib_tap_end_if_reset,
input calib_tap_inc_done
);
//*****************************************************************************
// Assertions to be added
//*****************************************************************************
// The phy_ctl_full signal must never be asserted in synchronous mode of
// operation either 4:1 or 2:1
//
// The RANKS parameter must never be set to '0' by the user
// valid values: 1 to 4
//
//*****************************************************************************
//***************************************************************************
// Number of Read level stage 1 writes limited to a SDRAM row
// The address of Read Level stage 1 reads must also be limited
// to a single SDRAM row
// (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128
localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 4 :
(BURST_MODE == "4") ? 8 : 4;
localparam ADDR_INC = (BURST_MODE == "8") ? 8 :
(BURST_MODE == "4") ? 4 : 8;
// In a 2 slot dual rank per system RTT_NOM values
// for Rank2 and Rank3 default to 40 ohms
localparam RTT_NOM2 = "40";
localparam RTT_NOM3 = "40";
localparam RTT_NOM_int = (USE_ODT_PORT == 1) ? RTT_NOM : RTT_WR;
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
// often row command needs to be issued during read-leveling
// For DDR3 the burst length is fixed during calibration
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
(BURST_MODE == "8") ? 1'b0 :
((BURST_MODE == "4") ? 1'b1 : 1'b0);
//***************************************************************************
// Counter values used to determine bus timing
// NOTE on all counter terminal counts - these can/should be one less than
// the actual delay to take into account extra clock cycle delay in
// generating the corresponding "done" signal
//***************************************************************************
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
// Calculate initial delay required in number of CLK clock cycles
// to delay initially. The counter is clocked by [CLK/1024] - which
// is approximately division by 1000 - note that the formulas below will
// result in more than the minimum wait time because of this approximation.
// NOTE: For DDR3 JEDEC specifies to delay reset
// by 200us, and CKE by an additional 500us after power-up
// For DDR2 CKE is delayed by 200us after power up.
localparam DDR3_RESET_DELAY_NS = 200000;
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
localparam DDR2_CKE_DELAY_NS = 200000;
localparam PWRON_RESET_DELAY_CNT =
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
// needs to be reworked.
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
localparam DDR2_INIT_PRE_CNT =
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
// cycles because this counter actually starts up before CKE is asserted
// to memory.
localparam TXPR_DELAY_CNT =
(5*CLK_MEM_PERIOD > tRFC+10000) ?
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
// TWR values in ns. Both DDR2 and DDR3 have the same value.
// 15000ns/tCK
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
// time to wait between consecutive commands in PHY_INIT - this is a
// generic number, and must be large enough to account for worst case
// timing parameter (tRFC - refresh-to-active) across all memory speed
// grades and operating frequencies. Expressed in clk
// (Divided by 4 or Divided by 2) clock cycles.
localparam CNTNEXT_CMD = 7'b1111111;
// Counter values to keep track of which MR register to load during init
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
// register configured during initialization.
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
localparam INIT_CNT_MR2 = 2'b00;
localparam INIT_CNT_MR3 = 2'b01;
localparam INIT_CNT_MR1 = 2'b10;
localparam INIT_CNT_MR0 = 2'b11;
localparam INIT_CNT_MR_DONE = 2'b11;
// Register chip programmable values for DDR3
// The register chip for the registered DIMM needs to be programmed
// before the initialization of the registered DIMM.
// Address for the control word is in : DBA2, DA2, DA1, DA0
// Data for the control word is in: DBA1 DBA0, DA4, DA3
// The values will be stored in the local param in the following format
// {DBA[2:0], DA[4:0]}
// RC0 is global features control word. Address == 000
localparam REG_RC0 = 8'b00000000;
// RC1 Clock driver enable control word. Enables or disables the four
// output clocks in the register chip. For single rank and dual rank
// two clocks will be enabled and for quad rank all the four clocks
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
// = 0000 for quad rank
localparam REG_RC1 = 8'b00000001;
// RC2 timing control word. Set in 1T timing mode
// Address = 010. Data = 0000
localparam REG_RC2 = 8'b00000010;
// RC3 timing control word. Setting the data based on number of RANKS (inturn the number of loads)
// This setting is specific to RDIMMs from Micron Technology
localparam REG_RC3 = (RANKS >= 2) ? 8'b00101011 : 8'b00000011;
// RC4 timing control work. Setting the data based on number of RANKS (inturn the number of loads)
// This setting is specific to RDIMMs from Micron Technology
localparam REG_RC4 = (RANKS >= 2) ? 8'b00101100 : 8'b00000100;
// RC5 timing control work. Setting the data based on number of RANKS (inturn the number of loads)
// This setting is specific to RDIMMs from Micron Technology
localparam REG_RC5 = (RANKS >= 2) ? 8'b00101101 : 8'b00000101;
// RC10 timing control work. Setting the data to 0000
localparam [3:0] FREQUENCY_ENCODING = (tCK >= 1072 && tCK < 1250) ? 4'b0100 :
(tCK >= 1250 && tCK < 1500) ? 4'b0011 :
(tCK >= 1500 && tCK < 1875) ? 4'b0010 :
(tCK >= 1875 && tCK < 2500) ? 4'b0001 : 4'b0000;
localparam REG_RC10 = {1'b1,FREQUENCY_ENCODING,3'b010};
localparam VREF_ENCODING = (VREF == "INTERNAL") ? 1'b1 : 1'b0;
localparam [3:0] DDR3_VOLTAGE_ENCODING = (DDR3_VDD_OP_VOLT == "125") ? {1'b0,VREF_ENCODING,2'b10} :
(DDR3_VDD_OP_VOLT == "135") ? {1'b0,VREF_ENCODING,2'b01} :
{1'b0,VREF_ENCODING,2'b00} ;
localparam REG_RC11 = {1'b1,DDR3_VOLTAGE_ENCODING,3'b011};
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Count value to generate pi_phase_locked_err signal
localparam PHASELOCKED_TIMEOUT = (SIM_CAL_OPTION == "NONE") ? 16383 : 1000;
// Timeout interval for detecting error with Traffic Generator
localparam [13:0] TG_TIMER_TIMEOUT
= (SIM_CAL_OPTION == "NONE") ? 14'h3FFF : 14'h0001;
//bit num per DQS
localparam DQ_PER_DQS = DQ_WIDTH/DQS_WIDTH;
//COMPLEX_ROW_CNT_BYTE
localparam COMPLEX_ROW_CNT_BYTE = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS*2: 2;
localparam COMPLEX_RD = (FIXED_VICTIM=="FALSE")? DQ_PER_DQS : 1;
// Master state machine encoding
localparam INIT_IDLE = 7'b0000000; //0
localparam INIT_WAIT_CKE_EXIT = 7'b0000001; //1
localparam INIT_LOAD_MR = 7'b0000010; //2
localparam INIT_LOAD_MR_WAIT = 7'b0000011; //3
localparam INIT_ZQCL = 7'b0000100; //4
localparam INIT_WAIT_DLLK_ZQINIT = 7'b0000101; //5
localparam INIT_WRLVL_START = 7'b0000110; //6
localparam INIT_WRLVL_WAIT = 7'b0000111; //7
localparam INIT_WRLVL_LOAD_MR = 7'b0001000; //8
localparam INIT_WRLVL_LOAD_MR_WAIT = 7'b0001001; //9
localparam INIT_WRLVL_LOAD_MR2 = 7'b0001010; //A
localparam INIT_WRLVL_LOAD_MR2_WAIT = 7'b0001011; //B
localparam INIT_RDLVL_ACT = 7'b0001100; //C
localparam INIT_RDLVL_ACT_WAIT = 7'b0001101; //D
localparam INIT_RDLVL_STG1_WRITE = 7'b0001110; //E
localparam INIT_RDLVL_STG1_WRITE_READ = 7'b0001111; //F
localparam INIT_RDLVL_STG1_READ = 7'b0010000; //10
localparam INIT_RDLVL_STG2_READ = 7'b0010001; //11
localparam INIT_RDLVL_STG2_READ_WAIT = 7'b0010010; //12
localparam INIT_PRECHARGE_PREWAIT = 7'b0010011; //13
localparam INIT_PRECHARGE = 7'b0010100; //14
localparam INIT_PRECHARGE_WAIT = 7'b0010101; //15
localparam INIT_DONE = 7'b0010110; //16
localparam INIT_DDR2_PRECHARGE = 7'b0010111; //17
localparam INIT_DDR2_PRECHARGE_WAIT = 7'b0011000; //18
localparam INIT_REFRESH = 7'b0011001; //19
localparam INIT_REFRESH_WAIT = 7'b0011010; //1A
localparam INIT_REG_WRITE = 7'b0011011; //1B
localparam INIT_REG_WRITE_WAIT = 7'b0011100; //1C
localparam INIT_DDR2_MULTI_RANK = 7'b0011101; //1D
localparam INIT_DDR2_MULTI_RANK_WAIT = 7'b0011110; //1E
localparam INIT_WRCAL_ACT = 7'b0011111; //1F
localparam INIT_WRCAL_ACT_WAIT = 7'b0100000; //20
localparam INIT_WRCAL_WRITE = 7'b0100001; //21
localparam INIT_WRCAL_WRITE_READ = 7'b0100010; //22
localparam INIT_WRCAL_READ = 7'b0100011; //23
localparam INIT_WRCAL_READ_WAIT = 7'b0100100; //24
localparam INIT_WRCAL_MULT_READS = 7'b0100101; //25
localparam INIT_PI_PHASELOCK_READS = 7'b0100110; //26
localparam INIT_MPR_RDEN = 7'b0100111; //27
localparam INIT_MPR_WAIT = 7'b0101000; //28
localparam INIT_MPR_READ = 7'b0101001; //29
localparam INIT_MPR_DISABLE_PREWAIT = 7'b0101010; //2A
localparam INIT_MPR_DISABLE = 7'b0101011; //2B
localparam INIT_MPR_DISABLE_WAIT = 7'b0101100; //2C
localparam INIT_OCLKDELAY_ACT = 7'b0101101; //2D
localparam INIT_OCLKDELAY_ACT_WAIT = 7'b0101110; //2E
localparam INIT_OCLKDELAY_WRITE = 7'b0101111; //2F
localparam INIT_OCLKDELAY_WRITE_WAIT = 7'b0110000; //30
localparam INIT_OCLKDELAY_READ = 7'b0110001; //31
localparam INIT_OCLKDELAY_READ_WAIT = 7'b0110010; //32
localparam INIT_REFRESH_RNK2_WAIT = 7'b0110011; //33
localparam INIT_RDLVL_COMPLEX_PRECHARGE = 7'b0110100; //34
localparam INIT_RDLVL_COMPLEX_PRECHARGE_WAIT = 7'b0110101; //35
localparam INIT_RDLVL_COMPLEX_ACT = 7'b0110110; //36
localparam INIT_RDLVL_COMPLEX_ACT_WAIT = 7'b0110111; //37
localparam INIT_RDLVL_COMPLEX_READ = 7'b0111000; //38
localparam INIT_RDLVL_COMPLEX_READ_WAIT = 7'b0111001; //39
localparam INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT = 7'b0111010; //3A
localparam INIT_OCAL_COMPLEX_ACT = 7'b0111011; //3B
localparam INIT_OCAL_COMPLEX_ACT_WAIT = 7'b0111100; //3C
localparam INIT_OCAL_COMPLEX_WRITE_WAIT = 7'b0111101; //3D
localparam INIT_OCAL_COMPLEX_RESUME_WAIT = 7'b0111110; //3E
localparam INIT_OCAL_CENTER_ACT = 7'b0111111; //3F
localparam INIT_OCAL_CENTER_WRITE = 7'b1000000; //40
localparam INIT_OCAL_CENTER_WRITE_WAIT = 7'b1000001; //41
localparam INIT_OCAL_CENTER_ACT_WAIT = 7'b1000010; //42
localparam INIT_RDLVL_COMPLEX_PI_WAIT = 7'b1000011; //43
localparam INIT_SKIP_CALIB_WAIT = 7'b1000100; //44
integer i, j, k, l, m, n, p, q;
reg pi_dqs_found_all_r;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r1;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r2;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r3;
(* ASYNC_REG = "TRUE" *) reg pi_phase_locked_all_r4;
reg pi_calib_rank_done_r;
reg [13:0] pi_phaselock_timer;
reg stg1_wr_done;
reg rnk_ref_cnt;
reg pi_dqs_found_done_r1;
reg pi_dqs_found_rank_done_r;
reg read_calib_int;
reg read_calib_r;
reg pi_calib_done_r;
reg pi_calib_done_r1;
reg burst_addr_r;
reg [1:0] chip_cnt_r;
reg [6:0] cnt_cmd_r;
reg cnt_cmd_done_r;
reg cnt_cmd_done_m7_r;
reg [7:0] cnt_dllk_zqinit_r;
reg cnt_dllk_zqinit_done_r;
reg cnt_init_af_done_r;
reg [1:0] cnt_init_af_r;
reg [1:0] cnt_init_data_r;
reg [1:0] cnt_init_mr_r;
reg cnt_init_mr_done_r;
reg cnt_init_pre_wait_done_r;
reg [7:0] cnt_init_pre_wait_r;
reg [9:0] cnt_pwron_ce_r;
reg cnt_pwron_cke_done_r;
reg cnt_pwron_cke_done_r1;
reg [8:0] cnt_pwron_r;
reg cnt_pwron_reset_done_r;
reg cnt_txpr_done_r;
reg [7:0] cnt_txpr_r;
reg ddr2_pre_flag_r;
reg ddr2_refresh_flag_r;
reg ddr3_lm_done_r;
reg [4:0] enable_wrlvl_cnt;
reg init_complete_r;
reg init_complete_r1;
reg init_complete_r2;
(* keep = "true" *) reg init_complete_r_timing;
(* keep = "true" *) reg init_complete_r1_timing;
reg [6:0] init_next_state;
reg [6:0] init_state_r;
reg [6:0] init_state_r1;
wire [15:0] load_mr0;
wire [15:0] load_mr1;
wire [15:0] load_mr2;
wire [15:0] load_mr3;
reg mem_init_done_r;
reg [1:0] mr2_r [0:3];
reg [2:0] mr1_r [0:3];
reg new_burst_r;
reg [15:0] wrcal_start_dly_r;
wire wrcal_start_pre;
reg wrcal_resume_r;
// Only one ODT signal per rank in PHY Control Block
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;
wire prech_done_pre;
reg [15:0] prech_done_dly_r;
reg prech_pending_r;
reg prech_req_posedge_r;
reg prech_req_r;
reg pwron_ce_r;
reg first_rdlvl_pat_r;
reg first_wrcal_pat_r;
reg phy_wrdata_en;
reg phy_wrdata_en_r1;
reg [1:0] wrdata_pat_cnt;
reg [1:0] wrcal_pat_cnt;
reg [ROW_WIDTH-1:0] address_w;
reg [BANK_WIDTH-1:0] bank_w;
reg rdlvl_stg1_done_r1;
reg rdlvl_stg1_start_int;
reg [15:0] rdlvl_start_dly0_r;
reg rdlvl_start_pre;
reg rdlvl_last_byte_done_r;
wire rdlvl_rd;
wire rdlvl_wr;
reg rdlvl_wr_r;
wire rdlvl_wr_rd;
reg [3:0] reg_ctrl_cnt_r;
reg [1:0] tmp_mr2_r [0:3];
reg [2:0] tmp_mr1_r [0:3];
reg wrlvl_done_r;
reg wrlvl_done_r1;
reg wrlvl_rank_done_r1;
reg wrlvl_rank_done_r2;
reg wrlvl_rank_done_r3;
reg wrlvl_rank_done_r4;
reg wrlvl_rank_done_r5;
reg wrlvl_rank_done_r6;
reg wrlvl_rank_done_r7;
reg [2:0] wrlvl_rank_cntr;
reg wrlvl_odt_ctl;
reg wrlvl_odt;
reg wrlvl_active;
reg wrlvl_active_r1;
reg [2:0] num_reads;
reg temp_wrcal_done_r;
reg temp_lmr_done;
reg extend_cal_pat;
reg [13:0] tg_timer;
reg tg_timer_go;
reg cnt_wrcal_rd;
reg [3:0] cnt_wait;
reg [7:0] wrcal_reads;
reg [8:0] stg1_wr_rd_cnt;
reg phy_data_full_r;
reg wr_level_dqs_asrt;
reg wr_level_dqs_asrt_r1;
reg [1:0] dqs_asrt_cnt;
reg [3:0] num_refresh;
wire oclkdelay_calib_start_pre;
reg [15:0] oclkdelay_start_dly_r;
reg [3:0] oclk_wr_cnt;
reg [3:0] wrcal_wr_cnt;
reg wrlvl_final_r;
reg prbs_rdlvl_done_r1;
reg prbs_rdlvl_done_r2;
reg prbs_rdlvl_done_r3;
reg prbs_last_byte_done_r;
reg phy_if_empty_r;
reg prbs_pat_resume_int;
reg complex_row0_wr_done;
reg complex_row1_wr_done;
reg complex_row0_rd_done;
reg complex_row1_rd_done;
reg complex_row0_rd_done_r1;
reg [3:0] complex_wait_cnt;
reg [3:0] complex_num_reads;
reg [3:0] complex_num_reads_dec;
reg [ROW_WIDTH-1:0] complex_address;
reg wr_victim_inc;
reg [2:0] wr_victim_sel;
reg [7:0] complex_row_cnt;
reg complex_sample_cnt_inc_r1;
reg complex_sample_cnt_inc_r2;
reg complex_odt_ext;
reg complex_ocal_odt_ext;
reg wrcal_final_chk;
wire prech_req;
reg reset_rd_addr_r1;
reg complex_rdlvl_int_ref_req;
reg ext_int_ref_req;
//complex OCLK delay calibration
reg [7:0] complex_row_cnt_ocal;
reg [4:0] complex_num_writes;
reg [4:0] complex_num_writes_dec;
reg complex_oclkdelay_calib_start_int;
reg complex_oclkdelay_calib_start_r1;
reg complex_oclkdelay_calib_start_r2;
reg complex_oclkdelay_calib_done_r1;
// reg [DQS_CNT_WIDTH:0] wr_byte_cnt_ocal;
reg [2:0] wr_victim_sel_ocal;
reg complex_row1_rd_done_r1; //time for switch to write
reg [2:0] complex_row1_rd_cnt; //row1 read number for the byte (8 (16 rows) row1)
reg complex_byte_rd_done; //read for the byte is done
reg complex_byte_rd_done_r1;
// reg complex_row_change; //every 16 rows of read, it is set to "0" for write
reg ocal_num_samples_inc; //1 read/write is done
reg complex_ocal_wr_start; //indicate complex ocal write is started. used for prbs rd addr gen
reg prbs_rdlvl_done_pulse; //rising edge for prbs_rdlvl_done. used for pipelining
reg prech_done_r1, prech_done_r2, prech_done_r3;
reg mask_lim_done;
reg complex_mask_lim_done;
reg oclkdelay_calib_start_int;
reg [REFRESH_TIMER_WIDTH-1:0] oclkdelay_ref_cnt;
reg oclkdelay_int_ref_req;
reg [3:0] ocal_act_wait_cnt;
reg oclk_calib_resume_level;
reg ocal_last_byte_done;
wire mmcm_wr; //MMCM centering write. no CS will be set
wire exit_ocal_complex_resume_wait =
init_state_r == INIT_OCAL_COMPLEX_RESUME_WAIT && complex_oclk_calib_resume;
reg calib_tap_inc_done_r1;
//***************************************************************************
// Debug
//***************************************************************************
//synthesis translate_off
always @(posedge mem_init_done_r) begin
if (!rst)
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
end
always @(posedge wrlvl_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Leveling completed at %t", $time);
end
always @(posedge rdlvl_stg1_done) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
end
always @(posedge mpr_rdlvl_done) begin
if (!rst)
$display ("PHY_INIT: MPR Read Leveling completed at %t", $time);
end
always @(posedge oclkdelay_calib_done) begin
if (!rst)
$display ("PHY_INIT: OCLKDELAY calibration completed at %t", $time);
end
always @(posedge pi_calib_done_r1) begin
if (!rst)
$display ("PHY_INIT: Phaser_In Phase Locked at %t", $time);
end
always @(posedge pi_dqs_found_done) begin
if (!rst)
$display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time);
end
always @(posedge wrcal_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Calibration completed at %t", $time);
end
always@(posedge prbs_rdlvl_done)begin
if(!rst)
$display("PHY_INIT : PRBS/PER_BIT calibration completed at %t",$time);
end
always@(posedge complex_oclkdelay_calib_done)begin
if(!rst)
$display("PHY_INIT : COMPLEX OCLKDELAY calibration completed at %t",$time);
end
always@(posedge oclkdelay_center_calib_done)begin
if(!rst)
$display("PHY_INIT : OCLKDELAY CENTER CALIB calibration completed at %t",$time);
end
//synthesis translate_on
assign dbg_phy_init[5:0] = init_state_r;
assign dbg_phy_init[6+:8] = complex_row_cnt;
assign dbg_phy_init[14+:3] = victim_sel;
assign dbg_phy_init[17+:4] = victim_byte_cnt;
assign dbg_phy_init[21+:9] = stg1_wr_rd_cnt[8:0];
assign dbg_phy_init[30+:15] = complex_address;
assign dbg_phy_init[(30+15)+:15] = phy_address[14:0];
assign dbg_phy_init[60] =prbs_rdlvl_prech_req ;
assign dbg_phy_init[61] =prech_req_posedge_r ;
//***************************************************************************
// DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage
//***************************************************************************
// assign pi_phaselock_calib_cnt = dqs_cnt_r;
assign pi_calib_done = pi_calib_done_r1;
//prevent PI incdec during complex read
always @ (posedge clk)
complex_act_start <= #TCQ (init_state_r == INIT_RDLVL_COMPLEX_ACT) || (init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT);
//detect rising edge of prbs_rdlvl_done to reset all control sighals
always @ (posedge clk) begin
prbs_rdlvl_done_pulse <= #TCQ prbs_rdlvl_done & ~prbs_rdlvl_done_r1;
end
always @(posedge clk) begin
if (rst)
wrcal_final_chk <= #TCQ 1'b0;
else if ((init_next_state == INIT_WRCAL_ACT) && (wrcal_done || (SKIP_CALIB == "TRUE")) &&
(DRAM_TYPE == "DDR3"))
wrcal_final_chk <= #TCQ 1'b1;
end
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
prbs_rdlvl_done_r2 <= #TCQ prbs_rdlvl_done_r1;
prbs_rdlvl_done_r3 <= #TCQ prbs_rdlvl_done_r2;
wrcal_resume_r <= #TCQ wrcal_resume;
wrcal_sanity_chk <= #TCQ wrcal_final_chk;
end
always @(posedge clk) begin
if (rst)
mpr_end_if_reset <= #TCQ 1'b0;
else if (mpr_last_byte_done && (num_refresh != 'd0))
mpr_end_if_reset <= #TCQ 1'b1;
else
mpr_end_if_reset <= #TCQ 1'b0;
end
// Siganl to mask memory model error for Invalid latching edge
always @(posedge clk)
if (rst)
calib_writes <= #TCQ 1'b0;
else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ))
calib_writes <= #TCQ 1'b1;
else
calib_writes <= #TCQ 1'b0;
always @(posedge clk)
if (rst)
wrcal_rd_wait <= #TCQ 1'b0;
else if (init_state_r == INIT_WRCAL_READ_WAIT)
wrcal_rd_wait <= #TCQ 1'b1;
else
wrcal_rd_wait <= #TCQ 1'b0;
//***************************************************************************
// Signal PHY completion when calibration is finished
// Signal assertion is delayed by four clock cycles to account for the
// multi cycle path constraint to (phy_init_data_sel) signal.
//***************************************************************************
always @(posedge clk)
if (rst) begin
init_complete_r <= #TCQ 1'b0;
init_complete_r_timing <= #TCQ 1'b0;
init_complete_r1 <= #TCQ 1'b0;
init_complete_r1_timing <= #TCQ 1'b0;
init_complete_r2 <= #TCQ 1'b0;
init_calib_complete <= #TCQ 1'b0;
end else begin
if (init_state_r == INIT_DONE) begin
init_complete_r <= #TCQ 1'b1;
init_complete_r_timing <= #TCQ 1'b1;
end
init_complete_r1 <= #TCQ init_complete_r;
init_complete_r1_timing <= #TCQ init_complete_r_timing;
init_complete_r2 <= #TCQ init_complete_r1;
init_calib_complete <= #TCQ init_complete_r2;
end
always @ (posedge clk)
if (rst)
complex_oclkdelay_calib_done_r1 <= #TCQ 1'b0;
else
complex_oclkdelay_calib_done_r1 <= #TCQ complex_oclkdelay_calib_done;
//reset read address for starting complex ocaldealy calib
always @ (posedge clk) begin
complex_ocal_reset_rd_addr <= #TCQ ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd9)) || (prbs_last_byte_done && ~prbs_last_byte_done_r);
end
//first write for complex oclkdealy calib
always @ (posedge clk) begin
if (rst)
complex_ocal_wr_start <= #TCQ 'b0;
else
complex_ocal_wr_start <= #TCQ complex_ocal_reset_rd_addr? 1'b1 : complex_ocal_wr_start;
end
//ocal stg3 centering start
// always @ (posedge clk)
// if(rst) oclkdelay_center_calib_start <= #TCQ 1'b0;
// else
// oclkdelay_center_calib_start <= #TCQ ((init_state_r == INIT_OCAL_CENTER_ACT) && lim_done)? 1'b1: oclkdelay_center_calib_start;
//***************************************************************************
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
// constraint will be assigned to this signal. This signal will only be
// used within the PHY
//***************************************************************************
// FDRSE u_ff_phy_init_data_sel
// (
// .Q (phy_init_data_sel),
// .C (clk),
// .CE (1'b1),
// .D (init_complete_r),
// .R (1'b0),
// .S (1'b0)
// ) /* synthesis syn_preserve=1 */
// /* synthesis syn_replicate = 0 */;
//***************************************************************************
// Mode register programming
//***************************************************************************
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
(BURST_MODE == "OTF") ? 2'b01 :
(BURST_MODE == "4") ? 2'b10 : 2'b11;
assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :
((nCL == 6) || (nCL == 14)) ? 3'b010 :
(nCL == 7) ? 3'b011 :
(nCL == 8) ? 3'b100 :
(nCL == 9) ? 3'b101 :
(nCL == 10) ? 3'b110 :
(nCL == 11) ? 3'b111 :
(nCL == 12) ? 3'b000 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
(TWR_CYC == 6) ? 3'b010 :
(TWR_CYC == 7) ? 3'b011 :
(TWR_CYC == 8) ? 3'b100 :
(TWR_CYC == 9) ? 3'b101 :
(TWR_CYC == 10) ? 3'b101 :
(TWR_CYC == 11) ? 3'b110 :
(TWR_CYC == 12) ? 3'b110 :
(TWR_CYC == 13) ? 3'b111 :
(TWR_CYC == 14) ? 3'b111 :
(TWR_CYC == 15) ? 3'b000 :
(TWR_CYC == 16) ? 3'b000 : 3'b010;
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
assign load_mr0[15:13] = 3'b000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
(BURST_MODE == "4") ? 3'b010 : 3'b111;
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
(nCL == 4) ? 3'b100 :
(nCL == 5) ? 3'b101 :
(nCL == 6) ? 3'b110 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
(TWR_CYC == 3) ? 3'b010 :
(TWR_CYC == 4) ? 3'b011 :
(TWR_CYC == 5) ? 3'b100 :
(TWR_CYC == 6) ? 3'b101 : 3'b010;
assign load_mr0[15:12]= 4'b0000; // Reserved
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
assign load_mr1[2] = ((RTT_NOM_int == "30") || (RTT_NOM_int == "40") ||
(RTT_NOM_int == "60")) ? 1'b1 : 1'b0;
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
(AL == "CL-1") ? 2'b01 :
(AL == "CL-2") ? 2'b10 : 2'b11;
assign load_mr1[5] = 1'b0;
assign load_mr1[6] = ((RTT_NOM_int == "40") || (RTT_NOM_int == "120")) ?
1'b1 : 1'b0;
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
assign load_mr1[8] = 1'b0;
assign load_mr1[9] = ((RTT_NOM_int == "20") || (RTT_NOM_int == "30")) ?
1'b1 : 1'b0;
assign load_mr1[10] = 1'b0;
assign load_mr1[15:11] = 5'b00000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
assign load_mr1[2] = ((RTT_NOM_int == "75") || (RTT_NOM_int == "50")) ?
1'b1 : 1'b0;
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
(AL == "1") ? 3'b001 :
(AL == "2") ? 3'b010 :
(AL == "3") ? 3'b011 :
(AL == "4") ? 3'b100 : 3'b111;
assign load_mr1[6] = ((RTT_NOM_int == "50") ||
(RTT_NOM_int == "150")) ? 1'b1 : 1'b0;
assign load_mr1[9:7] = 3'b000;
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
assign load_mr1[15:11] = 5'b00000;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
assign load_mr2[2:0] = 3'b000;
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
(nCWL == 6) ? 3'b001 :
(nCWL == 7) ? 3'b010 :
(nCWL == 8) ? 3'b011 :
(nCWL == 9) ? 3'b100 :
(nCWL == 10) ? 3'b101 :
(nCWL == 11) ? 3'b110 : 3'b111;
assign load_mr2[6] = 1'b0;
assign load_mr2[7] = 1'b0;
assign load_mr2[8] = 1'b0;
// Dynamic ODT disabled
assign load_mr2[10:9] = 2'b00;
assign load_mr2[15:11] = 5'b00000;
end else begin: gen_load_mr2_DDR2
assign load_mr2[15:0] = 16'd0;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
assign load_mr3[1:0] = 2'b00;
assign load_mr3[2] = 1'b0;
assign load_mr3[15:3] = 13'b0000000000000;
// For multi-rank systems the rank being accessed during writes in
// Read Leveling must be sent to phy_write for the bitslip logic
assign calib_rank_cnt = chip_cnt_r;
//***************************************************************************
// Logic to begin initial calibration, and to handle precharge requests
// during read-leveling (to avoid tRAS violations if individual read
// levelling calibration stages take more than max{tRAS) to complete).
//***************************************************************************
// Assert when readback for each stage of read-leveling begins. However,
// note this indicates only when the read command is issued and when
// Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not
// indicate when the read data is present on the bus (when this happens
// after the read command is issued depends on CAS LATENCY) - there will
// need to be some delay before valid data is present on the bus.
// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);
// Assert when read back for oclkdelay calibration begins
assign oclkdelay_calib_start_pre = (init_state_r == INIT_OCAL_CENTER_ACT); //(init_state_r == INIT_OCLKDELAY_READ);
// Assert when read back for write calibration begins
assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ) || (init_state_r == INIT_WRCAL_MULT_READS);
// Common precharge signal done signal - pulses only when there has been
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
// PRECH_DONE signal is used for all blocks
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
((rdlvl_last_byte_done_r || prbs_last_byte_done_r) && (init_state_r == INIT_RDLVL_ACT_WAIT) && cnt_cmd_done_r) ||
(dqs_found_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||
(init_state_r == INIT_MPR_RDEN) ||
((init_state_r == INIT_WRCAL_ACT_WAIT) && cnt_cmd_done_r) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && complex_oclkdelay_calib_start_r1) ||
((init_state_r == INIT_OCLKDELAY_ACT_WAIT) && cnt_cmd_done_r) ||
((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) && prbs_last_byte_done_r) || //prbs_rdlvl_done
(wrlvl_final && (init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r && ~oclkdelay_calib_done)) &&
prech_pending_r &&
!prech_req_posedge_r);
always @(posedge clk)
if (rst)
calib_tap_inc_start <= #TCQ 1'b0;
else if (init_state_r == INIT_SKIP_CALIB_WAIT)
calib_tap_inc_start <= #TCQ 1'b1;
always @(posedge clk)
calib_tap_inc_done_r1 <= #TCQ calib_tap_inc_done;
always @(posedge clk)
if (rst || (init_state_r == INIT_WRCAL_WRITE))
calib_tap_end_if_reset <= #TCQ 1'b0;
else if (calib_tap_inc_done && ~calib_tap_inc_done_r1)
calib_tap_end_if_reset <= #TCQ 1'b1;
always @(posedge clk)
if (rst)
pi_phaselock_start <= #TCQ 1'b0;
else if (init_state_r == INIT_PI_PHASELOCK_READS)
pi_phaselock_start <= #TCQ 1'b1;
// Delay start of each calibration by 16 clock cycles to ensure that when
// calibration logic begins, read data is already appearing on the bus.
// Each circuit should synthesize using an SRL16. Assume that reset is
// long enough to clear contents of SRL16.
always @(posedge clk) begin
rdlvl_last_byte_done_r <= #TCQ rdlvl_last_byte_done;
prbs_last_byte_done_r <= #TCQ prbs_last_byte_done;
rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
rdlvl_start_pre};
wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],
wrcal_start_pre};
oclkdelay_start_dly_r <= #TCQ {oclkdelay_start_dly_r[14:0],
oclkdelay_calib_start_pre};
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
prech_done_pre};
end
always @(posedge clk)
if (rst)
oclkdelay_calib_start_int <= #TCQ 1'b0;
else if (oclkdelay_start_dly_r[5])
oclkdelay_calib_start_int <= #TCQ 1'b1;
always @(posedge clk) begin
if (rst)
ocal_last_byte_done <= #TCQ 1'b0;
else if ((complex_oclkdelay_calib_cnt == DQS_WIDTH-1) && oclkdelay_center_calib_done)
ocal_last_byte_done <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || (init_state_r == INIT_REFRESH) || prbs_rdlvl_done || ocal_last_byte_done || oclkdelay_center_calib_done)
oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;
else if (oclkdelay_calib_start_int) begin
if (oclkdelay_ref_cnt > 'd0)
oclkdelay_ref_cnt <= #TCQ oclkdelay_ref_cnt - 1;
else
oclkdelay_ref_cnt <= #TCQ REFRESH_TIMER;
end
end
always @(posedge clk) begin
if (rst || (init_state_r == INIT_OCAL_CENTER_ACT) || oclkdelay_calib_done || ocal_last_byte_done || oclkdelay_center_calib_done)
oclkdelay_int_ref_req <= #TCQ 1'b0;
else if (oclkdelay_ref_cnt == 'd1)
oclkdelay_int_ref_req <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
ocal_act_wait_cnt <= #TCQ 'd0;
else if ((init_state_r == INIT_OCAL_CENTER_ACT_WAIT) && ocal_act_wait_cnt < 'd15)
ocal_act_wait_cnt <= #TCQ ocal_act_wait_cnt + 1;
else
ocal_act_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst || (init_state_r == INIT_OCLKDELAY_READ))
oclk_calib_resume_level <= #TCQ 1'b0;
else if (oclk_calib_resume)
oclk_calib_resume_level <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || (init_state_r == INIT_RDLVL_ACT_WAIT) || prbs_rdlvl_done)
complex_rdlvl_int_ref_req <= #TCQ 1'b0;
else if (oclkdelay_ref_cnt == 'd1)
// complex_rdlvl_int_ref_req <= #TCQ 1'b1;
complex_rdlvl_int_ref_req <= #TCQ 1'b0; //temporary fix for read issue
end
always @(posedge clk) begin
if (rst || (init_state_r == INIT_RDLVL_COMPLEX_READ))
ext_int_ref_req <= #TCQ 1'b0;
else if ((init_state_r == INIT_RDLVL_ACT_WAIT) && complex_rdlvl_int_ref_req)
ext_int_ref_req <= #TCQ 1'b1;
end
always @(posedge clk) begin
prech_done <= #TCQ prech_done_dly_r[15];
prech_done_r1 <= #TCQ prech_done_dly_r[15];
prech_done_r2 <= #TCQ prech_done_r1;
prech_done_r3 <= #TCQ prech_done_r2;
end
always @(posedge clk)
if (rst)
mpr_rdlvl_start <= #TCQ 1'b0;
else if (pi_dqs_found_done &&
(init_state_r == INIT_MPR_READ))
mpr_rdlvl_start <= #TCQ 1'b1;
always @(posedge clk)
phy_if_empty_r <= #TCQ phy_if_empty;
always @(posedge clk)
if (rst ||
((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || prbs_rdlvl_done)
prbs_gen_clk_en <= #TCQ 1'b0;
else if ((~phy_if_empty_r && rdlvl_stg1_done_r1 && ~prbs_rdlvl_done) ||
((init_state_r == INIT_RDLVL_ACT_WAIT) && rdlvl_stg1_done_r1 && (cnt_cmd_r == 'd127)) ||
((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && rdlvl_stg1_done_r1 && (complex_wait_cnt == 'd14))
|| (init_state_r == INIT_RDLVL_COMPLEX_READ) || ((init_state_r == INIT_PRECHARGE_PREWAIT) && prbs_rdlvl_start))
prbs_gen_clk_en <= #TCQ 1'b1;
//Enable for complex oclkdelay - used in prbs gen
always @(posedge clk)
if (rst ||
((stg1_wr_rd_cnt == 'd2) && ~stg1_wr_done) || complex_oclkdelay_calib_done ||
(complex_wait_cnt == 'd15 && complex_num_writes == 1 && complex_ocal_wr_start) ||
( init_state_r == INIT_RDLVL_STG1_WRITE && complex_num_writes_dec == 'd2) || ~complex_ocal_wr_start ||
(complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT ) ||
(init_state_r != INIT_OCAL_COMPLEX_RESUME_WAIT && init_state_r1 == INIT_OCAL_COMPLEX_RESUME_WAIT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT))
prbs_gen_oclk_clk_en <= #TCQ 1'b0;
else if ((~phy_if_empty_r && ~complex_oclkdelay_calib_done && prbs_rdlvl_done_r1) || // changed for new algo 3/26
((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && (complex_wait_cnt == 'd14)) ||
((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14)) ||
exit_ocal_complex_resume_wait ||
((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && ~stg1_wr_done && ~complex_row1_wr_done && ~complex_ocal_num_samples_done_r && (complex_wait_cnt == 'd14))
|| (init_state_r == INIT_RDLVL_COMPLEX_READ) )
prbs_gen_oclk_clk_en <= #TCQ 1'b1;
generate
if (RANKS < 2) begin
always @(posedge clk)
if (rst) begin
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
rdlvl_start_pre <= #TCQ 1'b0;
prbs_rdlvl_start <= #TCQ 1'b0;
end else begin
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))begin
rdlvl_start_pre <= #TCQ 1'b1;
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
end
if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&
(init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin
prbs_rdlvl_start <= #TCQ 1'b1;
end
end
end else begin
always @(posedge clk)
if (rst || rdlvl_stg1_rank_done) begin
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
rdlvl_start_pre <= #TCQ 1'b0;
prbs_rdlvl_start <= #TCQ 1'b0;
end else begin
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))begin
rdlvl_start_pre <= #TCQ 1'b1;
rdlvl_stg1_start <= #TCQ rdlvl_start_dly0_r[14];
end
if (pi_dqs_found_done && rdlvl_stg1_done && ~prbs_rdlvl_done &&
(init_state_r == INIT_RDLVL_COMPLEX_PI_WAIT) && (WRLVL == "ON")) begin
prbs_rdlvl_start <= #TCQ 1'b1;
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || dqsfound_retry || wrlvl_byte_redo) begin
pi_dqs_found_start <= #TCQ 1'b0;
wrcal_start <= #TCQ 1'b0;
end else begin
if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)
pi_dqs_found_start <= #TCQ 1'b1;
if (wrcal_start_dly_r[5])
wrcal_start <= #TCQ 1'b1;
end
end // else: !if(rst)
always @(posedge clk)
if (rst)
oclkdelay_calib_start <= #TCQ 1'b0;
else if (oclkdelay_start_dly_r[5])
oclkdelay_calib_start <= #TCQ 1'b1;
always @(posedge clk)
if (rst)
pi_dqs_found_done_r1 <= #TCQ 1'b0;
else
pi_dqs_found_done_r1 <= #TCQ pi_dqs_found_done;
always @(posedge clk)
wrlvl_final_r <= #TCQ wrlvl_final;
// Reset IN_FIFO after final write leveling to make sure the FIFO
// pointers are initialized
always @(posedge clk)
if (rst || (init_state_r == INIT_WRCAL_WRITE) || (init_state_r == INIT_REFRESH))
wrlvl_final_if_rst <= #TCQ 1'b0;
else if (wrlvl_done_r && //(wrlvl_final_r && wrlvl_done_r &&
(init_state_r == INIT_WRLVL_LOAD_MR2))
wrlvl_final_if_rst <= #TCQ 1'b1;
// Constantly enable DQS while write leveling is enabled in the memory
// This is more to get rid of warnings in simulation, can later change
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
always @(posedge clk)
if (rst ||
((init_state_r1 != INIT_WRLVL_START) &&
(init_state_r == INIT_WRLVL_START)))
wrlvl_odt_ctl <= #TCQ 1'b0;
else if (wrlvl_rank_done && ~wrlvl_rank_done_r1)
wrlvl_odt_ctl <= #TCQ 1'b1;
generate
if (nCK_PER_CLK == 4) begin: en_cnt_div4
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd12;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_odt_ctl)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end else begin: en_cnt_div2
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd21;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_odt_ctl)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_active <= #TCQ 1'b0;
else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)
wrlvl_active <= #TCQ 1'b1;
// signal used to assert DQS for write leveling.
// the DQS will be asserted once every 16 clock cycles.
always @(posedge clk)begin
if(rst || (enable_wrlvl_cnt != 5'd1)) begin
wr_level_dqs_asrt <= #TCQ 1'd0;
end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin
wr_level_dqs_asrt <= #TCQ 1'd1;
end
end
always @ (posedge clk) begin
if (rst || (wrlvl_done_r && ~wrlvl_done_r1))
dqs_asrt_cnt <= #TCQ 2'd0;
else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)
dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);
end
always @ (posedge clk) begin
if (rst || ~wrlvl_active)
wr_lvl_start <= #TCQ 1'd0;
else if (dqs_asrt_cnt == 2'd3)
wr_lvl_start <= #TCQ 1'd1;
end
always @(posedge clk) begin
if (rst)
wl_sm_start <= #TCQ 1'b0;
else
wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;
end
always @(posedge clk) begin
wrlvl_active_r1 <= #TCQ wrlvl_active;
wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;
wrlvl_done_r <= #TCQ wrlvl_done;
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
wrlvl_rank_done_r4 <= #TCQ wrlvl_rank_done_r3;
wrlvl_rank_done_r5 <= #TCQ wrlvl_rank_done_r4;
wrlvl_rank_done_r6 <= #TCQ wrlvl_rank_done_r5;
wrlvl_rank_done_r7 <= #TCQ wrlvl_rank_done_r6;
end
always @ (posedge clk) begin
//if (rst)
wrlvl_rank_cntr <= #TCQ 3'd0;
//else if (wrlvl_rank_done)
// wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
end
//*****************************************************************
// Precharge request logic - those calibration logic blocks
// that require greater than tRAS(max) to finish must break up
// their calibration into smaller units of time, with precharges
// issued in between. This is done using the XXX_PRECH_REQ and
// PRECH_DONE handshaking between PHY_INIT and those blocks
//*****************************************************************
// Shared request from multiple sources
assign prech_req = oclk_prech_req | rdlvl_prech_req | wrcal_prech_req | prbs_rdlvl_prech_req |
(dqs_found_prech_req & (init_state_r == INIT_RDLVL_STG2_READ_WAIT));
// Handshaking logic to force precharge during read leveling, and to
// notify read leveling logic when precharge has been initiated and
// it's okay to proceed with leveling again
always @(posedge clk)
if (rst) begin
prech_req_r <= #TCQ 1'b0;
prech_req_posedge_r <= #TCQ 1'b0;
prech_pending_r <= #TCQ 1'b0;
end else begin
prech_req_r <= #TCQ prech_req;
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
if (prech_req_posedge_r)
prech_pending_r <= #TCQ 1'b1;
// Clear after we've finished with the precharge and have
// returned to issuing read leveling calibration reads
else if (prech_done_pre)
prech_pending_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || prech_done_r3)
mask_lim_done <= #TCQ 1'b0;
else if (prech_pending_r)
mask_lim_done <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || prbs_rdlvl_done_r3)
complex_mask_lim_done <= #TCQ 1'b0;
else if (~prbs_rdlvl_done && complex_oclkdelay_calib_start_int)
complex_mask_lim_done <= #TCQ 1'b1;
end
//Complex oclkdelay calibrration
//***************************************************************************
// Various timing counters
//***************************************************************************
//*****************************************************************
// Generic delay for various states that require it (e.g. for turnaround
// between read and write). Make this a sufficiently large number of clock
// cycles to cover all possible frequencies and memory components)
// Requirements for this counter:
// 1. Greater than tMRD
// 2. tRFC (refresh-active) for DDR2
// 3. (list the other requirements, slacker...)
//*****************************************************************
always @(posedge clk) begin
case (init_state_r)
INIT_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR2_WAIT,
INIT_MPR_WAIT,
INIT_MPR_DISABLE_PREWAIT,
INIT_MPR_DISABLE_WAIT,
INIT_OCLKDELAY_ACT_WAIT,
INIT_OCLKDELAY_WRITE_WAIT,
INIT_RDLVL_ACT_WAIT,
INIT_RDLVL_STG1_WRITE_READ,
INIT_RDLVL_STG2_READ_WAIT,
INIT_WRCAL_ACT_WAIT,
INIT_WRCAL_WRITE_READ,
INIT_WRCAL_READ_WAIT,
INIT_PRECHARGE_PREWAIT,
INIT_PRECHARGE_WAIT,
INIT_DDR2_PRECHARGE_WAIT,
INIT_REG_WRITE_WAIT,
INIT_REFRESH_WAIT,
INIT_REFRESH_RNK2_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_cmd_r <= #TCQ cnt_cmd_r;
else
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
end
INIT_WRLVL_WAIT:
cnt_cmd_r <= #TCQ 'b0;
default:
cnt_cmd_r <= #TCQ 'b0;
endcase
end
// pulse when count reaches terminal count
always @(posedge clk)
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
// For ODT deassertion - hold throughout post read/write wait stage, but
// deassert before next command. The post read/write stage is very long, so
// we simply address the longest case here plus some margin.
always @(posedge clk)
cnt_cmd_done_m7_r <= #TCQ (cnt_cmd_r == (CNTNEXT_CMD - 7));
//************************************************************************
// Added to support PO fine delay inc when TG errors
always @(posedge clk) begin
case (init_state_r)
INIT_WRCAL_READ_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_wait <= #TCQ cnt_wait;
else
cnt_wait <= #TCQ cnt_wait + 1;
end
default:
cnt_wait <= #TCQ 'b0;
endcase
end
always @(posedge clk)
cnt_wrcal_rd <= #TCQ (cnt_wait == 'd4);
always @(posedge clk) begin
if (rst || ~temp_wrcal_done)
temp_lmr_done <= #TCQ 1'b0;
else if (temp_wrcal_done && (init_state_r == INIT_LOAD_MR))
temp_lmr_done <= #TCQ 1'b1;
end
always @(posedge clk)
temp_wrcal_done_r <= #TCQ temp_wrcal_done;
always @(posedge clk)
if (rst) begin
tg_timer_go <= #TCQ 1'b0;
end else if ((PRE_REV3ES == "ON") && temp_wrcal_done && temp_lmr_done &&
(init_state_r == INIT_WRCAL_READ_WAIT)) begin
tg_timer_go <= #TCQ 1'b1;
end else begin
tg_timer_go <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || (temp_wrcal_done && ~temp_wrcal_done_r) ||
(init_state_r == INIT_PRECHARGE_PREWAIT))
tg_timer <= #TCQ 'd0;
else if ((pi_phaselock_timer == PHASELOCKED_TIMEOUT) &&
tg_timer_go &&
(tg_timer != TG_TIMER_TIMEOUT))
tg_timer <= #TCQ tg_timer + 1;
end
always @(posedge clk) begin
if (rst)
tg_timer_done <= #TCQ 1'b0;
else if (tg_timer == TG_TIMER_TIMEOUT)
tg_timer_done <= #TCQ 1'b1;
else
tg_timer_done <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
no_rst_tg_mc <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT) && wrcal_read_req)
no_rst_tg_mc <= #TCQ 1'b1;
else
no_rst_tg_mc <= #TCQ 1'b0;
end
//************************************************************************
always @(posedge clk) begin
if (rst)
detect_pi_found_dqs <= #TCQ 1'b0;
else if ((cnt_cmd_r == 7'b0111111) &&
(init_state_r == INIT_RDLVL_STG2_READ_WAIT))
detect_pi_found_dqs <= #TCQ 1'b1;
else
detect_pi_found_dqs <= #TCQ 1'b0;
end
//*****************************************************************
// Initial delay after power-on for RESET, CKE
// NOTE: Could reduce power consumption by turning off these counters
// after initial power-up (at expense of more logic)
// NOTE: Likely can combine multiple counters into single counter
//*****************************************************************
// Create divided by 1024 version of clock
always @(posedge clk)
if (rst) begin
cnt_pwron_ce_r <= #TCQ 10'h000;
pwron_ce_r <= #TCQ 1'b0;
end else begin
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
end
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
always @(posedge clk)
if (rst)
cnt_pwron_r <= #TCQ 'b0;
else if (pwron_ce_r)
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
always @(posedge clk)
if (rst || ~phy_ctl_ready) begin
cnt_pwron_reset_done_r <= #TCQ 1'b0;
cnt_pwron_cke_done_r <= #TCQ 1'b0;
end else begin
// skip power-up count for simulation purposes only
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
(SIM_INIT_OPTION == "SKIP_INIT")) begin
cnt_pwron_reset_done_r <= #TCQ 1'b1;
cnt_pwron_cke_done_r <= #TCQ 1'b1;
end else begin
// otherwise, create latched version of done signal for RESET, CKE
if (DRAM_TYPE == "DDR3") begin
if (!cnt_pwron_reset_done_r)
cnt_pwron_reset_done_r
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end else begin // DDR2
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end
end
end // else: !if(rst || ~phy_ctl_ready)
always @(posedge clk)
cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;
// Keep RESET asserted and CKE deasserted until after power-on delay
always @(posedge clk or posedge rst) begin
if (rst)
phy_reset_n <= #TCQ 1'b0;
else
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
end
//*****************************************************************
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
// CKE deassertion before first MRS command can be asserted
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_txpr_r <= #TCQ 'b0;
cnt_txpr_done_r <= #TCQ 1'b0;
end else begin
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
if (!cnt_txpr_done_r)
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
end
//*****************************************************************
// Counter for the initial 400ns wait for issuing precharge all
// command after CKE assertion. Only for DDR2.
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_init_pre_wait_r <= #TCQ 'b0;
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
end else begin
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
if (!cnt_init_pre_wait_done_r)
cnt_init_pre_wait_done_r
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
end
//*****************************************************************
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
// (tZQINIT). Both take the same amount of time (512*tCK)
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_r <= #TCQ 'b0;
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else if (~(phy_ctl_full || phy_cmd_full)) begin
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
if (!cnt_dllk_zqinit_done_r)
cnt_dllk_zqinit_done_r
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
end
//*****************************************************************
// Keep track of which MRS counter needs to be programmed during
// memory initialization
// The counter and the done signal are reset an additional time
// for DDR2. The same signals are used for the additional DDR2
// initialization sequence.
//*****************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE)||
((init_state_r == INIT_REFRESH)
&& (~mem_init_done_r))) begin
cnt_init_mr_r <= #TCQ 'b0;
cnt_init_mr_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_LOAD_MR) begin
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
end
//*****************************************************************
// Flag to tell if the first precharge for DDR2 init sequence is
// done
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_pre_flag_r<= #TCQ 'b0;
else if (init_state_r == INIT_LOAD_MR)
ddr2_pre_flag_r<= #TCQ 1'b1;
// reset the flag for multi rank case
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_pre_flag_r <= #TCQ 'b0;
//*****************************************************************
// Flag to tell if the refresh stat for DDR2 init sequence is
// reached
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_refresh_flag_r<= #TCQ 'b0;
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))
// reset the flag for multi rank case
ddr2_refresh_flag_r<= #TCQ 1'b1;
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_refresh_flag_r <= #TCQ 'b0;
//*****************************************************************
// Keep track of the number of auto refreshes for DDR2
// initialization. The spec asks for a minimum of two refreshes.
// Four refreshes are performed here. The two extra refreshes is to
// account for the 200 clock cycle wait between step h and l.
// Without the two extra refreshes we would have to have a
// wait state.
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE) begin
cnt_init_af_r <= #TCQ 'b0;
cnt_init_af_done_r <= #TCQ 1'b0;
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
end
//*****************************************************************
// Keep track of the register control word programming for
// DDR3 RDIMM
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
reg_ctrl_cnt_r <= #TCQ 'b0;
else if (init_state_r == INIT_REG_WRITE)
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
generate
if (RANKS < 2) begin: one_rank
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done ||
(complex_byte_rd_done) || prbs_rdlvl_done_pulse )
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
end else begin: two_ranks
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done ||
(complex_byte_rd_done) || prbs_rdlvl_done_pulse ||
(rdlvl_stg1_rank_done ))
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst)
rnk_ref_cnt <= #TCQ 1'b0;
else if (stg1_wr_done &&
(init_state_r == INIT_REFRESH_WAIT) && cnt_cmd_done_r)
rnk_ref_cnt <= #TCQ ~rnk_ref_cnt;
always @(posedge clk)
if (rst || (init_state_r == INIT_MPR_RDEN) || (init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) || (init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) || (init_state_r ==INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT))
num_refresh <= #TCQ 'd0;
else if ((init_state_r == INIT_REFRESH) &&
(~pi_dqs_found_done || ((DRAM_TYPE == "DDR3") && ~oclkdelay_calib_done) ||
(rdlvl_stg1_done && ~prbs_rdlvl_done) ||
(prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)))
num_refresh <= #TCQ num_refresh + 1;
//***************************************************************************
// Initialization state machine
//***************************************************************************
//*****************************************************************
// Next-state logic
//*****************************************************************
always @(posedge clk)
if (rst)begin
init_state_r <= #TCQ INIT_IDLE;
init_state_r1 <= #TCQ INIT_IDLE;
end else begin
init_state_r <= #TCQ init_next_state;
init_state_r1 <= #TCQ init_state_r;
end
always @(*) begin
init_next_state = init_state_r;
(* full_case, parallel_case *) case (init_state_r)
//*******************************************************
// DRAM initialization
//*******************************************************
// Initial state - wait for:
// 1. Power-on delays to pass
// 2. PHY Control Block to assert phy_ctl_ready
// 3. PHY Control FIFO must not be FULL
// 4. Read path initialization to finish
INIT_IDLE:
if (cnt_pwron_cke_done_r && phy_ctl_ready && ck_addr_cmd_delay_done && delay_incdec_done
&& ~(phy_ctl_full || phy_cmd_full) ) begin
// If skipping memory initialization (simulation only)
if (SIM_INIT_OPTION == "SKIP_INIT")
//if (WRLVL == "ON")
// Proceed to write leveling
// init_next_state = INIT_WRLVL_START;
//else //if (SIM_CAL_OPTION != "SKIP_CAL")
// Proceed to Phaser_In phase lock
init_next_state = INIT_RDLVL_ACT;
// else
// Skip read leveling
//init_next_state = INIT_DONE;
else
init_next_state = INIT_WAIT_CKE_EXIT;
end
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
INIT_WAIT_CKE_EXIT:
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")
&& ~(phy_ctl_full || phy_cmd_full)) begin
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
(RANKS > 1)))
//register write for reg dimm. Some register chips
// have the register chip in a pre-programmed state
// in that case the nCS_PER_RANK == 1 && RANKS == 1
init_next_state = INIT_REG_WRITE;
else
// Load mode register - this state is repeated multiple times
init_next_state = INIT_LOAD_MR;
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2")
&& ~(phy_ctl_full || phy_cmd_full))
// DDR2 start with a precharge all command
init_next_state = INIT_DDR2_PRECHARGE;
INIT_REG_WRITE:
init_next_state = INIT_REG_WRITE_WAIT;
INIT_REG_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(reg_ctrl_cnt_r == 4'd8)
init_next_state = INIT_LOAD_MR;
else
init_next_state = INIT_REG_WRITE;
end
INIT_LOAD_MR:
init_next_state = INIT_LOAD_MR_WAIT;
// After loading MR, wait at least tMRD
INIT_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// If finished loading all mode registers, proceed to next step
if (prbs_rdlvl_done && pi_dqs_found_done && rdlvl_stg1_done)
// for ddr3 when the correct burst length is writtern at end
init_next_state = INIT_PRECHARGE;
else if (~wrcal_done && temp_lmr_done)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_init_mr_done_r)begin
if(DRAM_TYPE == "DDR3")
init_next_state = INIT_ZQCL;
else begin //DDR2
if(ddr2_refresh_flag_r)begin
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_DDR2_MULTI_RANK;
else
init_next_state = INIT_RDLVL_ACT;
// ddr2 initialization done.load mode state after refresh
end else
init_next_state = INIT_DDR2_PRECHARGE;
end
end else
init_next_state = INIT_LOAD_MR;
end
// DDR2 multi rank transition state
INIT_DDR2_MULTI_RANK:
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
INIT_DDR2_MULTI_RANK_WAIT:
init_next_state = INIT_DDR2_PRECHARGE;
// Initial ZQ calibration
INIT_ZQCL:
init_next_state = INIT_WAIT_DLLK_ZQINIT;
// Wait until both DLL have locked, and ZQ calibration done
INIT_WAIT_DLLK_ZQINIT:
if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_LOAD_MR;
//else if (WRLVL == "ON")
// init_next_state = INIT_WRLVL_START;
else
// skip write-leveling (e.g. for DDR2 interface)
init_next_state = INIT_RDLVL_ACT;
// Initial precharge for DDR2
INIT_DDR2_PRECHARGE:
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
INIT_DDR2_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if (ddr2_pre_flag_r)
init_next_state = INIT_REFRESH;
else // from precharge state initially go to load mode
init_next_state = INIT_LOAD_MR;
end
INIT_REFRESH:
if ((SKIP_CALIB == "TRUE") && ~calib_tap_inc_done && pi_dqs_found_done)
init_next_state = INIT_SKIP_CALIB_WAIT;
else if ((RANKS == 2) && (chip_cnt_r == RANKS - 1))
init_next_state = INIT_REFRESH_RNK2_WAIT;
else
init_next_state = INIT_REFRESH_WAIT;
INIT_REFRESH_RNK2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
INIT_REFRESH_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
if(cnt_init_af_done_r && (~mem_init_done_r))
// go to lm state as part of DDR2 init sequence
init_next_state = INIT_LOAD_MR;
// Go to state to issue back-to-back writes during limit check and centering
else if (~oclkdelay_calib_done && (mpr_last_byte_done || mpr_rdlvl_done) && (DRAM_TYPE == "DDR3")) begin
if (num_refresh == 'd8)
init_next_state = INIT_OCAL_CENTER_ACT;
else
init_next_state = INIT_REFRESH;
end else if(rdlvl_stg1_done && oclkdelay_center_calib_done &&
complex_oclkdelay_calib_done && ~wrlvl_done_r1 && (WRLVL == "ON"))
init_next_state = INIT_WRLVL_START;
else if (pi_dqs_found_done && ~wrlvl_done_r1 && ~wrlvl_final && ~wrlvl_byte_redo && (WRLVL == "ON"))
init_next_state = INIT_WRLVL_START;
else if ((((prbs_last_byte_done_r || prbs_rdlvl_done) && ~complex_oclkdelay_calib_done
&& pi_dqs_found_done) && (WRLVL == "ON")) //&& rdlvl_stg1_done // changed for new algo 3/26
&& mem_init_done_r) begin
if (num_refresh == 'd8) begin
if (BYPASS_COMPLEX_OCAL == "FALSE")
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
else
init_next_state = INIT_WRCAL_ACT;
end else
init_next_state = INIT_REFRESH;
end else if (~pi_dqs_found_done ||
(rdlvl_stg1_done && ~prbs_rdlvl_done && ~complex_oclkdelay_calib_done) ||
((CLK_PERIOD/nCK_PER_CLK <= 2500) && wrcal_done && ~rdlvl_stg1_done) ||
((CLK_PERIOD/nCK_PER_CLK > 2500) && wrlvl_done_r1 && ~rdlvl_stg1_done)) begin
if (num_refresh == 'd8)
init_next_state = INIT_RDLVL_ACT;
else
init_next_state = INIT_REFRESH;
end else if ((~wrcal_done && wrlvl_byte_redo)&& (DRAM_TYPE == "DDR3")
&& (CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRLVL_LOAD_MR2;
else if (((prbs_rdlvl_done && rdlvl_stg1_done && complex_oclkdelay_calib_done && pi_dqs_found_done) && (WRLVL == "ON"))
&& mem_init_done_r && (CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRCAL_ACT;
else if (pi_dqs_found_done && (DRAM_TYPE == "DDR3") && ~(mpr_last_byte_done || mpr_rdlvl_done)) begin
if (num_refresh == 'd8)
init_next_state = INIT_MPR_RDEN;
else
init_next_state = INIT_REFRESH;
end else if (((oclkdelay_calib_done && wrlvl_final && ~wrlvl_done_r1) || // changed for new algo 3/25
(~wrcal_done && wrlvl_byte_redo)) && (DRAM_TYPE == "DDR3"))
init_next_state = INIT_WRLVL_LOAD_MR2;
else if ((~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
&& pi_dqs_found_done)
init_next_state = INIT_WRCAL_ACT;
else if (mem_init_done_r) begin
if (RANKS < 2)
init_next_state = INIT_RDLVL_ACT;
else if (stg1_wr_done && ~rnk_ref_cnt && ~rdlvl_stg1_done)
init_next_state = INIT_PRECHARGE;
else
init_next_state = INIT_RDLVL_ACT;
end else // to DDR2 init state as part of DDR2 init sequence
init_next_state = INIT_REFRESH;
end
INIT_SKIP_CALIB_WAIT:
if (calib_tap_inc_done)
init_next_state = INIT_WRCAL_ACT;
//******************************************************
// Write Leveling
//*******************************************************
// Enable write leveling in MR1 and start write leveling
// for current rank
INIT_WRLVL_START:
init_next_state = INIT_WRLVL_WAIT;
// Wait for both MR load and write leveling to complete
// (write leveling should take much longer than MR load..)
INIT_WRLVL_WAIT:
if (wrlvl_rank_done_r7 && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR;
// Disable write leveling in MR1 for current rank
INIT_WRLVL_LOAD_MR:
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
INIT_WRLVL_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR2;
// Load MR2 to set ODT: Dynamic ODT for single rank case
// And ODTs for multi-rank case as well
INIT_WRLVL_LOAD_MR2:
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
// Wait tMRD before proceeding
INIT_WRLVL_LOAD_MR2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
//if (wrlvl_byte_done)
// init_next_state = INIT_PRECHARGE_PREWAIT;
// else if ((RANKS == 2) && wrlvl_rank_done_r2)
// init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
if (~wrlvl_done_r1)
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip rdlvl, then we're done
init_next_state = INIT_DONE;
else
// Otherwise, proceed to read leveling
//init_next_state = INIT_RDLVL_ACT;
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//*******************************************************
// Read Leveling
//*******************************************************
// single row activate. All subsequent read leveling writes and
// read will take place in this row
INIT_RDLVL_ACT:
init_next_state = INIT_RDLVL_ACT_WAIT;
// hang out for awhile before issuing subsequent column commands
// it's also possible to reach this state at various points
// during read leveling - determine what the current stage is
INIT_RDLVL_ACT_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// Just finished an activate. Now either write, read, or precharge
// depending on where we are in the training sequence
if (!pi_calib_done_r1)
init_next_state = INIT_PI_PHASELOCK_READS;
else if (!pi_dqs_found_done)
// (!pi_dqs_found_start || pi_dqs_found_rank_done))
init_next_state = INIT_RDLVL_STG2_READ;
else if (~wrcal_done && (WRLVL == "ON") && (CLK_PERIOD/nCK_PER_CLK <= 2500))
init_next_state = INIT_WRCAL_ACT_WAIT;
else if ((!rdlvl_stg1_done && ~stg1_wr_done && ~rdlvl_last_byte_done) ||
(!prbs_rdlvl_done && ~stg1_wr_done && ~prbs_last_byte_done)) begin
// Added to avoid rdlvl_stg1 write data pattern at the start of PRBS rdlvl
if (!prbs_rdlvl_done && ~stg1_wr_done && rdlvl_last_byte_done)
init_next_state = INIT_RDLVL_ACT_WAIT;
else
init_next_state = INIT_RDLVL_STG1_WRITE;
end else if ((!rdlvl_stg1_done && rdlvl_stg1_start_int) || !prbs_rdlvl_done) begin
if (rdlvl_last_byte_done || prbs_last_byte_done)
// Added to avoid extra reads at the end of read leveling
init_next_state = INIT_RDLVL_ACT_WAIT;
else begin
// Case 2: If in stage 1, and just precharged after training
// previous byte, then continue reading
if (rdlvl_stg1_done)
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
else
init_next_state = INIT_RDLVL_STG1_READ;
end
end else if ((prbs_rdlvl_done && rdlvl_stg1_done && (RANKS == 1)) && (WRLVL == "ON") &&
(CLK_PERIOD/nCK_PER_CLK > 2500))
init_next_state = INIT_WRCAL_ACT_WAIT;
else
// Otherwise, if we're finished with calibration, then precharge
// the row - silly, because we just opened it - possible to take
// this out by adding logic to avoid the ACT in first place. Make
// sure that cnt_cmd_done will handle tRAS(min)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//**************************************************
// Back-to-back reads for Phaser_IN Phase locking
// DQS to FREQ_REF clock
//**************************************************
INIT_PI_PHASELOCK_READS:
if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 1 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
// PRBS pattern of TBD length
INIT_RDLVL_STG1_WRITE:
// 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle
// 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words
// 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words
// An entire row worth of writes issued before proceeding to reads
// The number of write is (2^column width)/burst length to accomodate
// PRBS pattern for window detection.
//VCCO/VCCAUX write is not done
if ((complex_num_writes_dec == 1) && ~complex_row0_wr_done && prbs_rdlvl_done && rdlvl_stg1_done_r1)
init_next_state = INIT_OCAL_COMPLEX_WRITE_WAIT;
//back to back write from row1
else if (stg1_wr_rd_cnt == 9'd1) begin
if (rdlvl_stg1_done_r1)
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
else
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
end
INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT:
if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (complex_wait_cnt == 'd15)
//At the end of the byte, it goes to REFRESH
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE;
INIT_RDLVL_COMPLEX_PRECHARGE:
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;
INIT_RDLVL_COMPLEX_PRECHARGE_WAIT:
if (complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (complex_wait_cnt == 'd15) begin
if (prbs_rdlvl_done || prbs_last_byte_done_r) begin // changed for new algo 3/26
// added condition to ensure that limit starts after rdlvl_stg1_done is asserted in the bypass complex rdlvl mode
if ((~prbs_rdlvl_done && complex_oclkdelay_calib_start_int) || ~lim_done)
init_next_state = INIT_OCAL_CENTER_ACT; //INIT_OCAL_COMPLEX_ACT; // changed for new algo 3/26
else if (lim_done && complex_oclkdelay_calib_start_r2)
init_next_state = INIT_RDLVL_COMPLEX_ACT;
else
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_WAIT;
end else
init_next_state = INIT_RDLVL_COMPLEX_ACT;
end
INIT_RDLVL_COMPLEX_ACT:
//only for sampling boundary it need to wait
//when initial pi dec is not done in complex per-bit, it need to wait
if(prbs_rdlvl_start && (num_samples_done_r || ~complex_init_pi_dec_done))
init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT;
else init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT;
//wait PI movement is done before proceeding read
INIT_RDLVL_COMPLEX_PI_WAIT:
if(complex_pi_incdec_done)
init_next_state = INIT_RDLVL_COMPLEX_ACT_WAIT;
INIT_RDLVL_COMPLEX_ACT_WAIT:
if (complex_rdlvl_int_ref_req || prech_req_posedge_r) //prech req always happen in this state
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (complex_wait_cnt == 'd15) begin
if (oclkdelay_center_calib_start)
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
else if (stg1_wr_done)
init_next_state = INIT_RDLVL_COMPLEX_READ;
else if (~complex_row1_wr_done)
if (complex_oclkdelay_calib_start_int && complex_ocal_num_samples_done_r) //WAIT for resume signal for write
init_next_state = INIT_OCAL_COMPLEX_RESUME_WAIT;
else
init_next_state = INIT_RDLVL_STG1_WRITE;
else
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
end
// Write-read turnaround
INIT_RDLVL_STG1_WRITE_READ:
if (reset_rd_addr_r1)
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
if (rdlvl_stg1_done_r1)
//before going to read, wait for PI inc/dec done
init_next_state = INIT_RDLVL_COMPLEX_PI_WAIT;
else
init_next_state = INIT_RDLVL_STG1_READ;
end
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
// No precharges when reads provided to Phaser_IN for phase locking
// FREQ_REF to read DQS since data integrity is not important.
INIT_RDLVL_STG1_READ:
if (rdlvl_stg1_rank_done || (rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
INIT_RDLVL_COMPLEX_READ:
if (prech_req_posedge_r || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
//For non-back-to-back reads from row0 (VCCO and VCCAUX pattern)
else if (~prbs_rdlvl_done && (complex_num_reads_dec == 1) && ~complex_row0_rd_done)
init_next_state = INIT_RDLVL_COMPLEX_READ_WAIT;
//For back-to-back reads from row1 (ISI pattern)
else if (stg1_wr_rd_cnt == 'd1)
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
INIT_RDLVL_COMPLEX_READ_WAIT:
if (prech_req_posedge_r || complex_rdlvl_int_ref_req || (prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (stg1_wr_rd_cnt == 'd1)
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
else if (complex_wait_cnt == 'd15)
init_next_state = INIT_RDLVL_COMPLEX_READ;
//*********************************************
// DQSFOUND calibration (set of 4 reads with gaps)
//*********************************************
// Read of training data. Note that Stage 2 is not a constant read,
// instead there is a large gap between each set of back-to-back reads
INIT_RDLVL_STG2_READ:
// 4 read commands issued back-to-back
if (num_reads == 'b1)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
// Wait before issuing the next set of reads. If a precharge request
// comes in then handle - this can occur after stage 2 calibration is
// completed for a DQS group
INIT_RDLVL_STG2_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (pi_dqs_found_rank_done ||
pi_dqs_found_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r)
init_next_state = INIT_RDLVL_STG2_READ;
end
//******************************************************************
// MPR Read Leveling for DDR3 OCLK_DELAYED calibration
//******************************************************************
// Issue Load Mode Register 3 command with A[2]=1, A[1:0]=2'b00
// to enable Multi Purpose Register (MPR) Read
INIT_MPR_RDEN:
init_next_state = INIT_MPR_WAIT;
//Wait tMRD, tMOD
INIT_MPR_WAIT:
if (cnt_cmd_done_r) begin
init_next_state = INIT_MPR_READ;
end
// Issue back-to-back read commands to read from MPR with
// Address bus 0x0000 for BL=8. DQ[0] will output the pre-defined
// MPR pattern of 01010101 (Rise0 = 1'b0, Fall0 = 1'b1 ...)
INIT_MPR_READ:
if (mpr_rdlvl_done || mpr_rnk_done || rdlvl_prech_req)
init_next_state = INIT_MPR_DISABLE_PREWAIT;
INIT_MPR_DISABLE_PREWAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_MPR_DISABLE;
// Issue Load Mode Register 3 command with A[2]=0 to disable
// MPR read
INIT_MPR_DISABLE:
init_next_state = INIT_MPR_DISABLE_WAIT;
INIT_MPR_DISABLE_WAIT:
init_next_state = INIT_PRECHARGE_PREWAIT;
//***********************************************************************
// OCLKDELAY Calibration
//***********************************************************************
// This calibration requires single write followed by single read to
// determine the Phaser_Out stage 3 delay required to center write DQS
// in write DQ valid window.
// Single Row Activate command before issuing Write command
INIT_OCLKDELAY_ACT:
init_next_state = INIT_OCLKDELAY_ACT_WAIT;
INIT_OCLKDELAY_ACT_WAIT:
if (cnt_cmd_done_r && ~oclk_prech_req)
init_next_state = INIT_OCLKDELAY_WRITE;
else if (oclkdelay_calib_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
INIT_OCLKDELAY_WRITE:
if (oclk_wr_cnt == 4'd1)
init_next_state = INIT_OCLKDELAY_WRITE_WAIT;
INIT_OCLKDELAY_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if (oclkdelay_int_ref_req)
init_next_state = INIT_PRECHARGE_PREWAIT;
else
init_next_state = INIT_OCLKDELAY_READ;
end
INIT_OCLKDELAY_READ:
init_next_state = INIT_OCLKDELAY_READ_WAIT;
INIT_OCLKDELAY_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if ((oclk_calib_resume_level || oclk_calib_resume) && ~oclkdelay_int_ref_req)
init_next_state = INIT_OCLKDELAY_WRITE;
else if (oclkdelay_calib_done || prech_req_posedge_r ||
wrlvl_final || oclkdelay_int_ref_req)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (oclkdelay_center_calib_start)
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
end
//*********************************************
// Write calibration
//*********************************************
// single row activate
INIT_WRCAL_ACT:
init_next_state = INIT_WRCAL_ACT_WAIT;
// hang out for awhile before issuing subsequent column command
INIT_WRCAL_ACT_WAIT:
if (cnt_cmd_done_r && ~wrcal_prech_req)
init_next_state = INIT_WRCAL_WRITE;
else if (wrcal_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
// Write training pattern for write calibration
INIT_WRCAL_WRITE:
// Once we've issued enough commands for 8 words - proceed to reads
//if (burst_addr_r == 1'b1)
if (wrcal_wr_cnt == 4'd1)
init_next_state = INIT_WRCAL_WRITE_READ;
// Write-read turnaround
INIT_WRCAL_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRCAL_READ;
else if (dqsfound_retry)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
INIT_WRCAL_READ:
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
INIT_WRCAL_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (wrcal_resume_r) begin
if (wrcal_final_chk)
init_next_state = INIT_WRCAL_READ;
else
init_next_state = INIT_WRCAL_WRITE;
end else if (wrcal_done || prech_req_posedge_r || wrcal_act_req ||
// Added to support PO fine delay inc when TG errors
wrlvl_byte_redo || (temp_wrcal_done && ~temp_lmr_done))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (dqsfound_retry)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
else if (wrcal_read_req && cnt_wrcal_rd)
init_next_state = INIT_WRCAL_MULT_READS;
end
INIT_WRCAL_MULT_READS:
// multiple read commands issued back-to-back
if (wrcal_reads == 'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
//*********************************************
// Handling of precharge during and in between read-level stages
//*********************************************
// Make sure we aren't violating any timing specs by precharging
// immediately
INIT_PRECHARGE_PREWAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
// Initiate precharge
INIT_PRECHARGE:
init_next_state = INIT_PRECHARGE_WAIT;
INIT_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if ((wrcal_sanity_chk_done && (DRAM_TYPE == "DDR3")) ||
(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done &&
(DRAM_TYPE == "DDR2")))
init_next_state = INIT_DONE;
else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done && prbs_rdlvl_done &&
pi_dqs_found_done && complex_oclkdelay_calib_done && wrlvl_done_r1 && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2")))
init_next_state = INIT_WRCAL_ACT;
else if ((wrcal_done || (WRLVL == "OFF") || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
&& (rdlvl_stg1_done || (~wrcal_done && temp_wrcal_done && ~temp_lmr_done))
&& prbs_rdlvl_done && complex_oclkdelay_calib_done && wrlvl_done_r1 &rdlvl_stg1_done && pi_dqs_found_done) begin
// after all calibration program the correct burst length
init_next_state = INIT_LOAD_MR;
// Added to support PO fine delay inc when TG errors
end else if (~wrcal_done && temp_wrcal_done && temp_lmr_done)
init_next_state = INIT_WRCAL_READ_WAIT;
else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON"))
// If read leveling finished, proceed to write calibration
init_next_state = INIT_REFRESH;
else
// Otherwise, open row for read-leveling purposes
init_next_state = INIT_REFRESH;
end
//*******************************************************
// COMPLEX OCLK calibration - for fragmented write
//*******************************************************
INIT_OCAL_COMPLEX_ACT:
init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;
INIT_OCAL_COMPLEX_ACT_WAIT:
if (complex_wait_cnt =='d15)
init_next_state = INIT_RDLVL_STG1_WRITE;
INIT_OCAL_COMPLEX_WRITE_WAIT:
if (prech_req_posedge_r || (complex_oclkdelay_calib_done && ~complex_oclkdelay_calib_done_r1))
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (stg1_wr_rd_cnt == 'd1)
init_next_state = INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT;
else if (complex_wait_cnt == 'd15)
init_next_state = INIT_RDLVL_STG1_WRITE;
//wait for all srg2/stg3 tap movement is done and go back to write again
INIT_OCAL_COMPLEX_RESUME_WAIT:
if (complex_oclk_calib_resume)
init_next_state = INIT_RDLVL_STG1_WRITE;
else if (complex_oclkdelay_calib_done || complex_ocal_ref_req )
init_next_state = INIT_PRECHARGE_PREWAIT;
//*******************************************************
// OCAL STG3 Centering calibration
//*******************************************************
INIT_OCAL_CENTER_ACT:
init_next_state = INIT_OCAL_CENTER_ACT_WAIT;
INIT_OCAL_CENTER_ACT_WAIT:
if (ocal_act_wait_cnt == 'd15)
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
INIT_OCAL_CENTER_WRITE:
if(!oclk_center_write_resume && !lim_wr_req)
init_next_state = INIT_OCAL_CENTER_WRITE_WAIT;
INIT_OCAL_CENTER_WRITE_WAIT:
//if (oclkdelay_center_calib_done || prech_req_posedge_r)
if (prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && oclkdelay_calib_done && ~oclkdelay_center_calib_start)
init_next_state = INIT_OCAL_COMPLEX_ACT_WAIT;
else if (lim_done && ~mask_lim_done && ~complex_mask_lim_done && ~oclkdelay_center_calib_start)
init_next_state = INIT_OCLKDELAY_READ_WAIT;
else if (oclk_center_write_resume || lim_wr_req)
init_next_state = INIT_OCAL_CENTER_WRITE;
//*******************************************************
// Initialization/Calibration done. Take a long rest, relax
//*******************************************************
INIT_DONE:
init_next_state = INIT_DONE;
endcase
end
//*****************************************************************
// Initialization done signal - asserted before leveling starts
//*****************************************************************
always @(posedge clk)
if (rst)
mem_init_done_r <= #TCQ 1'b0;
else if ((!cnt_dllk_zqinit_done_r &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3"))
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
(ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
mem_init_done_r <= #TCQ 1'b1;
//*****************************************************************
// Write Calibration signal to PHY Control Block - asserted before
// Write Leveling starts
//*****************************************************************
//generate
//if (RANKS < 2) begin: ranks_one
always @(posedge clk) begin
if (rst || (done_dqs_tap_inc &&
(init_state_r == INIT_WRLVL_LOAD_MR2)))
write_calib <= #TCQ 1'b0;
else if (wrlvl_active_r1)
write_calib <= #TCQ 1'b1;
end
//end else begin: ranks_two
// always @(posedge clk) begin
// if (rst ||
// ((init_state_r1 == INIT_WRLVL_LOAD_MR_WAIT) &&
// ((wrlvl_rank_done_r2 && (chip_cnt_r == RANKS-1)) ||
// (SIM_CAL_OPTION == "FAST_CAL"))))
// write_calib <= #TCQ 1'b0;
// else if (wrlvl_active_r1)
// write_calib <= #TCQ 1'b1;
// end
//end
//endgenerate
//*****************************************************************
// Read Calibration signal to PHY Control Block - asserted after
// Write Leveling during PHASER_IN phase locking stage.
// Must be de-asserted before Read Leveling
//*****************************************************************
always @(posedge clk) begin
if (rst || pi_calib_done_r1)
read_calib_int <= #TCQ 1'b0;
else if (~pi_calib_done_r1 && (init_state_r == INIT_RDLVL_ACT_WAIT) &&
(cnt_cmd_r == CNTNEXT_CMD))
read_calib_int <= #TCQ 1'b1;
end
always @(posedge clk)
read_calib_r <= #TCQ read_calib_int;
always @(posedge clk) begin
if (rst || pi_calib_done_r1)
read_calib <= #TCQ 1'b0;
else if (~pi_calib_done_r1 && (init_state_r == INIT_PI_PHASELOCK_READS))
read_calib <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst)
pi_calib_done_r <= #TCQ 1'b0;
else if (pi_calib_rank_done_r)// && (chip_cnt_r == RANKS-1))
pi_calib_done_r <= #TCQ 1'b1;
always @(posedge clk)
if (rst)
pi_calib_rank_done_r <= #TCQ 1'b0;
else if (pi_phase_locked_all_r3 && ~pi_phase_locked_all_r4)
pi_calib_rank_done_r <= #TCQ 1'b1;
else
pi_calib_rank_done_r <= #TCQ 1'b0;
always @(posedge clk) begin
if (rst || ((PRE_REV3ES == "ON") && temp_wrcal_done && ~temp_wrcal_done_r))
pi_phaselock_timer <= #TCQ 'd0;
else if (((init_state_r == INIT_PI_PHASELOCK_READS) &&
(pi_phaselock_timer != PHASELOCKED_TIMEOUT)) ||
tg_timer_go)
pi_phaselock_timer <= #TCQ pi_phaselock_timer + 1;
else
pi_phaselock_timer <= #TCQ pi_phaselock_timer;
end
assign pi_phase_locked_err = (pi_phaselock_timer == PHASELOCKED_TIMEOUT) ? 1'b1 : 1'b0;
//*****************************************************************
// DDR3 final burst length programming done. For DDR3 during
// calibration the burst length is fixed to BL8. After calibration
// the correct burst length is programmed.
//*****************************************************************
always @(posedge clk)
if (rst)
ddr3_lm_done_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
(chip_cnt_r == RANKS-1) && wrcal_done)
ddr3_lm_done_r <= #TCQ 1'b1;
always @(posedge clk) begin
pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;
pi_phase_locked_all_r1 <= #TCQ pi_phase_locked_all;
pi_phase_locked_all_r2 <= #TCQ pi_phase_locked_all_r1;
pi_phase_locked_all_r3 <= #TCQ pi_phase_locked_all_r2;
pi_phase_locked_all_r4 <= #TCQ pi_phase_locked_all_r3;
pi_dqs_found_all_r <= #TCQ pi_dqs_found_done;
pi_calib_done_r1 <= #TCQ pi_calib_done_r;
end
//***************************************************************************
// Logic for deep memory (multi-rank) configurations
//***************************************************************************
// For DDR3 asserted when
generate
if (RANKS < 2) begin: single_rank
always @(posedge clk)
chip_cnt_r <= #TCQ 2'b00;
end else begin: dual_rank
always @(posedge clk)
if (rst ||
// Set chip_cnt_r to 2'b00 after both Ranks are read leveled
(rdlvl_stg1_done && prbs_rdlvl_done && ~wrcal_done && (SKIP_CALIB == "FALSE")) ||
// Set chip_cnt_r to 2'b00 after both Ranks are write leveled
(wrlvl_done_r &&
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin
chip_cnt_r <= #TCQ 2'b00;
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) &&
(DRAM_TYPE == "DDR3")) ||
((init_state_r==INIT_REFRESH_RNK2_WAIT) &&
(cnt_cmd_r=='d36)) ||
//mpr_rnk_done ||
//(rdlvl_stg1_rank_done && ~rdlvl_last_byte_done) ||
//(stg1_wr_done && (init_state_r == INIT_REFRESH) &&
//~(rnk_ref_cnt && rdlvl_last_byte_done)) ||
// Increment chip_cnt_r to issue Refresh to second rank
(~pi_dqs_found_all_r &&
(init_state_r==INIT_PRECHARGE_PREWAIT) &&
(cnt_cmd_r=='d36) && (SKIP_CALIB == "FALSE")) ||
// Increment chip_cnt_r when DQSFOUND done for the Rank
(pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r && (SKIP_CALIB == "FALSE")) ||
((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r
&& wrcal_done) ||
((init_state_r == INIT_DDR2_MULTI_RANK)
&& (DRAM_TYPE == "DDR2"))) begin
if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||
// condition to increment chip_cnt during
// final burst length programming for DDR3
~pi_calib_done_r || wrcal_done) //~mpr_rdlvl_done ||
&& (chip_cnt_r != RANKS-1))
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end
end
endgenerate
// verilint STARC-2.2.3.3 off
generate
if ((REG_CTRL == "ON") && (RANKS == 1)) begin: DDR3_RDIMM_1rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[0] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end
end else if (RANKS == 1) begin: DDR3_1rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
phy_int_cs_n[n] <= #TCQ 1'b0;
end
end else begin //odd CWL
for (p = nCS_PER_RANK; p < 2*nCS_PER_RANK; p = p + 1) begin
phy_int_cs_n[p] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end
end else if ((REG_CTRL == "ON") && (RANKS == 2)) begin: DDR3_2rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[0] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
2'b01:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) //even CWL
phy_int_cs_n[1] <= #TCQ 1'b0;
else // odd CWL
phy_int_cs_n[1+1*CS_WIDTH*nCS_PER_RANK] <= #TCQ 1'b0;
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
endcase
end
end
end else if (RANKS == 2) begin: DDR3_2rank
always @(posedge clk) begin
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (init_state_r == INIT_REG_WRITE) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if(!(CWL_M%2)) begin
phy_int_cs_n[0%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[1%nCK_PER_CLK] <= #TCQ 1'b0;
end else begin
phy_int_cs_n[2%nCK_PER_CLK] <= #TCQ 1'b0;
phy_int_cs_n[3%nCK_PER_CLK] <= #TCQ 1'b0;
end
end else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (n = 0; n < nCS_PER_RANK; n = n + 1) begin
phy_int_cs_n[n] <= #TCQ 1'b0;
end
end else begin // odd CWL
for (p = CS_WIDTH*nCS_PER_RANK; p < (CS_WIDTH*nCS_PER_RANK + nCS_PER_RANK); p = p + 1) begin
phy_int_cs_n[p] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
2'b01:begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(rdlvl_wr_rd && new_burst_r && ~mmcm_wr)) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
if (!(CWL_M % 2)) begin //even CWL
for (q = nCS_PER_RANK; q < (2 * nCS_PER_RANK); q = q + 1) begin
phy_int_cs_n[q] <= #TCQ 1'b0;
end
end else begin // odd CWL
for (m = (nCS_PER_RANK*CS_WIDTH + nCS_PER_RANK); m < (nCS_PER_RANK*CS_WIDTH + 2*nCS_PER_RANK); m = m + 1) begin
phy_int_cs_n[m] <= #TCQ 1'b0;
end
end
end else
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
//for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
//
// phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
//end
end
endcase
end
end // always @ (posedge clk)
end
// verilint STARC-2.2.3.3 on
// commented out for now. Need it for DDR2 2T timing
/* end else begin: DDR2
always @(posedge clk)
if (rst) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end else begin
if (init_state_r == INIT_REG_WRITE) begin
// All ranks selected simultaneously
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
end else if ((wrlvl_odt) ||
(init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH)) begin
phy_int_cs_n[0] <= #TCQ 1'b0;
end
else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end // else: !if(rst)
end // block: DDR2 */
endgenerate
assign phy_cs_n = phy_int_cs_n;
//***************************************************************************
// Write/read burst logic for calibration
//***************************************************************************
assign rdlvl_wr = (init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE);
assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||
((init_state_r == INIT_RDLVL_STG1_READ) && ~rdlvl_pi_incdec) || //rdlvl pi dec
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
((init_state_r == INIT_MPR_READ) && ~rdlvl_pi_incdec) ||
(init_state_r == INIT_WRCAL_MULT_READS);
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
assign mmcm_wr = (init_state_r == INIT_OCAL_CENTER_WRITE); //used to de-assert cs_n during centering
// assign mmcm_wr = 'b0; // (init_state_r == INIT_OCAL_CENTER_WRITE);
//***************************************************************************
// Address generation and logic to count # of writes/reads issued during
// certain stages of calibration
//***************************************************************************
// Column address generation logic:
// Keep track of the current column address - since all bursts are in
// increments of 8 only during calibration, we need to keep track of
// addresses [COL_WIDTH-1:3], lower order address bits will always = 0
always @(posedge clk)
if (rst || wrcal_done)
burst_addr_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||
(init_state_r == INIT_OCLKDELAY_ACT_WAIT) ||
(init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS) ||
(init_state_r == INIT_WRCAL_READ_WAIT))
burst_addr_r <= #TCQ 1'b1;
else if (rdlvl_wr_rd && new_burst_r)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
// Read Level Stage 1 requires writes to the entire row since
// a PRBS pattern is being written. This counter keeps track
// of the number of writes which depends on the column width
// The (stg1_wr_rd_cnt==9'd0) condition was added so the col
// address wraps around during stage1 reads
always @(posedge clk)
if (rst || ((init_state_r == INIT_RDLVL_STG1_WRITE_READ) &&
~rdlvl_stg1_done))
stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;
else if (rdlvl_last_byte_done || (stg1_wr_rd_cnt == 9'd1) ||
(prbs_rdlvl_prech_req && (init_state_r == INIT_RDLVL_ACT_WAIT)) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ) begin
if (~complex_row0_wr_done || wr_victim_inc ||
(complex_row1_wr_done && (~complex_row0_rd_done || (complex_row0_rd_done && complex_row1_rd_done))))
stg1_wr_rd_cnt <= #TCQ 'd127;
else
stg1_wr_rd_cnt <= #TCQ prbs_rdlvl_done?'d30 :'d22;
end else if (((init_state_r == INIT_RDLVL_STG1_WRITE) && new_burst_r && ~phy_data_full)
||((init_state_r == INIT_RDLVL_COMPLEX_READ) && rdlvl_stg1_done))
stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;
always @(posedge clk)
if (rst)
wr_victim_inc <= #TCQ 1'b0;
else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2) && ~stg1_wr_done)
wr_victim_inc <= #TCQ 1'b1;
else
wr_victim_inc <= #TCQ 1'b0;
always @(posedge clk)
reset_rd_addr_r1 <= #TCQ reset_rd_addr;
generate
if (FIXED_VICTIM == "FALSE") begin: row_cnt_victim_rotate
always @(posedge clk)
if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)
complex_row_cnt <= #TCQ 'd0;
else if ((((stg1_wr_rd_cnt == 'd22) && ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(complex_rdlvl_int_ref_req && (init_state_r == INIT_REFRESH_WAIT) && (cnt_cmd_r == 'd127)))) ||
complex_victim_inc || (complex_sample_cnt_inc_r2 && ~complex_victim_inc) || wr_victim_inc || reset_rd_addr_r1)) begin
// During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22
if ((complex_row_cnt < DQ_PER_DQS*2-1) && ~stg1_wr_done)
complex_row_cnt <= #TCQ complex_row_cnt + 1;
// During reads row count requires different conditions for increments
else if (stg1_wr_done) begin
if (reset_rd_addr_r1)
complex_row_cnt <= #TCQ 'd0;
// When looping multiple times in the same victim bit in a byte
else if (complex_sample_cnt_inc_r2 && ~complex_victim_inc)
complex_row_cnt <= #TCQ rd_victim_sel*2;
// When looping through victim bits within a byte
else if (complex_row_cnt < DQ_PER_DQS*2-1)
complex_row_cnt <= #TCQ complex_row_cnt + 1;
// When the number of samples is done and tap is incremented within a byte
else
complex_row_cnt <= #TCQ 'd0;
end
end
end else begin: row_cnt_victim_fixed
always @(posedge clk)
if (rst || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done)
complex_row_cnt <= #TCQ 'd0;
else if ((stg1_wr_rd_cnt == 'd22) && (((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) && (complex_wait_cnt == 'd15)) || complex_rdlvl_int_ref_req))
complex_row_cnt <= #TCQ 'd1;
else
complex_row_cnt <= #TCQ 'd0;
end
endgenerate
//row count
always @(posedge clk)
if (rst || (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) || ~rdlvl_stg1_done_r1 || prbs_rdlvl_done_pulse || complex_byte_rd_done)
complex_row_cnt_ocal <= #TCQ 'd0;
else if ( prbs_rdlvl_done && (((stg1_wr_rd_cnt == 'd30) && (init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE)) ||
(complex_sample_cnt_inc_r2) || wr_victim_inc)) begin
// During writes row count is incremented with every wr_victim_in and stg1_wr_rd_cnt=='d22
if (complex_row_cnt_ocal < COMPLEX_ROW_CNT_BYTE-1) begin
complex_row_cnt_ocal <= #TCQ complex_row_cnt_ocal + 1;
end
end
always @(posedge clk)
if (rst)
complex_odt_ext <= #TCQ 1'b0;
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE))
complex_odt_ext <= #TCQ 1'b0;
else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd1) && (init_state_r == INIT_RDLVL_STG1_WRITE))
complex_odt_ext <= #TCQ 1'b1;
always @(posedge clk)
if (rst || (wr_victim_inc && (complex_row_cnt == DQ_PER_DQS*2-1))) begin
wr_victim_sel <= #TCQ 'd0;
end else if (rdlvl_stg1_done_r1 && wr_victim_inc) begin
wr_victim_sel <= #TCQ wr_victim_sel + 1;
end
always @(posedge clk)
if (rst) begin
wr_victim_sel_ocal <= #TCQ 'd0;
end else if (wr_victim_inc && (complex_row_cnt_ocal == COMPLEX_ROW_CNT_BYTE-1)) begin
wr_victim_sel_ocal <= #TCQ 'd0;
end else if (prbs_rdlvl_done && wr_victim_inc) begin
wr_victim_sel_ocal <= #TCQ wr_victim_sel_ocal + 1;
end
always @(posedge clk)
if (rst) begin
victim_sel <= #TCQ 'd0;
victim_byte_cnt <= #TCQ 'd0;
end else if ((~stg1_wr_done && ~prbs_rdlvl_done) || (prbs_rdlvl_done && ~complex_wr_done)) begin
victim_sel <= #TCQ prbs_rdlvl_done? wr_victim_sel_ocal: wr_victim_sel;
victim_byte_cnt <= #TCQ 'd0;
end else begin
if( (init_state_r == INIT_RDLVL_COMPLEX_ACT) || reset_rd_addr)
victim_sel <= #TCQ prbs_rdlvl_done? complex_ocal_rd_victim_sel:rd_victim_sel;
victim_byte_cnt <= #TCQ 'd0;
end
generate
if (FIXED_VICTIM == "FALSE") begin: wr_done_victim_rotate
always @(posedge clk)
if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) ||
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
complex_byte_rd_done || prbs_rdlvl_done_pulse) begin
complex_row0_wr_done <= #TCQ 1'b0;
end else if ( rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin
complex_row0_wr_done <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst || (wr_victim_inc && (complex_row_cnt < DQ_PER_DQS*2-1) && ~prbs_rdlvl_done) ||
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
complex_byte_rd_done || prbs_rdlvl_done_pulse) begin
complex_row1_wr_done <= #TCQ 1'b0;
end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin
complex_row1_wr_done <= #TCQ 1'b1;
end
end else begin: wr_done_victim_fixed
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse ||
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
complex_byte_rd_done ) begin
complex_row0_wr_done <= #TCQ 1'b0;
end else if (rdlvl_stg1_done_r1 && (stg1_wr_rd_cnt == 9'd2)) begin
complex_row0_wr_done <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse ||
(wr_victim_inc && prbs_rdlvl_done && complex_row_cnt_ocal <COMPLEX_ROW_CNT_BYTE-1) ||
complex_byte_rd_done ) begin
complex_row1_wr_done <= #TCQ 1'b0;
end else if (complex_row0_wr_done && (stg1_wr_rd_cnt == 9'd2)) begin
complex_row1_wr_done <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse)
complex_row0_rd_done <= #TCQ 1'b0;
else if (complex_sample_cnt_inc)
complex_row0_rd_done <= #TCQ 1'b0;
else if ( (prbs_rdlvl_start || complex_oclkdelay_calib_start_int) && (stg1_wr_rd_cnt == 9'd2) && complex_row0_wr_done && complex_row1_wr_done)
complex_row0_rd_done <= #TCQ 1'b1;
always @(posedge clk)
complex_row0_rd_done_r1 <= #TCQ complex_row0_rd_done;
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse)
complex_row1_rd_done <= #TCQ 1'b0;
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) || (init_state_r == INIT_PRECHARGE))
complex_row1_rd_done <= #TCQ 1'b0;
else if (complex_row0_rd_done && (stg1_wr_rd_cnt == 9'd2))
complex_row1_rd_done <= #TCQ 1'b1;
always @(posedge clk)
complex_row1_rd_done_r1 <= #TCQ complex_row1_rd_done;
//calculate row rd num for complex_oclkdelay_calib
//once it reached to 8
always @ (posedge clk)
if (rst || prbs_rdlvl_done_pulse) complex_row1_rd_cnt <= #TCQ 'd0;
else
complex_row1_rd_cnt <= #TCQ (complex_row1_rd_done & ~complex_row1_rd_done_r1) ?
((complex_row1_rd_cnt == (COMPLEX_RD-1))? 0:complex_row1_rd_cnt + 'd1)
: complex_row1_rd_cnt;
//For write, reset rd_done for the byte
always @ (posedge clk) begin
if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE) || prbs_rdlvl_done_pulse)
complex_byte_rd_done <= #TCQ 'b0;
else if (prbs_rdlvl_done && (complex_row1_rd_cnt == (COMPLEX_RD-1)) && (complex_row1_rd_done & ~complex_row1_rd_done_r1))
complex_byte_rd_done <= #TCQ 'b1;
end
always @ (posedge clk) begin
complex_byte_rd_done_r1 <= #TCQ complex_byte_rd_done;
complex_ocal_num_samples_inc <= #TCQ (complex_byte_rd_done & ~complex_byte_rd_done_r1);
end
generate
if (RANKS < 2) begin: one_rank_complex
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) ||
(complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse )
complex_wr_done <= #TCQ 1'b0;
else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
complex_wr_done <= #TCQ 1'b1;
else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
complex_wr_done <= #TCQ 1'b1;
end else begin: dual_rank_complex
always @(posedge clk)
if ((init_state_r == INIT_IDLE) || rdlvl_last_byte_done || ( complex_oclkdelay_calib_done && (init_state_r == INIT_RDLVL_STG1_WRITE )) ||
(rdlvl_stg1_rank_done ) || (complex_byte_rd_done && init_state_r == INIT_RDLVL_COMPLEX_ACT) || prbs_rdlvl_done_pulse )
complex_wr_done <= #TCQ 1'b0;
else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
complex_wr_done <= #TCQ 1'b1;
else if ((init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) && complex_row1_wr_done && (complex_wait_cnt == 'd13))
complex_wr_done <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst)
complex_wait_cnt <= #TCQ 'd0;
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_WAIT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT_WAIT) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && complex_wait_cnt < 'd15)
complex_wait_cnt <= #TCQ complex_wait_cnt + 1;
else
complex_wait_cnt <= #TCQ 'd0;
always @(posedge clk)
if (rst) begin
complex_num_reads <= #TCQ 'd1;
end else if ((((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd14)) ||
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && ext_int_ref_req && (cnt_cmd_r == 'd127))) &&
~complex_row0_rd_done) begin
if (stg1_wr_rd_cnt > 'd85) begin
if (complex_num_reads < 'd6)
complex_num_reads <= #TCQ complex_num_reads + 1;
else
complex_num_reads <= #TCQ 'd1;
// Initila value for VCCAUX pattern is 3, 7, and 12
end else if (stg1_wr_rd_cnt > 'd73) begin
if (stg1_wr_rd_cnt == 'd85)
complex_num_reads <= #TCQ 'd3;
else if (complex_num_reads < 'd5)
complex_num_reads <= #TCQ complex_num_reads + 1;
end else if (stg1_wr_rd_cnt > 'd39) begin
if (stg1_wr_rd_cnt == 'd73)
complex_num_reads <= #TCQ 'd7;
else if (complex_num_reads < 'd10)
complex_num_reads <= #TCQ complex_num_reads + 1;
end else begin
if (stg1_wr_rd_cnt == 'd39)
complex_num_reads <= #TCQ 'd12;
else if (complex_num_reads < 'd14)
complex_num_reads <= #TCQ complex_num_reads + 1;
end
// Initialize to 1 at the start of reads or after precharge and activate
end else if ((((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)) && ~ext_int_ref_req) ||
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) && (stg1_wr_rd_cnt == 'd22)))
complex_num_reads <= #TCQ 'd1;
always @(posedge clk)
if (rst)
complex_num_reads_dec <= #TCQ 'd1;
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))
complex_num_reads_dec <= #TCQ complex_num_reads;
else if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (complex_num_reads_dec > 'd0))
complex_num_reads_dec <= #TCQ complex_num_reads_dec - 1;
always @(posedge clk)
if (rst)
complex_address <= #TCQ 'd0;
else if (((init_state_r == INIT_RDLVL_COMPLEX_READ_WAIT) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ_WAIT)) ||
((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (init_state_r1 != INIT_OCAL_COMPLEX_WRITE_WAIT)))
complex_address <= #TCQ phy_address[COL_WIDTH-1:0];
always @ (posedge clk)
if (rst)
complex_oclkdelay_calib_start_int <= #TCQ 'b0;
else if ((init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE_PREWAIT) && prbs_last_byte_done_r) // changed for new algo 3/26
complex_oclkdelay_calib_start_int <= #TCQ 'b1;
always @(posedge clk) begin
complex_oclkdelay_calib_start_r1 <= #TCQ complex_oclkdelay_calib_start_int;
complex_oclkdelay_calib_start_r2 <= #TCQ complex_oclkdelay_calib_start_r1;
end
always @ (posedge clk)
if (rst)
complex_oclkdelay_calib_start <= #TCQ 'b0;
else if (complex_oclkdelay_calib_start_int && (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT) && prbs_rdlvl_done) // changed for new algo 3/26
complex_oclkdelay_calib_start <= #TCQ 'b1;
//packet fragmentation for complex oclkdealy calib write
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse) begin
complex_num_writes <= #TCQ 'd1;
end else if ((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd14) && ~complex_row0_wr_done) begin
if (stg1_wr_rd_cnt > 'd85) begin
if (complex_num_writes < 'd6)
complex_num_writes <= #TCQ complex_num_writes + 1;
else
complex_num_writes <= #TCQ 'd1;
// Initila value for VCCAUX pattern is 3, 7, and 12
end else if (stg1_wr_rd_cnt > 'd73) begin
if (stg1_wr_rd_cnt == 'd85)
complex_num_writes <= #TCQ 'd3;
else if (complex_num_writes < 'd5)
complex_num_writes <= #TCQ complex_num_writes + 1;
end else if (stg1_wr_rd_cnt > 'd39) begin
if (stg1_wr_rd_cnt == 'd73)
complex_num_writes <= #TCQ 'd7;
else if (complex_num_writes < 'd10)
complex_num_writes <= #TCQ complex_num_writes + 1;
end else begin
if (stg1_wr_rd_cnt == 'd39)
complex_num_writes <= #TCQ 'd12;
else if (complex_num_writes < 'd14)
complex_num_writes <= #TCQ complex_num_writes + 1;
end
// Initialize to 1 at the start of write or after precharge and activate
end else if ((init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT) && complex_row0_wr_done)
complex_num_writes <= #TCQ 'd30;
else if (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)
complex_num_writes <= #TCQ 'd1;
always @(posedge clk)
if (rst || prbs_rdlvl_done_pulse)
complex_num_writes_dec <= #TCQ 'd1;
else if (((init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) && (complex_wait_cnt == 'd15) && ~complex_row0_rd_done) ||
((init_state_r == INIT_RDLVL_STG1_WRITE_READ) || (init_state_r == INIT_RDLVL_COMPLEX_ACT_WAIT)))
complex_num_writes_dec <= #TCQ complex_num_writes;
else if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (complex_num_writes_dec > 'd0))
complex_num_writes_dec <= #TCQ complex_num_writes_dec - 1;
always @(posedge clk)
if (rst)
complex_sample_cnt_inc_ocal <= #TCQ 1'b0;
else if ((stg1_wr_rd_cnt == 9'd1) && complex_byte_rd_done && prbs_rdlvl_done)
complex_sample_cnt_inc_ocal <= #TCQ 1'b1;
else
complex_sample_cnt_inc_ocal <= #TCQ 1'b0;
always @(posedge clk)
if (rst)
complex_sample_cnt_inc <= #TCQ 1'b0;
else if ((stg1_wr_rd_cnt == 9'd1) && complex_row1_rd_done)
complex_sample_cnt_inc <= #TCQ 1'b1;
else
complex_sample_cnt_inc <= #TCQ 1'b0;
always @(posedge clk) begin
complex_sample_cnt_inc_r1 <= #TCQ complex_sample_cnt_inc;
complex_sample_cnt_inc_r2 <= #TCQ complex_sample_cnt_inc_r1;
end
//complex refresh req
always @ (posedge clk) begin
if(rst || (init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(prbs_rdlvl_done && (init_state_r == INIT_RDLVL_COMPLEX_ACT)) )
complex_ocal_ref_done <= #TCQ 1'b1;
else if (init_state_r == INIT_RDLVL_STG1_WRITE)
complex_ocal_ref_done <= #TCQ 1'b0;
end
//complex ocal odt extention
always @(posedge clk)
if (rst)
complex_ocal_odt_ext <= #TCQ 1'b0;
else if (((init_state_r == INIT_PRECHARGE_PREWAIT) && cnt_cmd_done_m7_r) || (init_state_r == INIT_OCLKDELAY_READ_WAIT))
complex_ocal_odt_ext <= #TCQ 1'b0;
else if ((init_state_r == INIT_OCAL_CENTER_WRITE) || (init_state_r == INIT_OCAL_CENTER_WRITE_WAIT))
complex_ocal_odt_ext <= #TCQ 1'b1;
// OCLKDELAY calibration requires multiple writes because
// write can be up to 2 cycles early since OCLKDELAY tap
// can go down to 0
always @(posedge clk)
if (rst || (init_state_r == INIT_OCLKDELAY_WRITE_WAIT) ||
(oclk_wr_cnt == 4'd0))
oclk_wr_cnt <= #TCQ NUM_STG1_WR_RD;
else if ((init_state_r == INIT_OCLKDELAY_WRITE) &&
new_burst_r && ~phy_data_full)
oclk_wr_cnt <= #TCQ oclk_wr_cnt - 1;
// Write calibration requires multiple writes because
// write can be up to 2 cycles early due to new write
// leveling algorithm to avoid late writes
always @(posedge clk)
if (rst || (init_state_r == INIT_WRCAL_WRITE_READ) ||
(wrcal_wr_cnt == 4'd0))
wrcal_wr_cnt <= #TCQ NUM_STG1_WR_RD;
else if ((init_state_r == INIT_WRCAL_WRITE) &&
new_burst_r && ~phy_data_full)
wrcal_wr_cnt <= #TCQ wrcal_wr_cnt - 1;
generate
if(nCK_PER_CLK == 4) begin:back_to_back_reads_4_1
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 3'b000;
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
num_reads <= #TCQ 3'b011;
end else if(nCK_PER_CLK == 2) begin: back_to_back_reads_2_1
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 3'b000;
else if ((num_reads > 3'b000) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
num_reads <= #TCQ 3'b111;
end
endgenerate
// back-to-back reads during write calibration
always @(posedge clk)
if (rst ||(init_state_r == INIT_WRCAL_READ_WAIT))
wrcal_reads <= #TCQ 2'b00;
else if ((wrcal_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))
wrcal_reads <= #TCQ wrcal_reads - 1;
else if ((init_state_r == INIT_WRCAL_MULT_READS) || phy_ctl_full ||
phy_cmd_full && new_burst_r)
wrcal_reads <= #TCQ 'd255;
// determine how often to issue row command during read leveling writes
// and reads
always @(posedge clk)
if (rdlvl_wr_rd) begin
// 2:1 mode - every other command issued is a data command
// 4:1 mode - every command issued is a data command
if (nCK_PER_CLK == 2) begin
if (!phy_ctl_full)
new_burst_r <= #TCQ ~new_burst_r;
end else
new_burst_r <= #TCQ 1'b1;
end else
new_burst_r <= #TCQ 1'b1;
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
// simultaneous with the corresponding command/address for CWL = 5,6
always @(posedge clk) begin
rdlvl_wr_r <= #TCQ rdlvl_wr;
calib_wrdata_en <= #TCQ phy_wrdata_en;
end
always @(posedge clk) begin
if (rst || wrcal_done)
extend_cal_pat <= #TCQ 1'b0;
else if (temp_lmr_done && (PRE_REV3ES == "ON"))
extend_cal_pat <= #TCQ 1'b1;
end
generate
if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4
// Write data enable asserted for one DIV4 clock cycle
// Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.
always @(*) begin
if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
end
end else begin: wrdqen_div2 // block: wrdqen_div4
always @(*)
if((rdlvl_wr & ~phy_ctl_full & new_burst_r & ~phy_data_full)
| phy_wrdata_en_r1)
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
always @(posedge clk)
phy_wrdata_en_r1 <= #TCQ rdlvl_wr & ~phy_ctl_full & new_burst_r
& ~phy_data_full;
always @(posedge clk) begin
if (!phy_wrdata_en & first_rdlvl_pat_r)
wrdata_pat_cnt <= #TCQ 2'b00;
else if (wrdata_pat_cnt == 2'b11)
wrdata_pat_cnt <= #TCQ 2'b10;
else
wrdata_pat_cnt <= #TCQ wrdata_pat_cnt + 1;
end
always @(posedge clk) begin
if (!phy_wrdata_en & first_wrcal_pat_r)
wrcal_pat_cnt <= #TCQ 2'b00;
else if (extend_cal_pat && (wrcal_pat_cnt == 2'b01))
wrcal_pat_cnt <= #TCQ 2'b00;
else if (wrcal_pat_cnt == 2'b11)
wrcal_pat_cnt <= #TCQ 2'b10;
else
wrcal_pat_cnt <= #TCQ wrcal_pat_cnt + 1;
end
end
endgenerate
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
// is used during read-leveling to determine read latency
assign phy_rddata_en = ~phy_if_empty;
// Read data valid generation for MC and User Interface after calibration is
// complete
assign phy_rddata_valid = init_complete_r1_timing ? phy_rddata_en : 1'b0;
//***************************************************************************
// Generate training data written at start of each read-leveling stage
// For every stage of read leveling, 8 words are written into memory
// The format is as follows (shown as {rise,fall}):
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
//***************************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE))
cnt_init_data_r <= #TCQ 2'b00;
else if (phy_wrdata_en)
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
else if (init_state_r == INIT_WRCAL_WRITE)
cnt_init_data_r <= #TCQ 2'b10;
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
always @(posedge clk)
if (rst || rdlvl_stg1_rank_done)
first_rdlvl_pat_r <= #TCQ 1'b1;
else if (phy_wrdata_en && (init_state_r == INIT_RDLVL_STG1_WRITE))
first_rdlvl_pat_r <= #TCQ 1'b0;
always @(posedge clk)
if (rst || wrcal_resume ||
(init_state_r == INIT_WRCAL_ACT_WAIT))
first_wrcal_pat_r <= #TCQ 1'b1;
else if (phy_wrdata_en && (init_state_r == INIT_WRCAL_WRITE))
first_wrcal_pat_r <= #TCQ 1'b0;
generate
if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 2)) begin: wrdq_div2_2to1_rdlvl_first
always @(posedge clk)
if (~oclkdelay_calib_done)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}}};
else if (!rdlvl_stg1_done) begin
// The 16 words for stage 1 write data in 2:1 mode is written
// over 4 consecutive controller clock cycles. Note that write
// data follows phy_wrdata_en by one clock cycle
case (wrdata_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},
{DQ_WIDTH/4{4'h9}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
endcase
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
phy_wrdata <= #TCQ prbs_o;
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
end else if (!wrcal_done) begin
case (wrcal_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h5}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h4}}};
end
endcase
end
end else if ((CLK_PERIOD/nCK_PER_CLK > 2500) && (nCK_PER_CLK == 4)) begin: wrdq_div2_4to1_rdlvl_first
always @(posedge clk)
if (~oclkdelay_calib_done)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
else if (!rdlvl_stg1_done && ~phy_data_full)
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
if (first_rdlvl_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
else
// For all others, change the first two words written in order
// to differentiate the "early write" and "on-time write"
// readback patterns during read leveling
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
else if (~(prbs_rdlvl_done || prbs_last_byte_done_r) && ~phy_data_full)
phy_wrdata <= #TCQ prbs_o;
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
else if (!wrcal_done)
if (first_wrcal_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (nCK_PER_CLK == 4) begin: wrdq_div1_4to1_wrcal_first
always @(posedge clk)
if ((~oclkdelay_calib_done) && (DRAM_TYPE == "DDR3"))
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},{DQ_WIDTH/4{4'h0}}};
else if ((!wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
if (extend_cal_pat)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else if (first_wrcal_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
else
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (!rdlvl_stg1_done && ~phy_data_full) begin
// write different sequence for very
// first write to memory only. Used to help us differentiate
// if the writes are "early" or "on-time" during read leveling
if (first_rdlvl_pat_r)
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},{DQ_WIDTH/4{4'h9}}};
else
// For all others, change the first two words written in order
// to differentiate the "early write" and "on-time write"
// readback patterns during read leveling
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},{DQ_WIDTH/4{4'hC}},
{DQ_WIDTH/4{4'hE}},{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},{DQ_WIDTH/4{4'hB}}};
end else if (!prbs_rdlvl_done && ~phy_data_full)
phy_wrdata <= #TCQ prbs_o;
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[8*8-1:7*8]}},{DQ_WIDTH/8{prbs_o[7*8-1:6*8]}},
{DQ_WIDTH/8{prbs_o[6*8-1:5*8]}},{DQ_WIDTH/8{prbs_o[5*8-1:4*8]}},
{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
else if (!complex_oclkdelay_calib_done && ~phy_data_full)
phy_wrdata <= #TCQ prbs_o;
end else begin: wrdq_div1_2to1_wrcal_first
always @(posedge clk)
if ((~oclkdelay_calib_done)&& (DRAM_TYPE == "DDR3"))
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}},
{DQ_WIDTH/4{4'h0}}};
else if ((!wrcal_done) && (DRAM_TYPE == "DDR3"))begin
case (wrcal_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},
{DQ_WIDTH/4{4'hF}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h5}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h8}},
{DQ_WIDTH/4{4'hD}},
{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h4}}};
end
endcase
end else if (!rdlvl_stg1_done) begin
// The 16 words for stage 1 write data in 2:1 mode is written
// over 4 consecutive controller clock cycles. Note that write
// data follows phy_wrdata_en by one clock cycle
case (wrdata_pat_cnt)
2'b00: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h3}},
{DQ_WIDTH/4{4'h9}}};
end
2'b01: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
2'b10: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'hE}},
{DQ_WIDTH/4{4'h7}},
{DQ_WIDTH/4{4'h1}},
{DQ_WIDTH/4{4'hB}}};
end
2'b11: begin
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h4}},
{DQ_WIDTH/4{4'h2}},
{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hC}}};
end
endcase
end else if (!prbs_rdlvl_done && ~phy_data_full) begin
phy_wrdata <= #TCQ prbs_o;
// prbs_o is 8-bits wide hence {DQ_WIDTH/8{prbs_o}} results in
// prbs_o being concatenated 8 times resulting in DQ_WIDTH
/*phy_wrdata <= #TCQ {{DQ_WIDTH/8{prbs_o[4*8-1:3*8]}},
{DQ_WIDTH/8{prbs_o[3*8-1:2*8]}},
{DQ_WIDTH/8{prbs_o[2*8-1:8]}},
{DQ_WIDTH/8{prbs_o[8-1:0]}}};*/
end else if (!complex_oclkdelay_calib_done && ~phy_data_full) begin
phy_wrdata <= #TCQ prbs_o;
end
end
endgenerate
//***************************************************************************
// Memory control/address
//***************************************************************************
// Phases [2] and [3] are always deasserted for 4:1 mode
generate
if (nCK_PER_CLK == 4) begin: gen_div4_ca_tieoff
always @(posedge clk) begin
phy_ras_n[3:2] <= #TCQ 3'b11;
phy_cas_n[3:2] <= #TCQ 3'b11;
phy_we_n[3:2] <= #TCQ 3'b11;
end
end
endgenerate
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
// verilint STARC-2.7.3.3b off
generate
if (!(CWL_M % 2)) begin: even_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end else begin: odd_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b0;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b0;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_MPR_RDEN) ||
(init_state_r == INIT_MPR_DISABLE) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b0;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end
endgenerate
// verilint STARC-2.7.3.3b on
// Assign calib_cmd for the command field in PHY_Ctl_Word
always @(posedge clk) begin
if (wr_level_dqs_asrt) begin
// Request to toggle DQS during write leveling
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) begin // odd write latency
calib_data_offset_0 <= #TCQ CWL_M + 3;
calib_data_offset_1 <= #TCQ CWL_M + 3;
calib_data_offset_2 <= #TCQ CWL_M + 3;
calib_cas_slot <= #TCQ 2'b01;
end else begin // even write latency
calib_data_offset_0 <= #TCQ CWL_M + 2;
calib_data_offset_1 <= #TCQ CWL_M + 2;
calib_data_offset_2 <= #TCQ CWL_M + 2;
calib_cas_slot <= #TCQ 2'b00;
end
end else if (rdlvl_wr && new_burst_r) begin
// Write Command
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) begin // odd write latency
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 3 : CWL_M - 1;
calib_cas_slot <= #TCQ 2'b01;
end else begin // even write latency
calib_data_offset_0 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_data_offset_1 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_data_offset_2 <= #TCQ (nCK_PER_CLK == 4) ? CWL_M + 2 : CWL_M - 2 ;
calib_cas_slot <= #TCQ 2'b00;
end
end else if (rdlvl_rd && new_burst_r) begin
// Read Command
calib_cmd <= #TCQ 3'b011;
if (CWL_M % 2)
calib_cas_slot <= #TCQ 2'b01;
else
calib_cas_slot <= #TCQ 2'b00;
if (~pi_calib_done_r1) begin
calib_data_offset_0 <= #TCQ 6'd0;
calib_data_offset_1 <= #TCQ 6'd0;
calib_data_offset_2 <= #TCQ 6'd0;
end else if (~pi_dqs_found_done_r1) begin
calib_data_offset_0 <= #TCQ rd_data_offset_0;
calib_data_offset_1 <= #TCQ rd_data_offset_1;
calib_data_offset_2 <= #TCQ rd_data_offset_2;
end else begin
calib_data_offset_0 <= #TCQ rd_data_offset_ranks_0[6*chip_cnt_r+:6];
calib_data_offset_1 <= #TCQ rd_data_offset_ranks_1[6*chip_cnt_r+:6];
calib_data_offset_2 <= #TCQ rd_data_offset_ranks_2[6*chip_cnt_r+:6];
end
end else begin
// Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,
// Active, Refresh
calib_cmd <= #TCQ 3'b100;
calib_data_offset_0 <= #TCQ 6'd0;
calib_data_offset_1 <= #TCQ 6'd0;
calib_data_offset_2 <= #TCQ 6'd0;
if (CWL_M % 2)
calib_cas_slot <= #TCQ 2'b01;
else
calib_cas_slot <= #TCQ 2'b00;
end
end
// Write Enable to PHY_Control FIFO always asserted
// No danger of this FIFO being Full with 4:1 sync clock ratio
// This is also the write enable to the command OUT_FIFO
always @(posedge clk) begin
if (rst) begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ 2'b00;
end else if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full )) begin
calib_ctl_wren <= #TCQ 1'b1;
calib_cmd_wren <= #TCQ 1'b1;
calib_seq <= #TCQ calib_seq + 1;
end else begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ calib_seq;
end
end
generate
genvar rnk_i;
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
always @(posedge clk) begin
if (rst) begin
mr2_r[rnk_i] <= #TCQ 2'b00;
mr1_r[rnk_i] <= #TCQ 3'b000;
end else begin
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
end
end
end
endgenerate
// ODT assignment based on slot config and slot present
// For single slot systems slot_1_present input will be ignored
// Assuming component interfaces to be single slot systems
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @(posedge clk) begin
if (rst) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
end else begin
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// Single slot configuration with quad rank
// Assuming same behavior as single slot dual rank for now
// DDR2 does not have quad rank parts
4'b1111: begin
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 RTT_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 RTT_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
end
// Single slot configuration with single rank
4'b1000: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
end else begin
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
((cnt_init_mr_r == 2'd0) || (USE_ODT_PORT == 1)))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 RTT_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 RTT_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Single slot configuration with dual rank
4'b1100: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
endcase
end
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (posedge clk) begin
if (rst) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
end else begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// Two slot configuration, one slot present, single rank
4'b10_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b00_10: begin
//Rank1 ODT enabled
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one slot present, dual rank
4'b00_11: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b11_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one rank per slot
4'b10_10: begin
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010; //bit0 for rank0
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001; //bit0 for rank0
end
end else begin
if((init_state_r == INIT_WRLVL_WAIT) ||
(init_next_state == INIT_RDLVL_STG1_WRITE) ||
(init_next_state == INIT_WRCAL_WRITE) ||
(init_next_state == INIT_OCAL_CENTER_WRITE) ||
(init_next_state == INIT_OCLKDELAY_WRITE))
phy_tmp_odt_r <= #TCQ 4'b0011; // bit0 for rank0/1 (write)
else if ((init_next_state == INIT_PI_PHASELOCK_READS) ||
(init_next_state == INIT_MPR_READ) ||
(init_next_state == INIT_RDLVL_STG1_READ) ||
(init_next_state == INIT_RDLVL_COMPLEX_READ) ||
(init_next_state == INIT_RDLVL_STG2_READ) ||
(init_next_state == INIT_OCLKDELAY_READ) ||
(init_next_state == INIT_WRCAL_READ) ||
(init_next_state == INIT_WRCAL_MULT_READS))
phy_tmp_odt_r <= #TCQ 4'b0010; // bit0 for rank1 (rank 0 rd)
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_WR == "60") ? 3'b001 :
(RTT_WR == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
end
end
// Two Slots - One slot with dual rank and other with single rank
4'b10_11: begin
//Rank3 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[1] <= #TCQ 3'b000;
end
//Slot1 Rank1 or Rank3 is being written
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0011;
//Slot0 Rank0 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - One slot with dual rank and other with single rank
4'b11_10: begin
//Rank2 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
(RTT_NOM2 == "40") ? 3'b011:
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011:
3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r <=
#TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100; // rank 2 ODT asserted
end
end else begin
if (// wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
end else begin
phy_tmp_odt_r <=
#TCQ 4'b0101;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - two ranks per slot
4'b11_11: begin
//Rank2 Rtt_NOM
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
(RTT_NOM2 == "40") ? 3'b011 :
3'b000;
//Rank3 Rtt_NOM
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
(RTT_NOM3 == "40") ? 3'b011 :
3'b000;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM after write leveling completes
tmp_mr1_r[1] <= #TCQ 3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM after write leveling completes
tmp_mr1_r[0] <= #TCQ 3'b000;
end
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
//Slot1 Rank1 or Rank3 is being written
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
//Slot0 Rank0 or Rank2 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1001;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))begin
//Slot1 Rank1 or Rank3 is being read
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
//Slot0 Rank0 or Rank2 is being read
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1000;
end
end
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b1111;
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
3'b000;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "40") ? 3'b011 :
(RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "60") ? 3'b010 :
3'b000;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ (RTT_NOM_int == "60") ? 3'b001 :
(RTT_NOM_int == "120") ? 3'b010 :
(RTT_NOM_int == "20") ? 3'b100 :
(RTT_NOM_int == "30") ? 3'b101 :
(RTT_NOM_int == "40") ? 3'b011 :
3'b000;
end
end
endcase
end
end
end
endgenerate
// PHY only supports two ranks.
// calib_aux_out[0] is CKE for rank 0 and calib_aux_out[1] is ODT for rank 0
// calib_aux_out[2] is CKE for rank 1 and calib_aux_out[3] is ODT for rank 1
generate
if(CKE_ODT_AUX == "FALSE") begin
if ((nSLOTS == 1) && (RANKS < 2)) begin
always @(posedge clk)
if (rst) begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt ) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
complex_odt_ext ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
complex_ocal_odt_ext ||
(init_state_r == INIT_OCLKDELAY_WRITE)||
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
// Quad rank in a single slot
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))/* ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)*/) && (DRAM_TYPE == "DDR3")) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt)||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
complex_odt_ext ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
complex_ocal_odt_ext ||
(init_state_r == INIT_OCLKDELAY_WRITE)||
(init_state_r == INIT_OCLKDELAY_WRITE_WAIT))) begin
// Dual rank in a single slot
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
always @(posedge clk)
if (rst)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}} ;
calib_odt <= 2'b00 ;
end else begin
if (cnt_pwron_cke_done_r /*&& ~cnt_pwron_cke_done_r1*/)begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b1}};
end else begin
calib_cke <= #TCQ {nCK_PER_CLK{1'b0}};
end
if (((DRAM_TYPE == "DDR2") && (RTT_NOM == "DISABLED")) ||
((DRAM_TYPE == "DDR3") &&
(RTT_NOM == "DISABLED") && (RTT_WR == "OFF"))) begin
calib_odt[0] <= #TCQ 1'b0;
calib_odt[1] <= #TCQ 1'b0;
end else if (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE)) begin
// Quad rank in a single slot
if (nCK_PER_CLK == 2) begin
calib_odt[0]
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
calib_odt[1]
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end
// Turn on for idle rank during read if dynamic ODT is enabled in DDR3
end else if(((DRAM_TYPE == "DDR3") && (RTT_WR != "OFF")) &&
((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_MPR_READ) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_OCLKDELAY_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_MULT_READS))) begin
if (nCK_PER_CLK == 2) begin
calib_odt[0]
<= #TCQ (!calib_odt[0]) ? phy_tmp_odt_r[0] : 1'b0;
calib_odt[1]
<= #TCQ (!calib_odt[1]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_odt[0] <= #TCQ phy_tmp_odt_r[0];
calib_odt[1] <= #TCQ phy_tmp_odt_r[1];
end
// disable well before next command and before disabling write leveling
end else if(cnt_cmd_done_m7_r ||
(init_state_r == INIT_WRLVL_WAIT && ~wrlvl_odt))
calib_odt <= #TCQ 2'b00;
end
end
end else begin//USE AUX OUTPUT for routing CKE and ODT.
if ((nSLOTS == 1) && (RANKS < 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Quad rank in a single slot
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Dual rank in a single slot
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS == 2)) begin
always @(posedge clk)
if (rst)
calib_aux_out <= #TCQ 4'b0000;
else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out[0] <= #TCQ 1'b1;
calib_aux_out[2] <= #TCQ 1'b1;
end else begin
calib_aux_out[0] <= #TCQ 1'b0;
calib_aux_out[2] <= #TCQ 1'b0;
end
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done_r2 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_OCAL_COMPLEX_WRITE_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_WRITE))) begin
// Quad rank in a single slot
if (nCK_PER_CLK == 2) begin
calib_aux_out[1]
<= #TCQ (!calib_aux_out[1]) ? phy_tmp_odt_r[0] : 1'b0;
calib_aux_out[3]
<= #TCQ (!calib_aux_out[3]) ? phy_tmp_odt_r[1] : 1'b0;
end else begin
calib_aux_out[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out[3] <= #TCQ phy_tmp_odt_r[1];
end
end else begin
calib_aux_out[1] <= #TCQ 1'b0;
calib_aux_out[3] <= #TCQ 1'b0;
end
end
end
end
endgenerate
//*****************************************************************
// memory address during init
//*****************************************************************
always @(posedge clk)
phy_data_full_r <= #TCQ phy_data_full;
// verilint STARC-2.7.3.3b off
always @(*)begin
// Bus 0 for address/bank never used
address_w = 'b0;
bank_w = 'b0;
if ((init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_COMPLEX_PRECHARGE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_DDR2_PRECHARGE)) begin
// Set A10=1 for ZQ long calibration or Precharge All
address_w = 'b0;
address_w[10] = 1'b1;
bank_w = 'b0;
end else if (init_state_r == INIT_WRLVL_START) begin
// Enable wrlvl in MR1
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
address_w[7] = 1'b1;
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
// Finished with write leveling, disable wrlvl in MR1
// For single rank disable Rtt_Nom
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
// Set RTT_WR in MR2 after write leveling disabled
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end else if (init_state_r == INIT_MPR_READ) begin
address_w = 'b0;
bank_w = 'b0;
end else if (init_state_r == INIT_MPR_RDEN) begin
// Enable MPR read with LMR3 and A2=1
bank_w[BANK_WIDTH-1:0] = 'd3;
address_w = {ROW_WIDTH{1'b0}};
address_w[2] = 1'b1;
end else if (init_state_r == INIT_MPR_DISABLE) begin
// Disable MPR read with LMR3 and A2=0
bank_w[BANK_WIDTH-1:0] = 'd3;
address_w = {ROW_WIDTH{1'b0}};
end else if ((init_state_r == INIT_REG_WRITE)&
(DRAM_TYPE == "DDR3"))begin
// bank_w is assigned a 3 bit value. In some
// DDR2 cases there will be only two bank bits.
//Qualifying the condition with DDR3
bank_w = 'b0;
address_w = 'b0;
case (reg_ctrl_cnt_r)
4'h1:begin
address_w[4:0] = REG_RC1[4:0];
bank_w = REG_RC1[7:5];
end
4'h2: address_w[4:0] = REG_RC2[4:0];
4'h3: begin
address_w[4:0] = REG_RC3[4:0];
bank_w = REG_RC3[7:5];
end
4'h4: begin
address_w[4:0] = REG_RC4[4:0];
bank_w = REG_RC4[7:5];
end
4'h5: begin
address_w[4:0] = REG_RC5[4:0];
bank_w = REG_RC5[7:5];
end
4'h6: begin
address_w[4:0] = REG_RC10[4:0];
bank_w = REG_RC10[7:5];
end
4'h7: begin
address_w[4:0] = REG_RC11[4:0];
bank_w = REG_RC11[7:5];
end
default: address_w[4:0] = REG_RC0[4:0];
endcase
end else if (init_state_r == INIT_LOAD_MR) begin
// If loading mode register, look at cnt_init_mr to determine
// which MR is currently being programmed
address_w = 'b0;
bank_w = 'b0;
if(DRAM_TYPE == "DDR3")begin
if(rdlvl_stg1_done && prbs_rdlvl_done && pi_dqs_found_done)begin
// end of the calibration programming correct
// burst length
if (TEST_AL == "0") begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0; //Don't reset DLL
end else begin
// programming correct AL value
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if (TEST_AL == "CL-1")
address_w[4:3]= 2'b01; // AL="CL-1"
else
address_w[4:3]= 2'b10; // AL="CL-2"
end
end else begin
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end
INIT_CNT_MR3: begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end
INIT_CNT_MR0: begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
// fixing it to BL8 for calibration
address_w[1:0] = 2'b00;
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase
end
end else begin // DDR2
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL
end
end
INIT_CNT_MR3: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL. Repeted again
// because there is an extra state.
end
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
if(~ddr2_refresh_flag_r)begin
address_w = load_mr1[ROW_WIDTH-1:0];
end else begin // second set of lm commands
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[9:7] = 3'b111;
//OCD default state
end
end
INIT_CNT_MR0: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
// always disable odt for rank 1 and rank 3 as per SPEC
address_w[2] = 'b0;
address_w[6] = 'b0;
end
//OCD exit
end
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase
end
end else if ( ~prbs_rdlvl_done && ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ))) begin
// Writing and reading PRBS pattern for read leveling stage 1
// Need to support burst length 4 or 8. PRBS pattern will be
// written to entire row and read back from the same row repeatedly
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (((stg1_wr_rd_cnt == NUM_STG1_WR_RD) && ~rdlvl_stg1_done) || (stg1_wr_rd_cnt == 'd127) ||
((stg1_wr_rd_cnt == 'd22) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
end else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin
if ((init_state_r == INIT_RDLVL_COMPLEX_READ) && (init_state_r1 != INIT_RDLVL_COMPLEX_READ) )// ||
// ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )
address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;
else
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end
//need to add address for complex oclkdelay calib
end else if (prbs_rdlvl_done && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_COMPLEX_READ))) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if ((stg1_wr_rd_cnt == 'd127) || ((stg1_wr_rd_cnt == 'd30) && (((init_state_r1 != INIT_RDLVL_STG1_WRITE) && ~stg1_wr_done) || complex_row0_rd_done))) begin
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
end else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((stg1_wr_rd_cnt >= 9'd0) && new_burst_r && ~phy_data_full_r) begin
if ((init_state_r == INIT_RDLVL_STG1_WRITE) && (init_state_r1 != INIT_RDLVL_STG1_WRITE) )
// ((init_state_r == INIT_RDLVL_STG1_WRITE) && prbs_rdlvl_done) )
address_w[COL_WIDTH-1:0] = complex_address[COL_WIDTH-1:0] + ADDR_INC;
else
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end
end else if ((init_state_r == INIT_OCLKDELAY_WRITE) ||
(init_state_r == INIT_OCAL_CENTER_WRITE) ||
(init_state_r == INIT_OCLKDELAY_READ)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (oclk_wr_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((oclk_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_READ)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (wrcal_wr_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (phy_data_full_r || (!new_burst_r))
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0];
else if ((wrcal_wr_cnt >= 4'd0) && new_burst_r && ~phy_data_full_r)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_MULT_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ)) begin
// when writing or reading back training pattern for read leveling stage2
// need to support burst length of 4 or 8. This may mean issuing
// multiple commands to cover the entire range of addresses accessed
// during read leveling.
// Hard coding A[12] to 1 so that it will always be burst length of 8
// for DDR3. Does not have any effect on DDR2.
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
address_w[COL_WIDTH-1:0] =
{CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};
address_w[12] = 1'b1;
end else if ((init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_RDLVL_COMPLEX_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_OCAL_COMPLEX_ACT) ||
(init_state_r == INIT_OCAL_CENTER_ACT) ||
(init_state_r == INIT_OCLKDELAY_ACT)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
//if (stg1_wr_rd_cnt == 'd22)
// address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0] + 1;
//else
address_w = prbs_rdlvl_done ? CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt_ocal :
CALIB_ROW_ADD[ROW_WIDTH-1:0] + complex_row_cnt;
end else begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
end
// verilint STARC-2.7.3.3b on
// registring before sending out
generate
genvar r,s;
if ((DRAM_TYPE != "DDR3") || (CA_MIRROR != "ON")) begin: gen_no_mirror
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: div_clk_loop
always @(posedge clk) begin
phy_address[(r*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;
phy_bank[(r*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;
end
end
end else begin: gen_mirror
// Control/addressing mirroring (optional for DDR3 dual rank DIMMs)
// Mirror for the 2nd rank only. Logic needs to be enhanced to account
// for multiple slots, currently only supports one slot, 2-rank config
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_ba_div_clk_loop
for (s = 0; s < BANK_WIDTH; s = s + 1) begin: gen_ba
always @(posedge clk)
if (chip_cnt_r == 2'b00) begin
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[s];
end else begin
phy_bank[(r*BANK_WIDTH) + s] <= #TCQ bank_w[(s == 0) ? 1 : ((s == 1) ? 0 : s)];
end
end
end
for (r = 0; r < nCK_PER_CLK; r = r + 1) begin: gen_addr_div_clk_loop
for (s = 0; s < ROW_WIDTH; s = s + 1) begin: gen_addr
always @(posedge clk)
if (chip_cnt_r == 2'b00) begin
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[s];
end else begin
phy_address[(r*ROW_WIDTH) + s] <= #TCQ address_w[
(s == 3) ? 4 :
((s == 4) ? 3 :
((s == 5) ? 6 :
((s == 6) ? 5 :
((s == 7) ? 8 :
((s == 8) ? 7 : s)))))];
end
end
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Steps through the major sections of the output clock
// delay algorithm. Enabling various subblocks at the right time.
//
// Steps through each byte of the interface.
//
// Implements both the simple and complex data pattern.
//
// for each byte in interface
// begin
// Limit
// Scan - which includes DQS centering
// Precharge
// end
// set _wrlvl and _done equal to one
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_cntlr #
(parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8)
(/*AUTOARG*/
// Outputs
wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
reset_scan,
// Inputs
clk, rst, prech_done, oclkdelay_calib_start,
complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
po_counter_read_val, po_rdy, scan_done
);
localparam ONE = 1;
input clk;
input rst;
output wrlvl_final, complex_wrlvl_final;
reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
assign wrlvl_final = wrlvl_final_r;
assign complex_wrlvl_final = complex_wrlvl_final_r;
// Completed initial delay increment
output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
assign oclk_init_delay_done = 1'b1;
// Precharge done status from ddr_phy_init
input prech_done;
reg ocd_prech_req_ns, ocd_prech_req_r;
always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
output ocd_prech_req;
assign ocd_prech_req = ocd_prech_req_r;
input oclkdelay_calib_start, complex_oclkdelay_calib_start;
input lim_done;
reg lim_start_ns, lim_start_r;
always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
output lim_start;
assign lim_start = lim_start_r;
reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
output complex_oclkdelay_calib_done;
assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
output oclkdelay_calib_done;
assign oclkdelay_calib_done = oclkdelay_calib_done_r;
input phy_rddata_en;
reg prde_r1, prde_r2;
always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
always @(posedge clk) prde_r2 <= #TCQ prde_r1;
wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
assign phy_rddata_en_1 = phy_rddata_en_r1;
assign phy_rddata_en_2 = phy_rddata_en_r2;
assign phy_rddata_en_3 = phy_rddata_en_r3;
input [8:0] po_counter_read_val;
reg ocd_cntlr2stg2_dec_r;
output ocd_cntlr2stg2_dec;
assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
input po_rdy;
reg [3:0] po_rd_wait_ns, po_rd_wait_r;
always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
always @(posedge clk) byte_r <= #TCQ byte_ns;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
assign oclkdelay_calib_cnt = {1'b0, byte_r};
reg reset_scan_ns, reset_scan_r;
always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
output reset_scan;
assign reset_scan = reset_scan_r;
input scan_done;
reg [2:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
// Primary state machine.
always @(*) begin
// Default next state assignments.
byte_ns = byte_r;
complex_wrlvl_final_ns = complex_wrlvl_final_r;
lim_start_ns = lim_start_r;
oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
ocd_cntlr2stg2_dec_r = 1'b0;
po_rd_wait_ns = po_rd_wait_r;
if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
reset_scan_ns = reset_scan_r;
wrlvl_final_ns = wrlvl_final_r;
sm_ns = sm_r;
ocd_prech_req_ns= 1'b0;
if (rst == 1'b1) begin
// RESET next states
complex_oclkdelay_calib_done_ns = 1'b0;
complex_wrlvl_final_ns = 1'b0;
sm_ns = /*AK("READY")*/3'd0;
lim_start_ns = 1'b0;
oclkdelay_calib_done_ns = 1'b0;
reset_scan_ns = 1'b1;
wrlvl_final_ns = 1'b0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/3'd0: begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("LIMIT_START")*/3'd1:
sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
/*AL("LIMIT_WAIT")*/3'd2:begin
if (lim_done) begin
lim_start_ns = 1'b0;
sm_ns = /*AK("SCAN")*/3'd3;
reset_scan_ns = 1'b0;
end
end
/*AL("SCAN")*/3'd3:begin
if (scan_done) begin
reset_scan_ns = 1'b1;
sm_ns = /*AK("COMPUTE")*/3'd4;
end
end
/*AL("COMPUTE")*/3'd4:begin
sm_ns = /*AK("PRECHARGE")*/3'd5;
ocd_prech_req_ns = 1'b1;
end
/*AL("PRECHARGE")*/3'd5:begin
if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
end
/*AL("DONE")*/3'd6:begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
po_rd_wait_ns = 4'd8;
sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
end else begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("STG2_2_ZERO")*/3'd7:
if (~|po_rd_wait_r && po_rdy)
if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
else begin
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
sm_ns = /*AK("READY")*/3'd0;
oclkdelay_calib_done_ns= 1'b1;
wrlvl_final_ns = 1'b1;
if (complex_oclkdelay_calib_start) begin
complex_oclkdelay_calib_done_ns = 1'b1;
complex_wrlvl_final_ns = 1'b1;
end
end else begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
po_rd_wait_ns = 4'd8;
end
end // else: !if(|po_counter_read_val[5:0])
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v4_2_ddr_phy_ocd_cntlr
// Local Variables:
// verilog-autolabel-prefix: "3'd"
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_data.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Data comparison for both "non-complex" and "complex" data.
//
// Depending on complex_oclkdelay_calib_start, data provided on the phy_rddata
// bus is compared against a fixed ones and zeros pattern, or against data
// provided on the prob_o bus.
//
// In the case of complex data, the phy_rddata data is delayed by two
// clocks to match up with the prbs_o data.
//
// For 4:1 mode, in each fabric clock, a complete DRAM burst may be delivered.
// A DRAM burst is 8 times the width of the DQ bus. For an 8 byte DQ
// bus, 64 bytes are delivered on each clock.
//
// In 2:1 mode the DRAM burst is delivered on two fabric clocks. For
// an 8 byte bus, 32 bytes are delivered with each fabric clock.
//
// For the most part, this block does not use phy_rddata_en. It delivers
// its results and depends on downstream logic to know when its valid.
//
// phy_rddata_en is used for the PRBS compares when the last line of data
// needs to be carried over to a subsequent line.
//
// Since we work on a byte at a time, the comparison only works on
// one byte of the DQ bus at a time. The oclkdelay_calib_cnt field is used to
// select the proper 8 bytes out of both the phy_rddata and prob_o streams.
//
// Comparisons are computed for "zero" or "rise" data, and "oneeighty" or
// "fall" data. The "oneeighty" compares assumes the rising edge clock is
// landing in the oneeighty data.
//
// For the simple data, we don't need to worry about first byte or last
// byte conditions because the sampled data is taken from the middle
// of a 4 burst segment.
//
// The complex (or PRBS) data starts and stops. And we need to be
// careful about ignoring compares that might be using invalid latched
// data. The PRBS generator provides prbs_ignore_first_byte and
// prbs_ignore_last_bytes. The comparison block is procedural. It
// first compares across the entire line, then comes back and overwrites
// any byte compare results as indicated by the _ignore_ wires.
//
// The compares generate an eight bit vector, one for each byte. The
// final step is to bitwise AND this eight bit vector. We end up
// with two sets of two bits. Zero and oneeighty for the fixed pattern
// and the prbs.
//
// complex_oclkdelay_calib_start is used to
// select between the fixed and prbs compares. The final output
// is a two bit match bus.
//
// There is a deprecated feature to mask the compare for any byte.
//
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_data #
(parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64)
(/*AUTOARG*/
// Outputs
match,
// Inputs
clk, rst, complex_oclkdelay_calib_start, phy_rddata, prbs_o,
oclkdelay_calib_cnt, prbs_ignore_first_byte, prbs_ignore_last_bytes,
phy_rddata_en_1
);
localparam [7:0] OCAL_DQ_MASK = 8'b0000_0000;
input clk;
input rst;
input complex_oclkdelay_calib_start;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
reg [DQ_WIDTH-1:0] word, word_shifted;
reg [63:0] data_bytes_ns, data_bytes_r, data_bytes_r1, data_bytes_r2, prbs_bytes_ns, prbs_bytes_r;
always @(posedge clk) data_bytes_r <= #TCQ data_bytes_ns;
always @(posedge clk) data_bytes_r1 <= #TCQ data_bytes_r;
always @(posedge clk) data_bytes_r2 <= #TCQ data_bytes_r1;
always @(posedge clk) prbs_bytes_r <= #TCQ prbs_bytes_ns;
input prbs_ignore_first_byte, prbs_ignore_last_bytes;
reg prbs_ignore_first_byte_r, prbs_ignore_last_bytes_r;
always @(posedge clk) prbs_ignore_first_byte_r <= #TCQ prbs_ignore_first_byte;
always @(posedge clk) prbs_ignore_last_bytes_r <= #TCQ prbs_ignore_last_bytes;
input phy_rddata_en_1;
reg [7:0] last_byte_r;
wire [63:0] data_bytes = complex_oclkdelay_calib_start ? data_bytes_r2 : data_bytes_r;
wire [7:0] last_byte_ns;
generate if (nCK_PER_CLK == 4) begin
assign last_byte_ns = phy_rddata_en_1 ? data_bytes[63:56] : last_byte_r;
end else begin
assign last_byte_ns = phy_rddata_en_1 ? data_bytes[31:24] : last_byte_r;
end endgenerate
always @(posedge clk) last_byte_r <= #TCQ last_byte_ns;
reg second_half_ns, second_half_r;
always @(posedge clk) second_half_r <= #TCQ second_half_ns;
always @(*) begin
second_half_ns = second_half_r;
if (rst) second_half_ns = 1'b0;
else second_half_ns = phy_rddata_en_1 ^ second_half_r;
end
reg [7:0] comp0, comp180, prbs0, prbs180;
integer ii;
always @(*) begin
comp0 = 8'hff;
comp180 = 8'hff;
prbs0 = 8'hff;
prbs180 = 8'hff;
data_bytes_ns = 64'b0;
prbs_bytes_ns = 64'b0;
for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
begin
word = phy_rddata[ii*DQ_WIDTH+:DQ_WIDTH];
word_shifted = word >> oclkdelay_calib_cnt*8;
data_bytes_ns[ii*8+:8] = word_shifted[7:0];
word = prbs_o[ii*DQ_WIDTH+:DQ_WIDTH];
word_shifted = word >> oclkdelay_calib_cnt*8;
prbs_bytes_ns[ii*8+:8] = word_shifted[7:0];
comp0[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'hff : 8'h00);
comp180[ii] = data_bytes[ii*8+:8] == (ii%2 ? 8'h00 : 8'hff);
prbs0[ii] = data_bytes[ii*8+:8] == prbs_bytes_r[ii*8+:8];
end // for (ii=0; ii<2*nCK_PER_CLK; ii=ii+1)
prbs180[0] = last_byte_r == prbs_bytes_r[7:0];
for (ii=1; ii<2*nCK_PER_CLK; ii=ii+1)
prbs180[ii] = data_bytes[(ii-1)*8+:8] == prbs_bytes_r[ii*8+:8];
if (nCK_PER_CLK == 4) begin
if (prbs_ignore_last_bytes_r) begin
prbs0[7:6] = 2'b11;
prbs180[7] = 1'b1;
end
if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
end else begin
if (second_half_r) begin
if (prbs_ignore_last_bytes_r) begin
prbs0[3:2] = 2'b11;
prbs180[3] = 1'b1;
end
end else if (prbs_ignore_first_byte_r) prbs180[0] = 1'b1;
end // else: !if(nCK_PER_CLK == 4)
end // always @ (*)
wire [7:0] comp0_masked = comp0 | OCAL_DQ_MASK;
wire [7:0] comp180_masked = comp180 | OCAL_DQ_MASK;
wire [7:0] prbs0_masked = prbs0 | OCAL_DQ_MASK;
wire [7:0] prbs180_masked = prbs180 | OCAL_DQ_MASK;
output [1:0] match;
assign match = complex_oclkdelay_calib_start ? {&prbs180_masked, &prbs0_masked} : {&comp180_masked , &comp0_masked};
endmodule // mig_7series_v4_2_ddr_phy_ocd_data
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v4_2_ddr_phy_ocd_edge
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_lim #
(parameter TAPCNTRWIDTH = 7,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 9,
parameter TCQ = 100,
parameter TAPSPERKCLK = 56,
parameter TDQSS_DEGREES = 60,
parameter BYPASS_COMPLEX_OCAL = "FALSE")
(/*AUTOARG*/
// Outputs
lim2init_write_request, lim2init_prech_req, lim2poc_rdy, lim2poc_ktap_right,
lim2stg3_inc, lim2stg3_dec, lim2stg2_inc, lim2stg2_dec, lim_done,
lim2ocal_stg3_right_lim, lim2ocal_stg3_left_lim, dbg_ocd_lim,
// Inputs
clk, rst, lim_start, po_rdy, poc2lim_rise_align_taps_lead,
poc2lim_rise_align_taps_trail, poc2lim_fall_align_taps_lead,
poc2lim_fall_align_taps_trail, oclkdelay_init_val, wl_po_fine_cnt,
simp_stg3_final_sel, oclkdelay_calib_done, poc2lim_detect_done,
prech_done, oclkdelay_calib_cnt
);
function [TAPCNTRWIDTH:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base[TAPCNTRWIDTH-1:0]-b;
end
endfunction // mod_sub
input clk;
input rst;
input lim_start;
input po_rdy;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_rise_align_taps_trail;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_lead;
input [TAPCNTRWIDTH-1:0] poc2lim_fall_align_taps_trail;
input [5:0] oclkdelay_init_val;
input [5:0] wl_po_fine_cnt;
input [5:0] simp_stg3_final_sel;
input oclkdelay_calib_done;
input poc2lim_detect_done;
input prech_done;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
output lim2init_write_request;
output lim2init_prech_req;
output lim2poc_rdy;
output lim2poc_ktap_right; // I think this can be defaulted.
output lim2stg3_inc;
output lim2stg3_dec;
output lim2stg2_inc;
output lim2stg2_dec;
output lim_done;
output [5:0] lim2ocal_stg3_right_lim;
output [5:0] lim2ocal_stg3_left_lim;
output [255:0] dbg_ocd_lim;
// Stage 3 taps can move an additional + or - 60 degrees from the write level position
// Convert 60 degrees to MMCM taps. 360/60=6.
//localparam real DIV_FACTOR = 360/TDQSS_DEGREES;
//localparam real TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam DIV_FACTOR = 360/TDQSS_DEGREES;
localparam TDQSS_LIM_MMCM_TAPS = TAPSPERKCLK/DIV_FACTOR;
localparam WAIT_CNT = 15;
localparam IDLE = 14'b00_0000_0000_0001;
localparam INIT = 14'b00_0000_0000_0010;
localparam WAIT_WR_REQ = 14'b00_0000_0000_0100;
localparam WAIT_POC_DONE = 14'b00_0000_0000_1000;
localparam WAIT_STG3 = 14'b00_0000_0001_0000;
localparam STAGE3_INC = 14'b00_0000_0010_0000;
localparam STAGE3_DEC = 14'b00_0000_0100_0000;
localparam STAGE2_INC = 14'b00_0000_1000_0000;
localparam STAGE2_DEC = 14'b00_0001_0000_0000;
localparam STG3_INCDEC_WAIT = 14'b00_0010_0000_0000;
localparam STG2_INCDEC_WAIT = 14'b00_0100_0000_0000;
localparam STAGE2_TAP_CHK = 14'b00_1000_0000_0000;
localparam PRECH_REQUEST = 14'b01_0000_0000_0000;
localparam LIMIT_DONE = 14'b10_0000_0000_0000;
// Flip-flops
reg [5:0] stg3_init_val;
reg [13:0] lim_state;
reg lim_start_r;
reg ktap_right_r;
reg write_request_r;
reg prech_req_r;
reg poc_ready_r;
reg wait_cnt_en_r;
reg wait_cnt_done;
reg [3:0] wait_cnt_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg2_tap_cnt;
reg [5:0] stg3_left_lim;
reg [5:0] stg3_right_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_left_lim;
reg [DQS_WIDTH*6-1:0] cmplx_stg3_right_lim;
reg [DQS_WIDTH*6-1:0] simp_stg3_right_lim;
reg [5:0] stg3_dec_val;
reg [5:0] stg3_inc_val;
reg detect_done_r;
reg stg3_dec_r;
reg stg2_inc_r;
reg stg3_inc2init_val_r;
reg stg3_inc2init_val_r1;
reg stg3_dec2init_val_r;
reg stg3_dec2init_val_r1;
reg stg3_dec_req_r;
reg stg3_inc_req_r;
reg stg2_dec_req_r;
reg stg2_inc_req_r;
reg stg3_init_dec_r;
reg [TAPCNTRWIDTH:0] mmcm_current;
reg [TAPCNTRWIDTH:0] mmcm_init_trail;
reg [TAPCNTRWIDTH:0] mmcm_init_lead;
reg done_r;
reg [13:0] lim_nxt_state;
reg ktap_right;
reg write_request;
reg prech_req;
reg poc_ready;
reg stg3_dec;
reg stg2_inc;
reg stg3_inc2init_val;
reg stg3_dec2init_val;
reg stg3_dec_req;
reg stg3_inc_req;
reg stg2_dec_req;
reg stg2_inc_req;
reg stg3_init_dec;
reg done;
reg oclkdelay_calib_done_r;
wire [TAPCNTRWIDTH:0] mmcm_sub_dec = mod_sub (mmcm_init_trail, mmcm_current, TAPSPERKCLK);
wire [TAPCNTRWIDTH:0] mmcm_sub_inc = mod_sub (mmcm_current, mmcm_init_lead, TAPSPERKCLK);
/***************************************************************************/
// Debug signals
/***************************************************************************/
assign dbg_ocd_lim[0+:DQS_WIDTH*6] = simp_stg3_left_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[54+:DQS_WIDTH*6] = simp_stg3_right_lim[DQS_WIDTH*6-1:0];
assign dbg_ocd_lim[255:108] = 'd0;
assign lim2init_write_request = write_request_r;
assign lim2init_prech_req = prech_req_r;
assign lim2poc_ktap_right = ktap_right_r;
assign lim2poc_rdy = poc_ready_r;
assign lim2ocal_stg3_left_lim = stg3_left_lim;
assign lim2ocal_stg3_right_lim = stg3_right_lim;
assign lim2stg3_dec = stg3_dec_req_r;
assign lim2stg3_inc = stg3_inc_req_r;
assign lim2stg2_dec = stg2_dec_req_r;
assign lim2stg2_inc = stg2_inc_req_r;
assign lim_done = done_r;
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if ((lim_state == WAIT_WR_REQ) ||
(lim_state == WAIT_STG3) ||
(lim_state == INIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
end
// Wait counter for wait states WAIT_WR_REQ and WAIT_STG3
// To avoid DQS toggling when stage2 and 3 taps are moving
always @(posedge clk) begin
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
wait_cnt_done <= #TCQ 1'b0;
end else begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b1;
end
end
end
/**************************Wait Counter End***********************************/
// Flip-flops
always @(posedge clk) begin
if (rst)
oclkdelay_calib_done_r <= #TCQ 1'b0;
else
oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done;
end
always @(posedge clk) begin
if (rst)
stg3_init_val <= #TCQ oclkdelay_init_val;
else if (oclkdelay_calib_done)
stg3_init_val <= #TCQ simp_stg3_final_sel;
else
stg3_init_val <= #TCQ oclkdelay_init_val;
end
always @(posedge clk) begin
if (rst) begin
lim_state <= #TCQ IDLE;
lim_start_r <= #TCQ 1'b0;
ktap_right_r <= #TCQ 1'b0;
write_request_r <= #TCQ 1'b0;
prech_req_r <= #TCQ 1'b0;
poc_ready_r <= #TCQ 1'b0;
detect_done_r <= #TCQ 1'b0;
stg3_dec_r <= #TCQ 1'b0;
stg2_inc_r <= #TCQ 1'b0;
stg3_inc2init_val_r <= #TCQ 1'b0;
stg3_inc2init_val_r1<= #TCQ 1'b0;
stg3_dec2init_val_r <= #TCQ 1'b0;
stg3_dec2init_val_r1<= #TCQ 1'b0;
stg3_dec_req_r <= #TCQ 1'b0;
stg3_inc_req_r <= #TCQ 1'b0;
stg2_dec_req_r <= #TCQ 1'b0;
stg2_inc_req_r <= #TCQ 1'b0;
done_r <= #TCQ 1'b0;
stg3_dec_val <= #TCQ 'd0;
stg3_inc_val <= #TCQ 'd0;
stg3_init_dec_r <= #TCQ 1'b0;
end else begin
lim_state <= #TCQ lim_nxt_state;
lim_start_r <= #TCQ lim_start;
ktap_right_r <= #TCQ ktap_right;
write_request_r <= #TCQ write_request;
prech_req_r <= #TCQ prech_req;
poc_ready_r <= #TCQ poc_ready;
detect_done_r <= #TCQ poc2lim_detect_done;
stg3_dec_r <= #TCQ stg3_dec;
stg2_inc_r <= #TCQ stg2_inc;
stg3_inc2init_val_r <= #TCQ stg3_inc2init_val;
stg3_inc2init_val_r1<= #TCQ stg3_inc2init_val_r;
stg3_dec2init_val_r <= #TCQ stg3_dec2init_val;
stg3_dec2init_val_r1<= #TCQ stg3_dec2init_val_r;
stg3_dec_req_r <= #TCQ stg3_dec_req;
stg3_inc_req_r <= #TCQ stg3_inc_req;
stg2_dec_req_r <= #TCQ stg2_dec_req;
stg2_inc_req_r <= #TCQ stg2_inc_req;
stg3_init_dec_r <= #TCQ stg3_init_dec;
done_r <= #TCQ done;
if (stg3_init_val > (('d63 - wl_po_fine_cnt)/2))
stg3_dec_val <= #TCQ (stg3_init_val - ('d63 - wl_po_fine_cnt)/2);
else
stg3_dec_val <= #TCQ 'd0;
if (stg3_init_val < 'd63 - ((wl_po_fine_cnt)/2))
stg3_inc_val <= #TCQ (stg3_init_val + (wl_po_fine_cnt)/2);
else
stg3_inc_val <= #TCQ 'd63;
end
end
// Keeping track of stage 3 tap count
always @(posedge clk) begin
if (rst)
stg3_tap_cnt <= #TCQ stg3_init_val;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg3_tap_cnt <= #TCQ stg3_init_val;
else if (lim_state == STAGE3_INC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
else if (lim_state == STAGE3_DEC)
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
end
// Keeping track of stage 2 tap count
always @(posedge clk) begin
if (rst)
stg2_tap_cnt <= #TCQ 'd0;
else if ((lim_state == IDLE) || (lim_state == INIT))
stg2_tap_cnt <= #TCQ wl_po_fine_cnt;
else if (lim_state == STAGE2_INC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
else if (lim_state == STAGE2_DEC)
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
end
// Keeping track of MMCM tap count
always @(posedge clk) begin
if (rst) begin
mmcm_init_trail <= #TCQ 'd0;
mmcm_init_lead <= #TCQ 'd0;
end else if (poc2lim_detect_done && !detect_done_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_init_trail <= #TCQ poc2lim_rise_align_taps_trail;
if (stg3_tap_cnt == stg3_inc_val)
mmcm_init_lead <= #TCQ poc2lim_rise_align_taps_lead;
end
end
always @(posedge clk) begin
if (rst) begin
mmcm_current <= #TCQ 'd0;
end else if (stg3_dec_r) begin
if (stg3_tap_cnt == stg3_dec_val)
mmcm_current <= #TCQ mmcm_init_trail;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_lead;
end else begin
if (stg3_tap_cnt == stg3_inc_val)
mmcm_current <= #TCQ mmcm_init_lead;
else
mmcm_current <= #TCQ poc2lim_rise_align_taps_trail;
end
end
// Record Stage3 Left Limit
always @(posedge clk) begin
if (rst) begin
stg3_left_lim <= #TCQ 'd0;
simp_stg3_left_lim <= #TCQ 'd0;
cmplx_stg3_left_lim <= #TCQ 'd0;
end else if (stg3_inc2init_val_r && !stg3_inc2init_val_r1) begin
stg3_left_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_left_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_left_lim <= #TCQ 'd0;
end
// Record Stage3 Right Limit
always @(posedge clk) begin
if (rst) begin
stg3_right_lim <= #TCQ 'd0;
cmplx_stg3_right_lim <= #TCQ 'd0;
simp_stg3_right_lim <= #TCQ 'd0;
end else if (stg3_dec2init_val_r && !stg3_dec2init_val_r1) begin
stg3_right_lim <= #TCQ stg3_tap_cnt;
if (oclkdelay_calib_done)
cmplx_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
else
simp_stg3_right_lim[oclkdelay_calib_cnt*6+:6] <= #TCQ stg3_tap_cnt;
end else if (lim_start && !lim_start_r)
stg3_right_lim <= #TCQ 'd0;
end
always @(*) begin
lim_nxt_state = lim_state;
ktap_right = ktap_right_r;
write_request = write_request_r;
prech_req = prech_req_r;
poc_ready = poc_ready_r;
stg3_dec = stg3_dec_r;
stg2_inc = stg2_inc_r;
stg3_inc2init_val = stg3_inc2init_val_r;
stg3_dec2init_val = stg3_dec2init_val_r;
stg3_dec_req = stg3_dec_req_r;
stg3_inc_req = stg3_inc_req_r;
stg2_inc_req = stg2_inc_req_r;
stg2_dec_req = stg2_dec_req_r;
stg3_init_dec = stg3_init_dec_r;
done = done_r;
case(lim_state)
IDLE: begin
if (lim_start && !lim_start_r) begin
lim_nxt_state = INIT;
stg3_dec = 1'b1;
stg2_inc = 1'b1;
stg3_init_dec = 1'b1;
done = 1'b0;
end
//New start of limit module for complex oclkdelay calib
else if (oclkdelay_calib_done && !oclkdelay_calib_done_r && (BYPASS_COMPLEX_OCAL == "FALSE")) begin
done = 1'b0;
end
end
INIT: begin
ktap_right = 1'b1;
// Initial stage 2 increment to 63 for left limit
if (wait_cnt_done)
lim_nxt_state = STAGE2_TAP_CHK;
end
// Wait for DQS to toggle before asserting poc_ready
WAIT_WR_REQ: begin
write_request = 1'b1;
if (wait_cnt_done) begin
poc_ready = 1'b1;
lim_nxt_state = WAIT_POC_DONE;
end
end
// Wait for POC detect done signal
WAIT_POC_DONE: begin
if (poc2lim_detect_done) begin
write_request = 1'b0;
poc_ready = 1'b0;
lim_nxt_state = WAIT_STG3;
end
end
// Wait for DQS to stop toggling before stage3 inc/dec
WAIT_STG3: begin
if (wait_cnt_done) begin
if (stg3_dec_r) begin
// Check for Stage 3 underflow and MMCM tap limit
if ((stg3_tap_cnt > 'd0) && (mmcm_sub_dec < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_DEC;
else begin
stg3_dec = 1'b0;
stg3_inc2init_val = 1'b1;
lim_nxt_state = STAGE3_INC;
end
end else begin // Stage 3 being incremented
// Check for Stage 3 overflow and MMCM tap limit
if ((stg3_tap_cnt < 'd63) && (mmcm_sub_inc < TDQSS_LIM_MMCM_TAPS))
lim_nxt_state = STAGE3_INC;
else begin
stg3_dec2init_val = 1'b1;
lim_nxt_state = STAGE3_DEC;
end
end
end
end
STAGE3_INC: begin
stg3_inc_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
STAGE3_DEC: begin
stg3_dec_req = 1'b1;
lim_nxt_state = STG3_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG3_INCDEC_WAIT: begin
stg3_dec_req = 1'b0;
stg3_inc_req = 1'b0;
if (!stg3_dec_req_r && !stg3_inc_req_r && po_rdy) begin
if (stg3_init_dec_r) begin
// Initial decrement of stage 3
if (stg3_tap_cnt > stg3_dec_val)
lim_nxt_state = STAGE3_DEC;
else begin
lim_nxt_state = WAIT_WR_REQ;
stg3_init_dec = 1'b0;
end
end else if (stg3_dec2init_val_r) begin
if (stg3_tap_cnt > stg3_init_val)
lim_nxt_state = STAGE3_DEC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else if (stg3_inc2init_val_r) begin
if (stg3_tap_cnt < stg3_inc_val)
lim_nxt_state = STAGE3_INC;
else
lim_nxt_state = STAGE2_TAP_CHK;
end else begin
lim_nxt_state = WAIT_WR_REQ;
end
end
end
// Check for overflow and underflow of stage2 taps
STAGE2_TAP_CHK: begin
if (stg3_dec2init_val_r) begin
// Increment stage 2 to write level tap value at the end of limit detection
if (stg2_tap_cnt < wl_po_fine_cnt)
lim_nxt_state = STAGE2_INC;
else begin
lim_nxt_state = PRECH_REQUEST;
end
end else if (stg3_inc2init_val_r) begin
// Decrement stage 2 to '0' to determine right limit
if (stg2_tap_cnt > 'd0)
lim_nxt_state = STAGE2_DEC;
else begin
lim_nxt_state = PRECH_REQUEST;
stg3_inc2init_val = 1'b0;
end
end else if (stg2_inc_r && (stg2_tap_cnt < 'd63)) begin
// Initial increment to 63
lim_nxt_state = STAGE2_INC;
end else begin
lim_nxt_state = STG3_INCDEC_WAIT;
stg2_inc = 1'b0;
end
end
STAGE2_INC: begin
stg2_inc_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
STAGE2_DEC: begin
stg2_dec_req = 1'b1;
lim_nxt_state = STG2_INCDEC_WAIT;
end
// Wait for stage3 inc/dec to complete (po_rdy)
STG2_INCDEC_WAIT: begin
stg2_inc_req = 1'b0;
stg2_dec_req = 1'b0;
if (!stg2_inc_req_r && !stg2_dec_req_r && po_rdy)
lim_nxt_state = STAGE2_TAP_CHK;
end
PRECH_REQUEST: begin
prech_req = 1'b1;
if (prech_done) begin
prech_req = 1'b0;
if (stg3_dec2init_val_r)
lim_nxt_state = LIMIT_DONE;
else
lim_nxt_state = WAIT_WR_REQ;
end
end
LIMIT_DONE: begin
done = 1'b1;
ktap_right = 1'b0;
stg3_dec2init_val = 1'b0;
lim_nxt_state = IDLE;
end
default: begin
lim_nxt_state = IDLE;
end
endcase
end
endmodule //mig_7_series_v4_0_ddr_phy_ocd_lim
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_mux.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: The limit block and the _po_cntlr block both manipulate
// the phaser out and the POC. This block muxes those commands
// together, and encapsulates logic required for meeting phaser
// setup and wait times.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_mux #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
ktap_at_left_edge, ktap_at_right_edge, mmcm_edge_detect_rdy,
po_stg3_incdec, po_en_stg3, po_en_stg23, po_stg23_sel,
po_stg23_incdec, po_rdy, wl_po_fine_cnt_sel, oclk_prech_req,
// Inputs
clk, rst, ocd_ktap_right, ocd_ktap_left, lim2poc_ktap_right,
lim2poc_rdy, ocd_edge_detect_rdy, lim2stg2_inc, lim2stg2_dec,
lim2stg3_inc, lim2stg3_dec, ocd2stg2_inc, ocd2stg2_dec,
ocd_cntlr2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, wl_po_fine_cnt,
oclkdelay_calib_cnt, lim2init_prech_req, ocd_prech_req
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam PO_WAIT = 15;
localparam POW_WIDTH = clogb2(PO_WAIT);
localparam ONE = 1;
localparam TWO = 2;
input clk;
input rst;
input ocd_ktap_right, ocd_ktap_left;
input lim2poc_ktap_right;
output ktap_at_left_edge, ktap_at_right_edge;
assign ktap_at_left_edge = ocd_ktap_left;
assign ktap_at_right_edge = lim2poc_ktap_right || ocd_ktap_right;
input lim2poc_rdy;
input ocd_edge_detect_rdy;
output mmcm_edge_detect_rdy;
assign mmcm_edge_detect_rdy = lim2poc_rdy || ocd_edge_detect_rdy;
// po_stg3_incdec and po_en_stg3 are deprecated and should be removed.
output po_stg3_incdec;
output po_en_stg3;
assign po_stg3_incdec = 1'b0;
assign po_en_stg3 = 1'b0;
reg [1:0] po_setup_ns, po_setup_r;
always @(posedge clk) po_setup_r <= #TCQ po_setup_ns;
input lim2stg2_inc;
input lim2stg2_dec;
input lim2stg3_inc;
input lim2stg3_dec;
input ocd2stg2_inc;
input ocd2stg2_dec;
input ocd_cntlr2stg2_dec;
input ocd2stg3_inc;
input ocd2stg3_dec;
wire setup_po =
lim2stg2_inc || lim2stg2_dec || lim2stg3_inc || lim2stg3_dec ||
ocd2stg2_inc || ocd2stg2_dec || ocd2stg3_inc || ocd2stg3_dec || ocd_cntlr2stg2_dec;
always @(*) begin
po_setup_ns = po_setup_r;
if (rst) po_setup_ns = 2'b00;
else if (setup_po) po_setup_ns = 2'b11;
else if (|po_setup_r) po_setup_ns = po_setup_r - 2'b01;
end
reg po_en_stg23_r;
wire po_en_stg23_ns = ~rst && po_setup_r == 2'b01;
always @(posedge clk) po_en_stg23_r <= #TCQ po_en_stg23_ns;
output po_en_stg23;
assign po_en_stg23 = po_en_stg23_r;
wire sel_stg3 = lim2stg3_inc || lim2stg3_dec || ocd2stg3_inc || ocd2stg3_dec;
reg [POW_WIDTH-1:0] po_wait_r, po_wait_ns;
reg po_stg23_sel_r;
// Reset to zero at the end. Makes adjust stg2 at end of centering
// get the correct value of po_counter_read_val.
wire po_stg23_sel_ns = ~rst && (setup_po
? sel_stg3
? 1'b1
: 1'b0
: po_stg23_sel_r && !(po_wait_r == ONE[POW_WIDTH-1:0]));
always @(posedge clk) po_stg23_sel_r <= #TCQ po_stg23_sel_ns;
output po_stg23_sel;
assign po_stg23_sel = po_stg23_sel_r;
wire po_inc = lim2stg2_inc || lim2stg3_inc || ocd2stg2_inc || ocd2stg3_inc;
reg po_stg23_incdec_r;
wire po_stg23_incdec_ns = ~rst && (setup_po ? po_inc ? 1'b1 : 1'b0 : po_stg23_incdec_r);
always @(posedge clk) po_stg23_incdec_r <= #TCQ po_stg23_incdec_ns;
output po_stg23_incdec;
assign po_stg23_incdec = po_stg23_incdec_r;
always @(posedge clk) po_wait_r <= #TCQ po_wait_ns;
always @(*) begin
po_wait_ns = po_wait_r;
if (rst) po_wait_ns = {POW_WIDTH{1'b0}};
else if (po_en_stg23_r) po_wait_ns = PO_WAIT[POW_WIDTH-1:0] - ONE[POW_WIDTH-1:0];
else if (po_wait_r != {POW_WIDTH{1'b0}}) po_wait_ns = po_wait_r - ONE[POW_WIDTH-1:0];
end
wire po_rdy_ns = ~(setup_po || |po_setup_r || |po_wait_ns);
reg po_rdy_r;
always @(posedge clk) po_rdy_r <= #TCQ po_rdy_ns;
output po_rdy;
assign po_rdy = po_rdy_r;
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_shifted = wl_po_fine_cnt >> oclkdelay_calib_cnt*6;
output [5:0] wl_po_fine_cnt_sel;
assign wl_po_fine_cnt_sel = wl_po_fine_shifted[5:0];
input lim2init_prech_req;
input ocd_prech_req;
output oclk_prech_req;
assign oclk_prech_req = ocd_prech_req || lim2init_prech_req;
endmodule // mig_7series_v4_2_ddr_phy_ocd_mux
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_po_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Manipulates phaser out stg2f and stg3 on behalf of
// scan and DQS centering.
//
// Maintains a shadow of the phaser out stg2f and stg3 tap settings.
// The stg3 shadow is 6 bits, just like the phaser out. stg2f is
// 8 bits. This allows the po_cntlr to track how far past the stg2f
// saturation points we have gone when stepping to the limits of stg3.
// This way we're can stay in sync when we step back from the saturation
// limits.
//
// Looks at the edge values and determines which case has been
// detected by the scan. Uses the results to drive the centering.
//
// Main state machine waits until it sees reset_scan go to zero. While
// waiting it is writing the initialzation values to the stg2 and stg3
// shadows. When reset_scan goes low, taps_set is pulsed. This
// tells the sampling block to begin sampling. When the sampling
// block has finished sampling this setting of the phaser out taps,
// is signals by setting samp_done. When the main state machine
// sees samp_done it sets the next value in the phaser out and
// waits for the phaser out to be ready before beginning the next
// sample.
//
// Turns out phy_init is sensitive to the length of the ocal_num_samples_done
// pulse. Something like a precharge and activate time. Added feature
// to resume_wait to wait at least 32 cycles between assertion and
// subsequent deassertion of ocal_num_samples_done.
//
// Also turns out phy_init needs help to get into consistent
// starting state for complex cal. This can be done by preseting
// ocal_num_samples_done to one. Then waiting for 32 fabric clocks,
// turn off _done and then assert _resume.
//
// Scanning algorithm.
//
// Phaser manipulation algoritm.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_po_cntlr #
(parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter nCK_PER_CLK = 4,
parameter SAMPLES = 128,
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_done, ocal_num_samples_done_r, oclkdelay_center_calib_start,
oclkdelay_center_calib_done, oclk_center_write_resume, ocd2stg2_inc,
ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec, stg3, simp_stg3_final,
cmplx_stg3_final, simp_stg3_final_sel, ninety_offsets,
scanning_right, ocd_ktap_left, ocd_ktap_right, ocd_edge_detect_rdy,
taps_set, use_noise_window, ocal_scan_win_not_found,
// Inputs
clk, rst, reset_scan, oclkdelay_init_val, lim2ocal_stg3_right_lim,
lim2ocal_stg3_left_lim, complex_oclkdelay_calib_start,
po_counter_read_val, oclkdelay_calib_cnt, mmcm_edge_detect_done,
mmcm_lbclk_edge_aligned, poc_backup, phy_rddata_en_3, zero2fuzz,
fuzz2zero, oneeighty2fuzz, fuzz2oneeighty, z2f, f2z, o2f, f2o,
scan_right, samp_done, wl_po_fine_cnt_sel, po_rdy
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
input reset_scan;
reg scan_done_r;
output scan_done;
assign scan_done = scan_done_r;
output [5:0] simp_stg3_final_sel;
reg cmplx_samples_done_ns, cmplx_samples_done_r;
always @(posedge clk) cmplx_samples_done_r <= #TCQ cmplx_samples_done_ns;
output ocal_num_samples_done_r;
assign ocal_num_samples_done_r = cmplx_samples_done_r;
// Write Level signals during OCLKDELAY calibration
input [5:0] oclkdelay_init_val;
input [5:0] lim2ocal_stg3_right_lim;
input [5:0] lim2ocal_stg3_left_lim;
input complex_oclkdelay_calib_start;
reg oclkdelay_center_calib_start_ns, oclkdelay_center_calib_start_r;
always @(posedge clk) oclkdelay_center_calib_start_r <= #TCQ oclkdelay_center_calib_start_ns;
output oclkdelay_center_calib_start;
assign oclkdelay_center_calib_start = oclkdelay_center_calib_start_r;
reg oclkdelay_center_calib_done_ns, oclkdelay_center_calib_done_r;
always @(posedge clk) oclkdelay_center_calib_done_r <= #TCQ oclkdelay_center_calib_done_ns;
output oclkdelay_center_calib_done;
assign oclkdelay_center_calib_done = oclkdelay_center_calib_done_r;
reg oclk_center_write_resume_ns, oclk_center_write_resume_r;
always @(posedge clk) oclk_center_write_resume_r <= #TCQ oclk_center_write_resume_ns;
output oclk_center_write_resume;
assign oclk_center_write_resume = oclk_center_write_resume_r;
reg ocd2stg2_inc_r, ocd2stg2_dec_r, ocd2stg3_inc_r, ocd2stg3_dec_r;
output ocd2stg2_inc, ocd2stg2_dec, ocd2stg3_inc, ocd2stg3_dec;
assign ocd2stg2_inc = ocd2stg2_inc_r;
assign ocd2stg2_dec = ocd2stg2_dec_r;
assign ocd2stg3_inc = ocd2stg3_inc_r;
assign ocd2stg3_dec = ocd2stg3_dec_r;
// Remember, two stage 2 steps for every stg 3 step. And we need a sign bit.
reg [8:0] stg2_ns, stg2_r;
always @(posedge clk) stg2_r <= #TCQ stg2_ns;
reg [5:0] stg3_ns, stg3_r;
always @(posedge clk) stg3_r <= #TCQ stg3_ns;
output [5:0] stg3;
assign stg3 = stg3_r;
input [5:0] wl_po_fine_cnt_sel;
input [8:0] po_counter_read_val;
reg [5:0] po_counter_read_val_r;
always @(posedge clk) po_counter_read_val_r <= #TCQ po_counter_read_val[5:0];
reg [DQS_WIDTH*6-1:0] simp_stg3_final_ns, simp_stg3_final_r, cmplx_stg3_final_ns, cmplx_stg3_final_r;
always @(posedge clk) simp_stg3_final_r <= #TCQ simp_stg3_final_ns;
always @(posedge clk) cmplx_stg3_final_r <= #TCQ cmplx_stg3_final_ns;
output [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
assign simp_stg3_final = simp_stg3_final_r;
assign cmplx_stg3_final = cmplx_stg3_final_r;
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire [DQS_WIDTH*6-1:0] simp_stg3_final_shft = simp_stg3_final_r >> oclkdelay_calib_cnt * 6;
assign simp_stg3_final_sel = simp_stg3_final_shft[5:0];
wire [5:0] stg3_init = complex_oclkdelay_calib_start ? simp_stg3_final_sel : oclkdelay_init_val;
wire signed [8:0] stg2_steps = stg3_r > stg3_init
? -9'sd2 * $signed({3'b0, (stg3_r - stg3_init)})
: 9'sd2 * $signed({3'b0, (stg3_init - stg3_r)});
wire signed [8:0] stg2_target_ns = $signed({3'b0, wl_po_fine_cnt_sel}) + stg2_steps;
reg signed [8:0] stg2_target_r;
always @ (posedge clk) stg2_target_r <= #TCQ stg2_target_ns;
reg [5:0] stg2_final_ns, stg2_final_r;
always @(posedge clk) stg2_final_r <= #TCQ stg2_final_ns;
always @(*) stg2_final_ns = stg2_target_r[8] == 1'b1
? 6'd0
: stg2_target_r > 9'd63
? 6'd63
: stg2_target_r[5:0];
wire final_stg2_inc = stg2_final_r > po_counter_read_val_r;
wire final_stg2_dec = stg2_final_r < po_counter_read_val_r;
wire left_lim = stg3_r == lim2ocal_stg3_left_lim;
wire right_lim = stg3_r == lim2ocal_stg3_right_lim;
reg [1:0] ninety_offsets_ns, ninety_offsets_r;
always @(posedge clk) ninety_offsets_r <= #TCQ ninety_offsets_ns;
output [1:0] ninety_offsets;
assign ninety_offsets = ninety_offsets_r;
reg scanning_right_ns, scanning_right_r;
always @(posedge clk) scanning_right_r <= #TCQ scanning_right_ns;
output scanning_right;
assign scanning_right = scanning_right_r;
reg ocd_ktap_left_ns, ocd_ktap_left_r, ocd_ktap_right_ns, ocd_ktap_right_r;
always @(posedge clk) ocd_ktap_left_r <= #TCQ ocd_ktap_left_ns;
always @(posedge clk) ocd_ktap_right_r <= #TCQ ocd_ktap_right_ns;
output ocd_ktap_left, ocd_ktap_right;
assign ocd_ktap_left = ocd_ktap_left_r;
assign ocd_ktap_right = ocd_ktap_right_r;
reg ocd_edge_detect_rdy_ns, ocd_edge_detect_rdy_r;
always @(posedge clk) ocd_edge_detect_rdy_r <= #TCQ ocd_edge_detect_rdy_ns;
output ocd_edge_detect_rdy;
assign ocd_edge_detect_rdy = ocd_edge_detect_rdy_r;
input mmcm_edge_detect_done;
input mmcm_lbclk_edge_aligned;
input poc_backup;
reg poc_backup_ns, poc_backup_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
reg taps_set_r;
output taps_set;
assign taps_set = taps_set_r;
input phy_rddata_en_3;
input [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
input z2f, f2z, o2f, f2o;
wire zero = f2z && z2f;
wire noise = z2f && f2o;
wire oneeighty = f2o && o2f;
reg win_not_found;
reg [1:0] ninety_offsets_final_ns, ninety_offsets_final_r;
always @(posedge clk) ninety_offsets_final_r <= #TCQ ninety_offsets_final_ns;
reg [5:0] left, right, current_edge;
always @(*) begin
left = lim2ocal_stg3_left_lim;
right = lim2ocal_stg3_right_lim;
ninety_offsets_final_ns = 2'd0;
win_not_found = 1'b0;
if (zero) begin
left = fuzz2zero;
right = zero2fuzz;
end
else if (noise) begin
left = zero2fuzz;
right = fuzz2oneeighty;
ninety_offsets_final_ns = 2'd1;
end
else if (oneeighty) begin
left = fuzz2oneeighty;
right = oneeighty2fuzz;
ninety_offsets_final_ns = 2'd2;
end
else if (z2f) begin
right = zero2fuzz;
end
else if (f2o) begin
left = fuzz2oneeighty;
ninety_offsets_final_ns = 2'd2;
end
else if (f2z) begin
left = fuzz2zero;
end
else win_not_found = 1'b1;
current_edge = ocd_ktap_left_r ? left : right;
end // always @ begin
output use_noise_window;
assign use_noise_window = ninety_offsets == 2'd1;
reg ocal_scan_win_not_found_ns, ocal_scan_win_not_found_r;
always @(posedge clk) ocal_scan_win_not_found_r <= #TCQ ocal_scan_win_not_found_ns;
output ocal_scan_win_not_found;
assign ocal_scan_win_not_found = ocal_scan_win_not_found_r;
wire inc_po_ns = current_edge > stg3_r;
wire dec_po_ns = current_edge < stg3_r;
reg inc_po_r, dec_po_r;
always @(posedge clk) inc_po_r <= #TCQ inc_po_ns;
always @(posedge clk) dec_po_r <= #TCQ dec_po_ns;
input scan_right;
wire left_stop = left_lim || scan_right;
wire right_stop = right_lim || o2f;
// POC samples every other fabric clock.
localparam POC_SAMPLE_CLEAR_WAIT = SAMPLES * 2 > 15 ? SAMPLES * 2 : 15;
localparam MAX_RESUME_WAIT = POC_SAMPLE_CLEAR_WAIT > 31 ? POC_SAMPLE_CLEAR_WAIT : 31;
localparam RESUME_WAIT_WIDTH = clogb2(MAX_RESUME_WAIT + 1);
reg [RESUME_WAIT_WIDTH-1:0] resume_wait_ns, resume_wait_r;
always @(posedge clk) resume_wait_r <= #TCQ resume_wait_ns;
wire resume_wait = |resume_wait_r;
reg po_done_ns, po_done_r;
always @(posedge clk) po_done_r <= #TCQ po_done_ns;
input samp_done;
input po_rdy;
reg up_ns, up_r;
always @(posedge clk) up_r <= #TCQ up_ns;
reg [1:0] two_ns, two_r;
always @(posedge clk) two_r <= #TCQ two_ns;
/* wire stg2_zero = ~|stg2_r;
wire [8:0] stg2_2_zero = stg2_r[8] ? 9'd0
: stg2_r > 9'd63
? 9'd63
: stg2_r; */
reg [3:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
reg phy_rddata_en_3_second_ns, phy_rddata_en_3_second_r;
always @(posedge clk) phy_rddata_en_3_second_r <= #TCQ phy_rddata_en_3_second_ns;
always @(*) phy_rddata_en_3_second_ns = ~reset_scan && (phy_rddata_en_3
? ~phy_rddata_en_3_second_r
: phy_rddata_en_3_second_r);
wire use_samp_done = nCK_PER_CLK == 2 ? phy_rddata_en_3 && phy_rddata_en_3_second_r : phy_rddata_en_3;
reg po_center_wait;
reg po_slew;
reg po_finish_scan;
always @(*) begin
// Default next state assignments.
cmplx_samples_done_ns = cmplx_samples_done_r;
cmplx_stg3_final_ns = cmplx_stg3_final_r;
scanning_right_ns = scanning_right_r;
ninety_offsets_ns = ninety_offsets_r;
ocal_scan_win_not_found_ns = ocal_scan_win_not_found_r;
ocd_edge_detect_rdy_ns = ocd_edge_detect_rdy_r;
ocd_ktap_left_ns = ocd_ktap_left_r;
ocd_ktap_right_ns = ocd_ktap_right_r;
ocd2stg2_inc_r = 1'b0;
ocd2stg2_dec_r = 1'b0;
ocd2stg3_inc_r = 1'b0;
ocd2stg3_dec_r = 1'b0;
oclkdelay_center_calib_start_ns = oclkdelay_center_calib_start_r;
oclkdelay_center_calib_done_ns = 1'b0;
oclk_center_write_resume_ns = oclk_center_write_resume_r;
po_center_wait = 1'b0;
po_done_ns = po_done_r;
po_finish_scan = 1'b0;
po_slew = 1'b0;
poc_backup_ns = poc_backup_r;
scan_done_r = 1'b0;
simp_stg3_final_ns = simp_stg3_final_r;
sm_ns = sm_r;
taps_set_r = 1'b0;
up_ns = up_r;
stg2_ns = stg2_r;
stg3_ns = stg3_r;
two_ns = two_r;
resume_wait_ns = resume_wait_r;
if (rst == 1'b1) begin
// RESET next states
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b0;
ocd_edge_detect_rdy_ns = 1'b0;
oclk_center_write_resume_ns = 1'b0;
oclkdelay_center_calib_start_ns = 1'b0;
po_done_ns = 1'b1;
resume_wait_ns = 5'd0;
sm_ns = /*AK("READY")*/4'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/4'd0:begin
poc_backup_ns = 1'b0;
stg2_ns = {3'b0, wl_po_fine_cnt_sel};
stg3_ns = stg3_init;
scanning_right_ns = 1'b0;
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
if (!reset_scan && ~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
ocal_scan_win_not_found_ns = 1'b0;
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
end
end
/*AL("SAMPLING")*/4'd1:begin
if (samp_done && use_samp_done) begin
if (complex_oclkdelay_calib_start) cmplx_samples_done_ns = 1'b1;
scanning_right_ns = scanning_right_r || left_stop;
if (right_stop && scanning_right_r) begin
oclkdelay_center_calib_start_ns = 1'b1;
ocd_ktap_left_ns = 1'b1;
ocal_scan_win_not_found_ns = win_not_found;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else begin
if (scanning_right_ns) ocd2stg3_inc_r = 1'b1;
else ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("PO_WAIT")*/4'd2;
end
end
end
/*AL("PO_WAIT")*/4'd2:begin
if (po_done_r && ~resume_wait) begin
taps_set_r = 1'b1;
sm_ns = /*AK("SAMPLING")*/4'd1;
cmplx_samples_done_ns = 1'b0;
end
end
/*AL("SLEW_PO")*/4'd3:begin
po_slew = 1'b1;
ninety_offsets_ns = |ninety_offsets_final_r ? 2'b01 : 2'b00;
if (~resume_wait) begin
if (po_done_r) begin
if (inc_po_r) ocd2stg3_inc_r = 1'b1;
else if (dec_po_r) ocd2stg3_dec_r = 1'b1;
else if (~resume_wait) begin
cmplx_samples_done_ns = 1'b0;
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end // if (po_done)
end
end // case: 3'd3
/*AL("ALIGN_EDGES")*/4'd4:
if (~resume_wait) begin
if (mmcm_edge_detect_done) begin
ocd_edge_detect_rdy_ns = 1'b0;
if (ocd_ktap_left_r) begin
ocd_ktap_left_ns = 1'b0;
ocd_ktap_right_ns = 1'b1;
oclk_center_write_resume_ns = 1'b0;
sm_ns = /*AK("SLEW_PO")*/4'd3;
end else if (ocd_ktap_right_r) begin
ocd_ktap_right_ns = 1'b0;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else if (~mmcm_lbclk_edge_aligned) begin
sm_ns = /*AK("DQS_STOP_WAIT")*/4'd6;
oclk_center_write_resume_ns = 1'b0;
end else begin
if (ninety_offsets_r != ninety_offsets_final_r && ocd_edge_detect_rdy_r) begin
ninety_offsets_ns = ninety_offsets_r + 2'b01;
sm_ns = /*AK("WAIT_ONE")*/4'd5;
end else begin
oclk_center_write_resume_ns = 1'b0;
poc_backup_ns = poc_backup;
// stg2_ns = stg2_2_zero;
sm_ns = /*AK("FINISH_SCAN")*/4'd8;
end
end // else: !if(~mmcm_lbclk_edge_aligned)
end else ocd_edge_detect_rdy_ns = 1'b1;
end // if (~resume_wait)
/*AL("WAIT_ONE")*/4'd5:
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
/*AL("DQS_STOP_WAIT")*/4'd6:
if (~resume_wait) begin
ocd2stg3_dec_r = 1'b1;
sm_ns = /*AK("CENTER_PO_WAIT")*/4'd7;
end
/*AL("CENTER_PO_WAIT")*/4'd7: begin
po_center_wait = 1'b1; // Kludge to get around limitation of the AUTOs symbols.
if (po_done_r) begin
sm_ns = /*AK("ALIGN_EDGES")*/4'd4;
oclk_center_write_resume_ns = 1'b1;
end
end
/*AL("FINISH_SCAN")*/4'd8: begin
po_finish_scan = 1'b1;
if (resume_wait_r == 5'd1) begin
if (~poc_backup_r) begin
oclkdelay_center_calib_done_ns = 1'b1;
oclkdelay_center_calib_start_ns = 1'b0;
end
end
if (~resume_wait) begin
if (po_rdy)
if (poc_backup_r) begin
ocd2stg3_inc_r = 1'b1;
poc_backup_ns = 1'b0;
end
else if (~final_stg2_inc && ~final_stg2_dec) begin
if (complex_oclkdelay_calib_start) cmplx_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
else simp_stg3_final_ns[oclkdelay_calib_cnt*6+:6] = stg3_r;
sm_ns = /*AK("READY")*/4'd0;
scan_done_r = 1'b1;
end else begin
ocd2stg2_inc_r = final_stg2_inc;
ocd2stg2_dec_r = final_stg2_dec;
end
end // if (~resume_wait)
end // case: 4'd8
endcase // case (sm_r)
if (ocd2stg3_inc_r) begin
stg3_ns = stg3_r + 6'h1;
up_ns = 1'b0;
end
if (ocd2stg3_dec_r) begin
stg3_ns = stg3_r - 6'h1;
up_ns = 1'b1;
end
if (ocd2stg3_inc_r || ocd2stg3_dec_r) begin
po_done_ns = 1'b0;
two_ns = 2'b00;
end
if (~po_done_r)
if (po_rdy)
if (two_r == 2'b10 || po_center_wait || po_slew || po_finish_scan) po_done_ns = 1'b1;
else begin
two_ns = two_r + 2'b1;
if (up_r) begin
stg2_ns = stg2_r + 9'b1;
if (stg2_r >= 9'd0 && stg2_r < 9'd63) ocd2stg2_inc_r = 1'b1;
end else begin
stg2_ns = stg2_r - 9'b1;
if (stg2_r > 9'd0 && stg2_r <= 9'd63) ocd2stg2_dec_r = 1'b1;
end
end // else: !if(two_r == 2'b10)
if (ocd_ktap_left_ns && ~ocd_ktap_left_r) resume_wait_ns = 'b1;
else if (oclk_center_write_resume_ns && ~oclk_center_write_resume_r)
resume_wait_ns = POC_SAMPLE_CLEAR_WAIT[RESUME_WAIT_WIDTH-1:0];
else if (~oclk_center_write_resume_ns && oclk_center_write_resume_r) resume_wait_ns = 'd15;
else if (cmplx_samples_done_ns & ~cmplx_samples_done_r ||
complex_oclkdelay_calib_start & reset_scan ||
poc_backup_r & ocd2stg3_inc_r) resume_wait_ns = 'd31;
else if (|resume_wait_r) resume_wait_ns = resume_wait_r - 'd1;
end // always @ begin
endmodule // mig_7series_v4_2_ddr_phy_ocd_po_cntlr
// Local Variables:
// verilog-autolabel-prefix: "4'd"
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_samp.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Controls the number of samples and generates an aggregate
//sampling result.
//
// The following shows the nesting of the sampling loop. Nominally built
// to accomodate the "complex" sampling protocol. Adapted for use with
// "simple" samplng.
//
// simple complex
//
// samples OCAL_SIMPLE_SCAN_SAMPS 1 or 50 Depends on SIM_CAL_OPTION
// rd_victim_sel 0 0 to 7
// data_cnt 1 157
//
// First it collects comparison results provided on the
// two bit "match" bus. A particular phaser tap setting may be recorded one
// or many times depending on various parameter settings.
// The two bit match bus corresponds to comparisons for the
// zero or rising phase, and the oneeighty or falling phase. The "aggregate"
// starts out as NULL and then begins collecting comparison results
// when phy_rddata_en_1 is high. The first result is always set into
// the aggregate result. Subsequent results that match aggregate, don't
// make any change. Subsequent compare results that don't match cause the aggregate
// to turn to FUZZ.
//
// A "sample" is defined as a single DRAM burst for the simple step, and
// an entire 157 DRAM data bursts across the 8 victim bits for complex.
//
// Once all samples have been taken, the samp_result is computed by
// comparing the number of successful compares against the threshold.
//
// The second function is to track and control the number of samples. For
// "simple" data, the number of samples is set by OCAL_SIMPLE_SCAN_SAMPS.
// For "complex" data, nominally
// the complex data pattern consists of a sequence of 157 DRAM chunks. This
// sequence is run with each bit in the byte designated as the "victim". This sequence
// is repeated 50 times, although when SIM_CAL_OPTION is set to none "NONE", it is only
// repeated once.
//
// This block generates oclk_calib_resume. For the simple pattern, a single DRAM
// burst is returned For complex its 157 which indicates the start of the 157*50
// sequence for a bit. samp_done is pulsed.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_ocd_samp #
(parameter nCK_PER_CLK = 4,
parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
parameter SCAN_PCT_SAMPS_SOLID = 95,
parameter TCQ = 100,
parameter SIM_CAL_OPTION = "NONE")
(/*AUTOARG*/
// Outputs
samp_done, oclk_calib_resume, rd_victim_sel, samp_result,
// Inputs
complex_oclkdelay_calib_start, clk, rst, reset_scan,
ocal_num_samples_inc, match, phy_rddata_en_1, taps_set,
phy_rddata_en_2
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ONE = 1;
localparam CMPLX_DATA_CNT = nCK_PER_CLK == 2 ? 157 * 2 : 157;
localparam SIMP_DATA_CNT = nCK_PER_CLK == 2 ? 2 : 1;
localparam DATA_CNT_WIDTH = nCK_PER_CLK == 2 ? 9 : 8;
localparam CMPLX_SAMPS = SIM_CAL_OPTION == "NONE" ? 50 : 1;
// Plus one because were counting in natural numbers.
localparam SAMP_CNT_WIDTH = clogb2(OCAL_SIMPLE_SCAN_SAMPS > CMPLX_SAMPS
? OCAL_SIMPLE_SCAN_SAMPS : CMPLX_SAMPS) + 1;
// Remember SAMPLES is natural number counting. One corresponds to one sample.
localparam integer SIMP_SAMPS_SOLID_THRESH = OCAL_SIMPLE_SCAN_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
localparam integer SIMP_SAMPS_HALF_THRESH = SIMP_SAMPS_SOLID_THRESH/2;
localparam integer CMPLX_SAMPS_SOLID_THRESH = CMPLX_SAMPS * SCAN_PCT_SAMPS_SOLID * 0.01;
localparam integer CMPLX_SAMPS_HALF_THRESH = CMPLX_SAMPS_SOLID_THRESH/2;
input complex_oclkdelay_calib_start;
wire [SAMP_CNT_WIDTH-1:0] samples = complex_oclkdelay_calib_start
? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input rst;
input reset_scan;
// Given the need to count phy_data_en, this is not useful.
input ocal_num_samples_inc;
input [1:0] match;
input phy_rddata_en_1;
input taps_set;
reg samp_done_ns, samp_done_r;
always @(posedge clk) samp_done_r <= #TCQ samp_done_ns;
output samp_done;
assign samp_done = samp_done_r;
input phy_rddata_en_2;
wire samp_valid = samp_done_r && phy_rddata_en_2;
reg [1:0] agg_samp_ns, agg_samp_r;
always @(posedge clk) agg_samp_r <= #TCQ agg_samp_ns;
reg oclk_calib_resume_ns, oclk_calib_resume_r;
always @(posedge clk) oclk_calib_resume_r <= #TCQ oclk_calib_resume_ns;
output oclk_calib_resume;
assign oclk_calib_resume = oclk_calib_resume_r;
// Complex data counting.
// Inner most loop. 157 phy_data_en.
reg [DATA_CNT_WIDTH-1:0] data_cnt_ns, data_cnt_r;
always @(posedge clk) data_cnt_r <= #TCQ data_cnt_ns;
// Nominally, 50 samples of the above 157 phy_data_en.
reg [SAMP_CNT_WIDTH-1:0] samps_ns, samps_r;
always @(posedge clk) samps_r <= #TCQ samps_ns;
// Step through the 8 bits in the byte.
reg [2:0] rd_victim_sel_ns, rd_victim_sel_r;
always @(posedge clk) rd_victim_sel_r <= #TCQ rd_victim_sel_ns;
output [2:0] rd_victim_sel;
assign rd_victim_sel = rd_victim_sel_r;
reg [SAMP_CNT_WIDTH-1:0] zero_ns, zero_r, oneeighty_ns, oneeighty_r;
always @(posedge clk) zero_r <= #TCQ zero_ns;
always @(posedge clk) oneeighty_r <= #TCQ oneeighty_ns;
wire [SAMP_CNT_WIDTH-1:0] samp_thresh = (complex_oclkdelay_calib_start
? CMPLX_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_SOLID_THRESH[SAMP_CNT_WIDTH-1:0]);
wire [SAMP_CNT_WIDTH-1:0] samp_half_thresh = (complex_oclkdelay_calib_start
? CMPLX_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]
: SIMP_SAMPS_HALF_THRESH[SAMP_CNT_WIDTH-1:0]);
wire zero_ge_thresh = zero_r >= samp_thresh;
wire zero_le_half_thresh = zero_r <= samp_half_thresh;
wire oneeighty_ge_thresh = oneeighty_r >= samp_thresh;
wire oneeighty_le_half_thresh = oneeighty_r <= samp_half_thresh;
reg [1:0] samp_result_ns, samp_result_r;
always @(posedge clk) samp_result_r <= #TCQ samp_result_ns;
always @(*)
if (rst) samp_result_ns = 'b0;
else begin
samp_result_ns = samp_result_r;
if (samp_valid) begin
if (~samp_result_r[0] && zero_ge_thresh) samp_result_ns[0] = 'b1;
if (samp_result_r[0] && zero_le_half_thresh) samp_result_ns[0] = 'b0;
if (~samp_result_r[1] && oneeighty_ge_thresh) samp_result_ns[1] = 'b1;
if (samp_result_r[1] && oneeighty_le_half_thresh) samp_result_ns[1] = 'b0;
end
end
output [1:0] samp_result;
assign samp_result = samp_result_ns;
reg [0:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
wire [DATA_CNT_WIDTH-1:0] data_cnt = complex_oclkdelay_calib_start
? CMPLX_DATA_CNT[DATA_CNT_WIDTH-1:0]
: SIMP_DATA_CNT[DATA_CNT_WIDTH-1:0];
wire [2:0] rd_victim_end = complex_oclkdelay_calib_start ? 3'h7 : 3'h0;
wire data_end = data_cnt_r == ONE[DATA_CNT_WIDTH-1:0];
wire samp_end = samps_r == ONE[SAMP_CNT_WIDTH-1:0];
// Primary state machine.
always @(*) begin
// Default next state assignments.
agg_samp_ns = agg_samp_r;
data_cnt_ns = data_cnt_r;
oclk_calib_resume_ns = 1'b0;
oneeighty_ns = oneeighty_r;
rd_victim_sel_ns = rd_victim_sel_r;
samp_done_ns = samp_done_r;
samps_ns = samps_r;
sm_ns = sm_r;
zero_ns = zero_r;
if (rst == 1'b1) begin
// RESET next states
sm_ns = /*AK("READY")*/1'd0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/1'd0:begin
agg_samp_ns = NULL;
data_cnt_ns = data_cnt;
oneeighty_ns = 'b0;
zero_ns = 'b0;
rd_victim_sel_ns = 3'b0;
samps_ns = complex_oclkdelay_calib_start ? CMPLX_SAMPS[SAMP_CNT_WIDTH-1:0]
: OCAL_SIMPLE_SCAN_SAMPS[SAMP_CNT_WIDTH-1:0];
if (taps_set) begin
samp_done_ns = 1'b0;
sm_ns = /*AK("AWAITING_DATA")*/1'd1;
oclk_calib_resume_ns = 1'b1;
end
end
/*AL("AWAITING_DATA")*/1'd1:begin
if (phy_rddata_en_1) begin
case (agg_samp_r)
NULL : if (~&match) agg_samp_ns = match;
ZERO, ONEEIGHTY : if (~(agg_samp_r == match || &match)) agg_samp_ns = FUZZ;
FUZZ : ;
endcase // case (agg_samp_r)
if (~data_end) data_cnt_ns = data_cnt_r - ONE[DATA_CNT_WIDTH-1:0];
else begin
data_cnt_ns = data_cnt;
if (rd_victim_end != rd_victim_sel_r) rd_victim_sel_ns = rd_victim_sel_r + 3'h1;
else begin
rd_victim_sel_ns = 3'h0;
if (agg_samp_ns == ZERO) zero_ns = zero_r + ONE[SAMP_CNT_WIDTH-1:0];
if (agg_samp_ns == ONEEIGHTY) oneeighty_ns = oneeighty_r + ONE[SAMP_CNT_WIDTH-1:0];
agg_samp_ns = NULL;
if (~samp_end) samps_ns = samps_r - ONE[SAMP_CNT_WIDTH-1:0];
else samp_done_ns = 1'b1;
end
end
if (samp_done_ns) sm_ns = /*AK("READY")*/1'd0;
else oclk_calib_resume_ns = ~complex_oclkdelay_calib_start && data_end;
end
end
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v4_2_ddr_phy_ocd_samp
// Local Variables:
// verilog-autolabel-prefix: "1'd"
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_oclkdelay_cal #
(parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter DRAM_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter DQ_WIDTH = 64,
parameter MMCM_SAMP_WAIT = 10,
parameter OCAL_SIMPLE_SCAN_SAMPS = 2,
parameter PCT_SAMPS_SOLID = 95,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SCAN_PCT_SAMPS_SOLID = 95,
parameter SIM_CAL_OPTION = "NONE",
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 56,
parameter BYPASS_COMPLEX_OCAL = "FALSE")
(/*AUTOARG*/
// Outputs
wrlvl_final, rd_victim_sel, psincdec, psen, poc_error, po_stg23_sel,
po_stg23_incdec, po_en_stg23, oclkdelay_center_calib_start,
oclkdelay_center_calib_done, oclk_prech_req,
oclk_center_write_resume, oclk_calib_resume,
ocal_num_samples_done_r, lim2init_write_request, dbg_poc,
complex_wrlvl_final, complex_oclkdelay_calib_done,
oclkdelay_calib_cnt, dbg_phy_oclkdelay_cal, dbg_oclkdelay_rd_data,
oclkdelay_calib_done, lim_done, dbg_ocd_lim,
// Inputs
wl_po_fine_cnt, rst, psdone, prech_done, prbs_o,
prbs_ignore_last_bytes, prbs_ignore_first_byte, poc_sample_pd,
po_counter_read_val, phy_rddata_en, phy_rddata, oclkdelay_init_val,
oclkdelay_calib_start, ocal_num_samples_inc, metaQ,
complex_oclkdelay_calib_start, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ...
input complex_oclkdelay_calib_start;// To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v, ...
input metaQ; // To u_poc of mig_7series_v4_2_poc_top.v
input ocal_num_samples_inc; // To u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v
input oclkdelay_calib_start; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
input [5:0] oclkdelay_init_val; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ...
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;// To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v
input phy_rddata_en; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
input [8:0] po_counter_read_val; // To u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v, ...
input poc_sample_pd; // To u_poc of mig_7series_v4_2_poc_top.v
input prbs_ignore_first_byte; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v
input prbs_ignore_last_bytes; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] prbs_o; // To u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v
input prech_done; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ...
input psdone; // To u_poc of mig_7series_v4_2_poc_top.v
input rst; // To u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v, ...
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt; // To u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output complex_oclkdelay_calib_done;// From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
output complex_wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
output [1023:0] dbg_poc; // From u_poc of mig_7series_v4_2_poc_top.v
output lim2init_write_request; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
output ocal_num_samples_done_r;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
output oclk_calib_resume; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v
output oclk_center_write_resume;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
output oclk_prech_req; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
output oclkdelay_center_calib_done;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
output oclkdelay_center_calib_start;// From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
output po_en_stg23; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
output po_stg23_incdec; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
output po_stg23_sel; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
output poc_error; // From u_poc of mig_7series_v4_2_poc_top.v
output psen; // From u_poc of mig_7series_v4_2_poc_top.v
output psincdec; // From u_poc of mig_7series_v4_2_poc_top.v
output [2:0] rd_victim_sel; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v
output wrlvl_final; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire f2o; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire f2z; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire [5:0] fuzz2oneeighty; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire [5:0] fuzz2zero; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire ktap_at_left_edge; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
wire ktap_at_right_edge; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
wire lim2init_prech_req; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire [5:0] lim2ocal_stg3_left_lim; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire [5:0] lim2ocal_stg3_right_lim;// From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2poc_ktap_right; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2poc_rdy; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2stg2_dec; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2stg2_inc; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2stg3_dec; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim2stg3_inc; // From u_ocd_lim of mig_7series_v4_2_ddr_phy_ocd_lim.v
wire lim_start; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire [1:0] match; // From u_ocd_data of mig_7series_v4_2_ddr_phy_ocd_data.v
wire mmcm_edge_detect_done; // From u_poc of mig_7series_v4_2_poc_top.v
wire mmcm_edge_detect_rdy; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
wire mmcm_lbclk_edge_aligned;// From u_poc of mig_7series_v4_2_poc_top.v
wire [1:0] ninety_offsets; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire o2f; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire ocd2stg2_dec; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd2stg2_inc; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd2stg3_dec; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd2stg3_inc; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd_cntlr2stg2_dec; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire ocd_edge_detect_rdy; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd_ktap_left; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd_ktap_right; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire ocd_prech_req; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire [5:0] oneeighty2fuzz; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire phy_rddata_en_1; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire phy_rddata_en_2; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire phy_rddata_en_3; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire po_rdy; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
wire poc_backup; // From u_poc of mig_7series_v4_2_poc_top.v
wire reset_scan; // From u_ocd_cntlr of mig_7series_v4_2_ddr_phy_ocd_cntlr.v
wire [TAPCNTRWIDTH-1:0] rise_lead_right; // From u_poc of mig_7series_v4_2_poc_top.v
wire [TAPCNTRWIDTH-1:0] rise_trail_right; // From u_poc of mig_7series_v4_2_poc_top.v
wire samp_done; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v
wire [1:0] samp_result; // From u_ocd_samp of mig_7series_v4_2_ddr_phy_ocd_samp.v
wire scan_done; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire scan_right; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire scanning_right; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire [5:0] simp_stg3_final_sel; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire [5:0] stg3; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire taps_set; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire use_noise_window; // From u_ocd_po_cntlr of mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v
wire [5:0] wl_po_fine_cnt_sel; // From u_ocd_mux of mig_7series_v4_2_ddr_phy_ocd_mux.v
wire z2f; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
wire [5:0] zero2fuzz; // From u_ocd_edge of mig_7series_v4_2_ddr_phy_ocd_edge.v
// End of automatics
wire [DQS_WIDTH*6-1:0] simp_stg3_final, cmplx_stg3_final;
wire ocal_scan_win_not_found;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
output [255:0] dbg_phy_oclkdelay_cal;
output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data;
output oclkdelay_calib_done;
output lim_done;
output [255:0] dbg_ocd_lim;
// Debug signals
assign dbg_phy_oclkdelay_cal[0] = f2o;
assign dbg_phy_oclkdelay_cal[1] = f2z;
assign dbg_phy_oclkdelay_cal[2] = o2f;
assign dbg_phy_oclkdelay_cal[3] = z2f;
assign dbg_phy_oclkdelay_cal[4+:6] = fuzz2oneeighty;
assign dbg_phy_oclkdelay_cal[10+:6] = fuzz2zero;
assign dbg_phy_oclkdelay_cal[16+:6] = oneeighty2fuzz;
assign dbg_phy_oclkdelay_cal[22+:6] = zero2fuzz;
assign dbg_phy_oclkdelay_cal[28+:3] = oclkdelay_calib_cnt;
assign dbg_phy_oclkdelay_cal[31] = oclkdelay_calib_start;
assign dbg_phy_oclkdelay_cal[32] = lim_done;
assign dbg_phy_oclkdelay_cal[33+:6] =lim2ocal_stg3_left_lim ;
assign dbg_phy_oclkdelay_cal[39+:6] = lim2ocal_stg3_right_lim ;
assign dbg_phy_oclkdelay_cal[45+:8] = po_counter_read_val[8:0];
assign dbg_phy_oclkdelay_cal[53+:54] = simp_stg3_final[DQS_WIDTH*6-1:0];
assign dbg_phy_oclkdelay_cal[107] = ocal_scan_win_not_found;
assign dbg_phy_oclkdelay_cal[108] = oclkdelay_center_calib_start;
assign dbg_phy_oclkdelay_cal[109] = oclkdelay_center_calib_done;
assign dbg_phy_oclkdelay_cal[115:110] = stg3[5:0];
/*mig_7series_v4_2_ddr_phy_ocd_lim AUTO_TEMPLATE(
.TDQSS_DEGREES (),
.wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0]),
.poc2lim_detect_done (mmcm_edge_detect_done),
.poc2lim_fall_align_taps_.* ({TAPCNTRWIDTH{1'b0}}),
.poc2lim_rise_align_taps_lead (rise_lead_right),
.poc2lim_rise_align_taps_trail (rise_trail_right),); */
mig_7series_v4_2_ddr_phy_ocd_lim #
(/*AUTOINSTPARAM*/
// Parameters
.BYPASS_COMPLEX_OCAL (BYPASS_COMPLEX_OCAL),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ),
.TDQSS_DEGREES ()) // Templated
u_ocd_lim
(/*AUTOINST*/
// Outputs
.dbg_ocd_lim (dbg_ocd_lim[255:0]),
.lim2init_prech_req (lim2init_prech_req),
.lim2init_write_request (lim2init_write_request),
.lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]),
.lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]),
.lim2poc_ktap_right (lim2poc_ktap_right),
.lim2poc_rdy (lim2poc_rdy),
.lim2stg2_dec (lim2stg2_dec),
.lim2stg2_inc (lim2stg2_inc),
.lim2stg3_dec (lim2stg3_dec),
.lim2stg3_inc (lim2stg3_inc),
.lim_done (lim_done),
// Inputs
.clk (clk),
.lim_start (lim_start),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
.po_rdy (po_rdy),
.poc2lim_detect_done (mmcm_edge_detect_done), // Templated
.poc2lim_fall_align_taps_lead ({TAPCNTRWIDTH{1'b0}}), // Templated
.poc2lim_fall_align_taps_trail ({TAPCNTRWIDTH{1'b0}}), // Templated
.poc2lim_rise_align_taps_lead (rise_lead_right), // Templated
.poc2lim_rise_align_taps_trail (rise_trail_right), // Templated
.prech_done (prech_done),
.rst (rst),
.simp_stg3_final_sel (simp_stg3_final_sel[5:0]),
.wl_po_fine_cnt (wl_po_fine_cnt_sel[5:0])); // Templated
/*mig_7series_v4_2_poc_top AUTO_TEMPLATE(
.CCENABLE (0),
.LANE_CNT_WIDTH (DQS_CNT_WIDTH),
.SCANFROMRIGHT (1),
.lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]),
.pd_out (metaQ),); */
mig_7series_v4_2_poc_top #
(/*AUTOINSTPARAM*/
// Parameters
.CCENABLE (0), // Templated
.LANE_CNT_WIDTH (DQS_CNT_WIDTH), // Templated
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.PCT_SAMPS_SOLID (PCT_SAMPS_SOLID),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.SCANFROMRIGHT (1), // Templated
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc
(/*AUTOINST*/
// Outputs
.dbg_poc (dbg_poc[1023:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
.poc_error (poc_error),
.psen (psen),
.psincdec (psincdec),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
// Inputs
.clk (clk),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.lane (oclkdelay_calib_cnt[DQS_CNT_WIDTH-1:0]), // Templated
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.ninety_offsets (ninety_offsets[1:0]),
.pd_out (metaQ), // Templated
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.rst (rst),
.use_noise_window (use_noise_window));
/*mig_7series_v4_2_ddr_phy_ocd_mux AUTO_TEMPLATE(
.po_stg3_incdec (),
.po_en_stg3 (),); */
mig_7series_v4_2_ddr_phy_ocd_mux #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.TCQ (TCQ))
u_ocd_mux
(/*AUTOINST*/
// Outputs
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.oclk_prech_req (oclk_prech_req),
.po_en_stg23 (po_en_stg23),
.po_en_stg3 (), // Templated
.po_rdy (po_rdy),
.po_stg23_incdec (po_stg23_incdec),
.po_stg23_sel (po_stg23_sel),
.po_stg3_incdec (), // Templated
.wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]),
// Inputs
.clk (clk),
.lim2init_prech_req (lim2init_prech_req),
.lim2poc_ktap_right (lim2poc_ktap_right),
.lim2poc_rdy (lim2poc_rdy),
.lim2stg2_dec (lim2stg2_dec),
.lim2stg2_inc (lim2stg2_inc),
.lim2stg3_dec (lim2stg3_dec),
.lim2stg3_inc (lim2stg3_inc),
.ocd2stg2_dec (ocd2stg2_dec),
.ocd2stg2_inc (ocd2stg2_inc),
.ocd2stg3_dec (ocd2stg3_dec),
.ocd2stg3_inc (ocd2stg3_inc),
.ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec),
.ocd_edge_detect_rdy (ocd_edge_detect_rdy),
.ocd_ktap_left (ocd_ktap_left),
.ocd_ktap_right (ocd_ktap_right),
.ocd_prech_req (ocd_prech_req),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.rst (rst),
.wl_po_fine_cnt (wl_po_fine_cnt[6*DQS_WIDTH-1:0]));
mig_7series_v4_2_ddr_phy_ocd_data #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK))
u_ocd_data
(/*AUTOINST*/
// Outputs
.match (match[1:0]),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.phy_rddata (phy_rddata[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.phy_rddata_en_1 (phy_rddata_en_1),
.prbs_ignore_first_byte (prbs_ignore_first_byte),
.prbs_ignore_last_bytes (prbs_ignore_last_bytes),
.prbs_o (prbs_o[2*nCK_PER_CLK*DQ_WIDTH-1:0]),
.rst (rst));
mig_7series_v4_2_ddr_phy_ocd_samp #
(/*AUTOINSTPARAM*/
// Parameters
.OCAL_SIMPLE_SCAN_SAMPS (OCAL_SIMPLE_SCAN_SAMPS),
.SCAN_PCT_SAMPS_SOLID (SCAN_PCT_SAMPS_SOLID),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK))
u_ocd_samp
(/*AUTOINST*/
// Outputs
.oclk_calib_resume (oclk_calib_resume),
.rd_victim_sel (rd_victim_sel[2:0]),
.samp_done (samp_done),
.samp_result (samp_result[1:0]),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.match (match[1:0]),
.ocal_num_samples_inc (ocal_num_samples_inc),
.phy_rddata_en_1 (phy_rddata_en_1),
.phy_rddata_en_2 (phy_rddata_en_2),
.reset_scan (reset_scan),
.rst (rst),
.taps_set (taps_set));
mig_7series_v4_2_ddr_phy_ocd_edge #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ))
u_ocd_edge
(/*AUTOINST*/
// Outputs
.f2o (f2o),
.f2z (f2z),
.fuzz2oneeighty (fuzz2oneeighty[5:0]),
.fuzz2zero (fuzz2zero[5:0]),
.o2f (o2f),
.oneeighty2fuzz (oneeighty2fuzz[5:0]),
.scan_right (scan_right),
.z2f (z2f),
.zero2fuzz (zero2fuzz[5:0]),
// Inputs
.clk (clk),
.phy_rddata_en_2 (phy_rddata_en_2),
.reset_scan (reset_scan),
.samp_done (samp_done),
.samp_result (samp_result[1:0]),
.scanning_right (scanning_right),
.stg3 (stg3[5:0]));
/*mig_7series_v4_2_ddr_phy_ocd_cntlr AUTO_TEMPLATE(
.oclk_init_delay_done (),); */
mig_7series_v4_2_ddr_phy_ocd_cntlr #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.TCQ (TCQ))
u_ocd_cntlr
(/*AUTOINST*/
// Outputs
.complex_oclkdelay_calib_done (complex_oclkdelay_calib_done),
.complex_wrlvl_final (complex_wrlvl_final),
.lim_start (lim_start),
.ocd_cntlr2stg2_dec (ocd_cntlr2stg2_dec),
.ocd_prech_req (ocd_prech_req),
.oclk_init_delay_done (), // Templated
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.oclkdelay_calib_done (oclkdelay_calib_done),
.phy_rddata_en_1 (phy_rddata_en_1),
.phy_rddata_en_2 (phy_rddata_en_2),
.phy_rddata_en_3 (phy_rddata_en_3),
.reset_scan (reset_scan),
.wrlvl_final (wrlvl_final),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.lim_done (lim_done),
.oclkdelay_calib_start (oclkdelay_calib_start),
.phy_rddata_en (phy_rddata_en),
.po_counter_read_val (po_counter_read_val[8:0]),
.po_rdy (po_rdy),
.prech_done (prech_done),
.rst (rst),
.scan_done (scan_done));
mig_7series_v4_2_ddr_phy_ocd_po_cntlr #
(/*AUTOINSTPARAM*/
// Parameters
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.SAMPLES (SAMPLES),
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK))
u_ocd_po_cntlr
(.cmplx_stg3_final (cmplx_stg3_final[DQS_WIDTH*6-1:0]),
.ocal_scan_win_not_found (ocal_scan_win_not_found),
.simp_stg3_final (simp_stg3_final[DQS_WIDTH*6-1:0]),
/*AUTOINST*/
// Outputs
.ninety_offsets (ninety_offsets[1:0]),
.ocal_num_samples_done_r (ocal_num_samples_done_r),
.ocd2stg2_dec (ocd2stg2_dec),
.ocd2stg2_inc (ocd2stg2_inc),
.ocd2stg3_dec (ocd2stg3_dec),
.ocd2stg3_inc (ocd2stg3_inc),
.ocd_edge_detect_rdy (ocd_edge_detect_rdy),
.ocd_ktap_left (ocd_ktap_left),
.ocd_ktap_right (ocd_ktap_right),
.oclk_center_write_resume (oclk_center_write_resume),
.oclkdelay_center_calib_done (oclkdelay_center_calib_done),
.oclkdelay_center_calib_start (oclkdelay_center_calib_start),
.scan_done (scan_done),
.scanning_right (scanning_right),
.simp_stg3_final_sel (simp_stg3_final_sel[5:0]),
.stg3 (stg3[5:0]),
.taps_set (taps_set),
.use_noise_window (use_noise_window),
// Inputs
.clk (clk),
.complex_oclkdelay_calib_start (complex_oclkdelay_calib_start),
.f2o (f2o),
.f2z (f2z),
.fuzz2oneeighty (fuzz2oneeighty[5:0]),
.fuzz2zero (fuzz2zero[5:0]),
.lim2ocal_stg3_left_lim (lim2ocal_stg3_left_lim[5:0]),
.lim2ocal_stg3_right_lim (lim2ocal_stg3_right_lim[5:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.o2f (o2f),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt[DQS_CNT_WIDTH:0]),
.oclkdelay_init_val (oclkdelay_init_val[5:0]),
.oneeighty2fuzz (oneeighty2fuzz[5:0]),
.phy_rddata_en_3 (phy_rddata_en_3),
.po_counter_read_val (po_counter_read_val[8:0]),
.po_rdy (po_rdy),
.poc_backup (poc_backup),
.reset_scan (reset_scan),
.rst (rst),
.samp_done (samp_done),
.scan_right (scan_right),
.wl_po_fine_cnt_sel (wl_po_fine_cnt_sel[5:0]),
.z2f (z2f),
.zero2fuzz (zero2fuzz[5:0]));
endmodule // mig_7series_v4_2_ddr_phy_oclkdelay_cal
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
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// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_prbs_rdlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// PRBS Read leveling calibration logic
// NOTES:
// 1. Window detection with PRBS pattern.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_prbs_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter PRBS_WIDTH = 8, // PRBS generator output width
parameter FIXED_VICTIM = "TRUE", // No victim rotation when "TRUE"
parameter FINE_PER_BIT = "ON",
parameter CENTER_COMP_MODE = "ON",
parameter PI_VAL_ADJ = "ON"
)
(
input clk,
input rst,
// Calibration status, control signals
input prbs_rdlvl_start,
(* max_fanout = 100 *) output reg prbs_rdlvl_done,
output reg prbs_last_byte_done,
output reg prbs_rdlvl_prech_req,
input complex_sample_cnt_inc,
input prech_done,
input phy_if_empty,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
//Expected data from PRBS generator
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data,
// Decrement initial Phaser_IN Fine tap delay
input [5:0] pi_counter_read_val,
// Stage 1 calibration outputs
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output [255:0] dbg_prbs_rdlvl,
output [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt,
output reg [2:0] rd_victim_sel,
output reg complex_victim_inc,
output reg reset_rd_addr,
output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output reg [DRAM_WIDTH-1:0] fine_delay_incdec_pb, //fine_delay decreament per bit
output reg fine_delay_sel, //fine delay selection - actual update of fine delay
output reg num_samples_done_r,
input complex_act_start, //read is done. ready for PI movement
output complex_init_pi_dec_done, //Initial PI incdec is done. ready for start
output reg complex_pi_incdec_done //PI incdec is done. ready for Read
);
localparam [5:0] PRBS_IDLE = 6'h00;
localparam [5:0] PRBS_NEW_DQS_WAIT = 6'h01;
localparam [5:0] PRBS_PAT_COMPARE = 6'h02;
localparam [5:0] PRBS_DEC_DQS = 6'h03;
localparam [5:0] PRBS_DEC_DQS_WAIT = 6'h04;
localparam [5:0] PRBS_INC_DQS = 6'h05;
localparam [5:0] PRBS_INC_DQS_WAIT = 6'h06;
localparam [5:0] PRBS_CALC_TAPS = 6'h07;
localparam [5:0] PRBS_NEXT_DQS = 6'h08;
localparam [5:0] PRBS_NEW_DQS_PREWAIT = 6'h09;
localparam [5:0] PRBS_DONE = 6'h0A;
localparam [5:0] PRBS_CALC_TAPS_PRE = 6'h0B;
localparam [5:0] PRBS_CALC_TAPS_WAIT = 6'h0C;
localparam [5:0] FINE_PI_DEC = 6'h0D; //go back to all fail or back to center
localparam [5:0] FINE_PI_DEC_WAIT = 6'h0E; //wait for PI tap dec settle
localparam [5:0] FINE_PI_INC = 6'h0F; //increse up to 1 fail
localparam [5:0] FINE_PI_INC_WAIT = 6'h10; //wait for PI tap int settle
localparam [5:0] FINE_PAT_COMPARE_PER_BIT = 6'h11; //compare per bit error and check left/right/gain/loss
localparam [5:0] FINE_CALC_TAPS = 6'h12; //setup fine_delay_incdec_pb for better window size
localparam [5:0] FINE_CALC_TAPS_WAIT = 6'h13; //wait for ROM value for dec cnt
localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_INC = 6'h14; //wait for read is done before PI inc
localparam [5:0] RD_DONE_WAIT_FOR_PI_INC_DEC = 6'h15; //wait for read is done before PI dec
localparam [11:0] NUM_SAMPLES_CNT = (SIM_CAL_OPTION == "NONE") ? 'd12 : 12'h001; //MG from 50
localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001;
localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001;
//minimum valid window for centering
localparam MIN_WIN = 8;
localparam [MIN_WIN-1:0] MATCH_ALL_ONE = {MIN_WIN{1'b1}};
localparam [MIN_WIN-1:0] MIN_PASS = {MIN_WIN{1'b0}}; //8'b00000000
localparam [MIN_WIN-1:0] MIN_LEFT = {1'b1,{{MIN_WIN-1}{1'b0}}}; //8'b10000000
wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing;
reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r;
reg [DQS_CNT_WIDTH:0] prbs_dqs_cnt_r;
reg prbs_prech_req_r;
reg [5:0] prbs_state_r;
reg [5:0] prbs_state_r1;
reg wait_state_cnt_en_r;
reg [3:0] wait_state_cnt_r;
reg cnt_wait_state;
reg err_chk_invalid;
// reg found_edge_r;
reg prbs_found_1st_edge_r;
reg prbs_found_2nd_edge_r;
reg [5:0] prbs_1st_edge_taps_r;
// reg found_stable_eye_r;
reg [5:0] prbs_dqs_tap_cnt_r;
reg [5:0] prbs_dec_tap_calc_plus_3;
reg [5:0] prbs_dec_tap_calc_minus_3;
reg prbs_dqs_tap_limit_r;
reg [5:0] prbs_inc_tap_cnt;
reg [5:0] prbs_dec_tap_cnt;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r1;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r1;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r2;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r2;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r3;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r4;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r4;
reg mux_rd_valid_r;
reg rd_valid_r1;
reg rd_valid_r2;
reg rd_valid_r3;
reg new_cnt_dqs_r;
reg prbs_tap_en_r;
reg prbs_tap_inc_r;
reg pi_en_stg2_f_timing;
reg pi_stg2_f_incdec_timing;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
wire [DQ_WIDTH-1:0] compare_data_r0;
wire [DQ_WIDTH-1:0] compare_data_f0;
wire [DQ_WIDTH-1:0] compare_data_r1;
wire [DQ_WIDTH-1:0] compare_data_f1;
wire [DQ_WIDTH-1:0] compare_data_r2;
wire [DQ_WIDTH-1:0] compare_data_f2;
wire [DQ_WIDTH-1:0] compare_data_r3;
wire [DQ_WIDTH-1:0] compare_data_f3;
reg [DRAM_WIDTH-1:0] compare_data_rise0_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall0_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise1_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall1_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise2_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall2_r1;
reg [DRAM_WIDTH-1:0] compare_data_rise3_r1;
reg [DRAM_WIDTH-1:0] compare_data_fall3_r1;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg [5:0] prbs_2nd_edge_taps_r;
// reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
reg [5:0] rdlvl_cpt_tap_cnt;
reg prbs_rdlvl_start_r;
reg compare_err;
reg compare_err_r0;
reg compare_err_f0;
reg compare_err_r1;
reg compare_err_f1;
reg compare_err_r2;
reg compare_err_f2;
reg compare_err_r3;
reg compare_err_f3;
reg compare_err_latch;
reg samples_cnt1_en_r;
reg samples_cnt2_en_r;
reg [11:0] samples_cnt_r;
reg num_samples_done_ind; //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync
reg [DQS_WIDTH-1:0] prbs_tap_mod;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
//reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
//**************************************************************************
// signals for per-bit algorithm of fine_delay calculations
//**************************************************************************
reg [6*DRAM_WIDTH-1:0] left_edge_pb; //left edge value per bit
reg [6*DRAM_WIDTH-1:0] right_edge_pb; //right edge value per bit
reg [MIN_WIN*DRAM_WIDTH-1:0] match_flag_pb; //5 consecutive match flag per bit
reg [MIN_WIN-1:0] match_flag_and; //5 consecute match flag of all bits (1: all bit fail)
reg [MIN_WIN-1:0] match_flag_or; //5 consecute match flag of all bits (1: any bit fail)
reg [DRAM_WIDTH-1:0] left_edge_found_pb; //left_edge found per bit - use for loss calculation
reg [DRAM_WIDTH-1:0] left_edge_updated; //left edge was updated for this PI tap - used for largest left edge /ref bit update
reg [DRAM_WIDTH-1:0] right_edge_found_pb; //right_edge found per bit - use for gail calulation and smallest right edge update
reg right_edge_found; //smallest right_edge found
reg [DRAM_WIDTH*6-1:0] left_loss_pb; //left_edge loss per bit
reg [DRAM_WIDTH*6-1:0] right_gain_pb; //right_edge gain per bit
reg [DRAM_WIDTH-1:0] ref_bit; //bit number which has largest left edge (with smaller right edge)
reg [DRAM_WIDTH-1:0] bit_cnt; //bit number used to calculate ref bit
reg [DRAM_WIDTH-1:0] ref_bit_per_bit; //bit flags which have largest left edge
reg [5:0] ref_right_edge; //ref_bit right edge - keep the smallest edge of ref bits
reg [5:0] largest_left_edge; //biggest left edge of per bit - will be left edge of byte
reg [5:0] smallest_right_edge; //smallest right edge of per bit - will be right edge of byte
reg [5:0] fine_pi_dec_cnt; //Phase In tap decrement count (to go back to '0' or center)
reg [6:0] center_calc; //used for calculate the dec tap for centering
reg [5:0] right_edge_ref; //ref_bit right edge
reg [5:0] left_edge_ref; //ref_bit left edge
reg [DRAM_WIDTH-1:0] compare_err_pb; //compare error per bit
reg [DRAM_WIDTH-1:0] compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge
reg compare_err_pb_and; //indicate all bit fail
reg compare_err_pb_or; //indicate any bit fail
reg fine_inc_stage; //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit)
reg [1:0] stage_cnt; //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage)
wire fine_calib; //turn on/off fine delay calibration
reg [5:0] mem_out_dec;
reg [5:0] dec_cnt;
reg fine_dly_error; //indicate it has wrong left/right edge
reg edge_det_error; //indicate it has wrong left/right edge
wire center_comp;
wire pi_adj;
reg no_err_win_detected;
reg no_err_win_detected_latch;
reg [1:0] valid_window_cnt; //number of valid window in the scan
reg double_window_ind; //indication of double window
//if inital PI dec is not done, init SM should wait until it is done
reg complex_init_pi_dec_done_r; //if inital PI dec is not done, init SM should wait until it is done
wire complex_rdlvl_err;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
//fine delay turn on
assign fine_calib = (FINE_PER_BIT=="ON")? 1:0;
assign center_comp = (CENTER_COMP_MODE == "ON")? 1: 0;
assign pi_adj = (PI_VAL_ADJ == "ON")?1:0;
//Debug error flag
assign complex_rdlvl_err = fine_dly_error | edge_det_error;
//initial dec is only happening for per-bit
assign complex_init_pi_dec_done = fine_calib? complex_init_pi_dec_done_r : 1'b1;
assign dbg_prbs_rdlvl[0+:6] = left_edge_pb[0+:6];
assign dbg_prbs_rdlvl[7:6] = left_loss_pb[0+:2];
assign dbg_prbs_rdlvl[8+:6] = left_edge_pb[6+:6];
assign dbg_prbs_rdlvl[15:14] = left_loss_pb[6+:2];
assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ;
assign dbg_prbs_rdlvl[23:22] = left_loss_pb[12+:2];
assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ;
assign dbg_prbs_rdlvl[31:30] = left_loss_pb[18+:2];
assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6];
assign dbg_prbs_rdlvl[39:38] = left_loss_pb[24+:2];
assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6];
assign dbg_prbs_rdlvl[47:46] = left_loss_pb[30+:2];
assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6];
assign dbg_prbs_rdlvl[55:54] = left_loss_pb[36+:2];
assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6];
assign dbg_prbs_rdlvl[63:62] = left_loss_pb[42+:2];
assign dbg_prbs_rdlvl[64+:6] = right_edge_pb[0+:6];
assign dbg_prbs_rdlvl[71:70] = right_gain_pb[0+:2];
assign dbg_prbs_rdlvl[72+:6] = right_edge_pb[6+:6] ;
assign dbg_prbs_rdlvl[79:78] = right_gain_pb[6+:2];
assign dbg_prbs_rdlvl[80+:6] = right_edge_pb[12+:6];
assign dbg_prbs_rdlvl[87:86] = right_gain_pb[12+:2];
assign dbg_prbs_rdlvl[88+:6] = right_edge_pb[18+:6];
assign dbg_prbs_rdlvl[95:94] = right_gain_pb[18+:2];
assign dbg_prbs_rdlvl[96+:6] = right_edge_pb[24+:6];
assign dbg_prbs_rdlvl[103:102] = right_gain_pb[24+:2];
assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6];
assign dbg_prbs_rdlvl[111:110] = right_gain_pb[30+:2];
assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6];
assign dbg_prbs_rdlvl[119:118] = right_gain_pb[36+:2];
assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6];
assign dbg_prbs_rdlvl[127:126] = right_gain_pb[42+:2];
assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val;
assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r;
assign dbg_prbs_rdlvl[140] = prbs_found_1st_edge_r;
assign dbg_prbs_rdlvl[141] = prbs_found_2nd_edge_r;
assign dbg_prbs_rdlvl[142] = compare_err;
assign dbg_prbs_rdlvl[143] = phy_if_empty;
assign dbg_prbs_rdlvl[144] = prbs_rdlvl_start;
assign dbg_prbs_rdlvl[145] = prbs_rdlvl_done;
assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r;
assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6];
assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]};
assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ;
assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0];
assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0];
assign dbg_prbs_rdlvl[184] = rd_valid_r2;
assign dbg_prbs_rdlvl[185] = compare_err_r0;
assign dbg_prbs_rdlvl[186] = compare_err_f0;
assign dbg_prbs_rdlvl[187] = compare_err_r1;
assign dbg_prbs_rdlvl[188] = compare_err_f1;
assign dbg_prbs_rdlvl[189] = compare_err_r2;
assign dbg_prbs_rdlvl[190] = compare_err_f2;
assign dbg_prbs_rdlvl[191] = compare_err_r3;
assign dbg_prbs_rdlvl[192] = compare_err_f3;
assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb;
assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb;
assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ;
assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ;
assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb;
assign dbg_prbs_rdlvl[229] = fine_delay_sel;
assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r;
assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt;
assign dbg_prbs_rdlvl[244+:5] = match_flag_and[4:0];
assign dbg_prbs_rdlvl[249+:2] = stage_cnt;
assign dbg_prbs_rdlvl[251] = fine_inc_stage;
assign dbg_prbs_rdlvl[252] = compare_err_pb_and;
assign dbg_prbs_rdlvl[253] = right_edge_found;
assign dbg_prbs_rdlvl[254] = complex_rdlvl_err;
assign dbg_prbs_rdlvl[255] = double_window_ind;
//**************************************************************************
// Record first and second edges found during calibration
//**************************************************************************
generate
always @(posedge clk)
if (rst) begin
dbg_prbs_first_edge_taps <= #TCQ 'b0;
dbg_prbs_second_edge_taps <= #TCQ 'b0;
end else if (prbs_state_r == PRBS_CALC_TAPS) begin
// Record tap counts of first and second edge edges during
// calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (prbs_found_1st_edge_r)
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_1st_edge_taps_r;
if (prbs_found_2nd_edge_r)
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_2nd_edge_taps_r;
end else if (prbs_state_r == FINE_CALC_TAPS) begin
if(stage_cnt == 'd2) begin
dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ largest_left_edge;
dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ smallest_right_edge;
end
end
endgenerate
//double window indication flag
always @ (posedge clk)
if (rst) double_window_ind <= #TCQ 1'd0;
else double_window_ind <= #TCQ double_window_ind? 1'b1: (valid_window_cnt > 1);
//padded calculation
always @ (smallest_right_edge or largest_left_edge)
center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge};
//***************************************************************************
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else begin: rd_data_div2_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign compare_data_r2 = 'h0;
assign compare_data_f2 = 'h0;
assign compare_data_r3 = 'h0;
assign compare_data_f3 = 'h0;
end
endgenerate
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
//Compare data
compare_data_rise0_r1[mux_i] <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall0_r1[mux_i] <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise1_r1[mux_i] <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall1_r1[mux_i] <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise2_r1[mux_i] <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall2_r1[mux_i] <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_rise3_r1[mux_i] <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
compare_data_fall3_r1[mux_i] <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
endgenerate
generate
genvar muxr2_i;
if (nCK_PER_CLK == 4) begin: gen_mux_div4
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i];
mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i];
mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i];
mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i];
end
//pipeline stage
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i];
mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i];
mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i];
mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i];
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i];
mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i];
mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i];
mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_div2
for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2
always @(posedge clk) begin
if (mux_rd_valid_r) begin
mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
mux_rd_rise2_r2[muxr2_i] <= 'h0;
mux_rd_fall2_r2[muxr2_i] <= 'h0;
mux_rd_rise3_r2[muxr2_i] <= 'h0;
mux_rd_fall3_r2[muxr2_i] <= 'h0;
end
mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
mux_rd_rise2_r3[muxr2_i] <= 'h0;
mux_rd_fall2_r3[muxr2_i] <= 'h0;
mux_rd_rise3_r3[muxr2_i] <= 'h0;
mux_rd_fall3_r3[muxr2_i] <= 'h0;
//pipeline stage
mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
mux_rd_rise2_r4[muxr2_i] <= 'h0;
mux_rd_fall2_r4[muxr2_i] <= 'h0;
mux_rd_rise3_r4[muxr2_i] <= 'h0;
mux_rd_fall3_r4[muxr2_i] <= 'h0;
end
end
end
endgenerate
// Registered signal indicates when mux_rd_rise/fall_r is valid
always @(posedge clk) begin
mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start;
rd_valid_r1 <= #TCQ mux_rd_valid_r;
rd_valid_r2 <= #TCQ rd_valid_r1;
rd_valid_r3 <= #TCQ rd_valid_r2;
end
// Counter counts # of samples compared
// Reset sample counter when not "sampling"
// Otherwise, count # of samples compared
// Same counter is shared for three samples checked
always @(posedge clk)
if (rst)
samples_cnt_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
samples_cnt_r <= #TCQ 'b0;
end else if (complex_sample_cnt_inc) begin
samples_cnt_r <= #TCQ samples_cnt_r + 1;
/*if (!rd_valid_r1 ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(samples_cnt_r == NUM_SAMPLES_CNT) ||
(samples_cnt_r == NUM_SAMPLES_CNT1))
samples_cnt_r <= #TCQ 'b0;
else if (rd_valid_r1 &&
(((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) ||
((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r)))
samples_cnt_r <= #TCQ samples_cnt_r + 1;*/
end
// Count #2 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt1_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt1_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1)
samples_cnt1_en_r <= #TCQ 1'b1;
end
// Counter #3 enable generation
// Assert when correct number of samples compared
always @(posedge clk)
if (rst)
samples_cnt2_en_r <= #TCQ 1'b0;
else begin
if ((prbs_state_r == PRBS_IDLE) ||
(prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS) ||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
samples_cnt2_en_r <= #TCQ 1'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r)
samples_cnt2_en_r <= #TCQ 1'b1;
end
// Victim selection logic
always @(posedge clk)
if (rst)
rd_victim_sel <= #TCQ 'd0;
else if (num_samples_done_r)
rd_victim_sel <= #TCQ 'd0;
else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
if (rd_victim_sel < 'd7)
rd_victim_sel <= #TCQ rd_victim_sel + 1;
end
// Output row count increment pulse to phy_init
always @(posedge clk)
if (rst)
complex_victim_inc <= #TCQ 1'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
complex_victim_inc <= #TCQ 1'b1;
else
complex_victim_inc <= #TCQ 1'b0;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if (samples_cnt_r == NUM_SAMPLES_CNT)
num_samples_done_r <= #TCQ 1'b1;
end else begin: victim_not_fixed
always @(posedge clk)
if (rst)
num_samples_done_r <= #TCQ 1'b0;
else if ((prbs_state_r == PRBS_DEC_DQS) ||
(prbs_state_r == PRBS_INC_DQS)||
(prbs_state_r == FINE_PI_INC) ||
(prbs_state_r == FINE_PI_DEC))
num_samples_done_r <= #TCQ 'b0;
else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7))
num_samples_done_r <= #TCQ 1'b1;
end
endgenerate
//***************************************************************************
// Compare Read Data for the byte being Leveled with Expected data from PRBS
// generator. Resulting compare_err signal used to determine read data valid
// edge.
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: cmp_err_4to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
compare_err_r2 <= #TCQ 1'b0;
compare_err_f2 <= #TCQ 1'b0;
compare_err_r3 <= #TCQ 1'b0;
compare_err_f3 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err_r2 <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1);
compare_err_f2 <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1);
compare_err_r3 <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1);
compare_err_f3 <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1 |
compare_err_r2 | compare_err_f2 |
compare_err_r3 | compare_err_f3);
end
end
end else begin: cmp_err_2to1
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == PRBS_INC_DQS) || (prbs_state_r == PRBS_DEC_DQS)) begin
compare_err <= #TCQ 1'b0;
compare_err_r0 <= #TCQ 1'b0;
compare_err_f0 <= #TCQ 1'b0;
compare_err_r1 <= #TCQ 1'b0;
compare_err_f1 <= #TCQ 1'b0;
end else if (rd_valid_r2) begin
compare_err_r0 <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
compare_err_f0 <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
compare_err_r1 <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
compare_err_f1 <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
compare_err <= #TCQ (compare_err_r0 | compare_err_f0 |
compare_err_r1 | compare_err_f1);
end
end
end
endgenerate
//Sticky bit compare_err
always @ (posedge clk)
if (prbs_state_r == PRBS_PAT_COMPARE)
compare_err_latch <= #TCQ compare_err? 1'b1: compare_err_latch;
else
compare_err_latch <= #TCQ 1'b0;
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// read calibration
//***************************************************************************
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (prbs_tap_en_r) begin
// Change only specified DQS
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r;
end else begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;
pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
prbs_rdlvl_prech_req <= #TCQ 1'b0;
else
prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_tap_cnt_r <= #TCQ 'b0;
rdlvl_cpt_tap_cnt <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dqs_tap_cnt_r <= #TCQ pi_counter_read_val;
rdlvl_cpt_tap_cnt <= #TCQ pi_counter_read_val;
end else if (prbs_tap_en_r) begin
if (prbs_tap_inc_r)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else if (prbs_dqs_tap_cnt_r != 'd0)
prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
end
always @(posedge clk)
if (rst) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b0;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b0;
end else if (new_cnt_dqs_r) begin
prbs_dec_tap_calc_plus_3 <= #TCQ 'b000011;
prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100;
end else begin
prbs_dec_tap_calc_plus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt + 3);
prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r - rdlvl_cpt_tap_cnt - 3);
end
always @(posedge clk)
if (rst || new_cnt_dqs_r)
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
else if (prbs_dqs_tap_cnt_r == 6'd63)
prbs_dqs_tap_limit_r <= #TCQ 1'b1;
else
prbs_dqs_tap_limit_r <= #TCQ 1'b0;
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*prbs_dqs_cnt_r.
// replacing this with two left shifts + one left shift to avoid
// DSP multiplier.
assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r};
always @(posedge clk)
prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing;
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
prbs_final_dqs_tap_cnt_r <= #TCQ 'b0;
end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin
prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6]
<= #TCQ prbs_dqs_tap_cnt_r;
end
end
//*****************************************************************
always @(posedge clk) begin
prbs_state_r1 <= #TCQ prbs_state_r;
prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start;
end
// Wait counter for wait states
always @(posedge clk)
if ((prbs_state_r == PRBS_NEW_DQS_WAIT) ||
(prbs_state_r == PRBS_INC_DQS_WAIT) ||
(prbs_state_r == PRBS_DEC_DQS_WAIT) ||
(prbs_state_r == FINE_PI_DEC_WAIT) ||
(prbs_state_r == FINE_PI_INC_WAIT) ||
(prbs_state_r == PRBS_NEW_DQS_PREWAIT))
wait_state_cnt_en_r <= #TCQ 1'b1;
else
wait_state_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_state_cnt_en_r) begin
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b0;
end else begin
if (wait_state_cnt_r < 'd15) begin
wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1;
cnt_wait_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_state_cnt_r <= #TCQ 'b0;
cnt_wait_state <= #TCQ 1'b1;
end
end
always @ (posedge clk)
err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14);
//*****************************************************************
// compare error checking per-bit
//****************************************************************
generate
genvar pb_i;
if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
//prevent error check during PI inc/dec and wait
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) |
(mux_rd_rise2_r3[pb_i] != compare_data_rise2_r1[pb_i]) |
(mux_rd_fall2_r3[pb_i] != compare_data_fall2_r1[pb_i]) |
(mux_rd_rise3_r3[pb_i] != compare_data_rise3_r1[pb_i]) |
(mux_rd_fall3_r3[pb_i] != compare_data_fall3_r1[pb_i]) ;
end //always
end //for
end else begin: cmp_err_pb_2to1
for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
always @ (posedge clk) begin
if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
(err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
compare_err_pb[pb_i] <= #TCQ 1'b0;
else if (rd_valid_r2)
compare_err_pb[pb_i] <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
(mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
(mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
(mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) ;
end //always
end //for
end //if
endgenerate
//generate stick error bit - left/right edge
generate
genvar pb_r;
for(pb_r=0; pb_r<DRAM_WIDTH; pb_r=pb_r+1) begin
always @ (posedge clk) begin
if((prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
(~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT))))
compare_err_pb_latch_r[pb_r] <= #TCQ 1'b0;
else
compare_err_pb_latch_r[pb_r] <= #TCQ compare_err_pb[pb_r]? 1'b1:compare_err_pb_latch_r[pb_r];
end
end
endgenerate
//checking all/any bit has error
always @ (posedge clk) begin
if(rst | (prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
(~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT)))) begin
compare_err_pb_and <= #TCQ 1'b0;
compare_err_pb_or <= #TCQ 1'b0;
end
else begin
compare_err_pb_and <= #TCQ &compare_err_pb? 1'b1: compare_err_pb_and;
compare_err_pb_or <= #TCQ |compare_err_pb? 1'b1: compare_err_pb_or;
end
end
//in stage 0, if left edge found, update ref_bit (one hot)
always @ (posedge clk) begin
if (rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
ref_bit_per_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_PI_INC) && (stage_cnt=='b0)) begin
if(|left_edge_updated) ref_bit_per_bit <= #TCQ left_edge_updated;
end
end
//ref bit with samllest right edge
//if bit 1 and 3 are set to ref_bit_per_bit but bit 1 has smaller right edge, bit is selected as ref_bit
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
bit_cnt <= #TCQ 'd0;
ref_right_edge <= #TCQ 6'h3f;
ref_bit <= #TCQ 'd0;
end else if ((prbs_state_r == FINE_CALC_TAPS_WAIT) && (stage_cnt == 'b0) && (bit_cnt < DRAM_WIDTH)) begin
bit_cnt <= #TCQ bit_cnt +'b1;
if ((ref_bit_per_bit[bit_cnt]==1'b1) && (right_edge_pb[bit_cnt*6+:6]<= ref_right_edge)) begin
ref_bit <= #TCQ bit_cnt;
ref_right_edge <= #TCQ right_edge_pb[bit_cnt*6+:6];
end
end
end
//pipe lining for reference bit left/right edge
always @ (posedge clk) begin
left_edge_ref <= #TCQ left_edge_pb[ref_bit*6+:6];
right_edge_ref <= #TCQ right_edge_pb[ref_bit*6+:6];
end
//left_edge/right_edge/left_loss/right_gain update
generate
genvar eg;
for(eg=0; eg<DRAM_WIDTH; eg = eg+1) begin
always @ (posedge clk) begin
if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE; //8'hff
left_edge_pb[eg*6+:6] <= #TCQ 'b0;
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
left_edge_updated[eg] <= #TCQ 'b0;
end else begin
if((prbs_state_r == FINE_PAT_COMPARE_PER_BIT) && num_samples_done_r) begin
//left edge is updated when match flag becomes 10000000 (1 fail ,8 success)
if(match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_LEFT && compare_err_pb_latch_r[eg]==0) begin
left_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1);
left_edge_found_pb[eg] <= #TCQ 1'b1; //used for update largest_left_edge
left_edge_updated[eg] <= #TCQ 1'b1;
//check the loss of bit - update only for left edge found
if(~left_edge_found_pb[eg])
left_loss_pb[eg*6+:6] <= #TCQ (left_edge_ref > prbs_dqs_tap_cnt_r -(MIN_WIN-1))? 'd0
: prbs_dqs_tap_cnt_r-(MIN_WIN-1)-left_edge_ref;
//right edge is updated when match flag becomes 000000001 (8 success, 1 fail)
end else if (match_flag_pb[eg*MIN_WIN+:MIN_WIN]== MIN_PASS && compare_err_pb_latch_r[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//check the gain of bit - update only for right edge found
if(~right_edge_found_pb[eg])
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)?
((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]):
((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]);
//no right edge found
end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin
right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
right_edge_found_pb[eg] <= #TCQ 1'b1;
//right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge)
right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])?
(right_edge_ref - right_edge_pb[eg*6+:6]) : 0;
end
//update match flag - shift and update
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ {match_flag_pb[(eg*MIN_WIN)+:(MIN_WIN-1)],compare_err_pb_latch_r[eg]};
end else if (prbs_state_r == FINE_PI_DEC) begin
left_edge_found_pb[eg] <= #TCQ 1'b0;
right_edge_found_pb[eg] <= #TCQ 1'b0;
left_loss_pb[eg*6+:6] <= #TCQ 'b0;
right_gain_pb[eg*6+:6] <= #TCQ 'b0;
match_flag_pb[eg*MIN_WIN+:MIN_WIN] <= #TCQ MATCH_ALL_ONE ; //new fix
left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge
end else if (prbs_state_r == FINE_PI_INC) begin
left_edge_updated[eg] <= #TCQ 'b0; //used only for update largest ref_bit and largest_left_edge
end
end
end //always
end //for
endgenerate
//update fine_delay according to loss/gain value per bit
generate
genvar f_pb;
for(f_pb=0; f_pb<DRAM_WIDTH; f_pb=f_pb+1) begin
always @ (posedge clk) begin
if(rst | prbs_state_r == PRBS_NEW_DQS_WAIT ) begin
fine_delay_incdec_pb[f_pb] <= #TCQ 1'b0;
end else if((prbs_state_r == FINE_CALC_TAPS_WAIT) && (bit_cnt == DRAM_WIDTH)) begin
if(stage_cnt == 'd0) fine_delay_incdec_pb[f_pb] <= #TCQ (f_pb==ref_bit)? 1'b0:1'b1; //only for initial stage
else if(stage_cnt == 'd1) fine_delay_incdec_pb[f_pb] <= #TCQ (right_gain_pb[f_pb*6+:6]>left_loss_pb[f_pb*6+:6])?1'b1:1'b0;
end
end
end
endgenerate
//fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3)
always @ (posedge clk) begin
if (rst)
fine_inc_stage <= #TCQ 'b1;
else
fine_inc_stage <= #TCQ (stage_cnt!='d3);
end
//*****************************************************************
always @(posedge clk)
if (rst) begin
prbs_dqs_cnt_r <= #TCQ 'b0;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ PRBS_IDLE;
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_inc_tap_cnt <= #TCQ 'b0;
prbs_dec_tap_cnt <= #TCQ 'b0;
new_cnt_dqs_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL")
prbs_rdlvl_done <= #TCQ 1'b1;
else
prbs_rdlvl_done <= #TCQ 1'b0;
prbs_2nd_edge_taps_r <= #TCQ 6'bxxxxxx;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_tap_mod <= #TCQ 'd0;
reset_rd_addr <= #TCQ 'b0;
fine_pi_dec_cnt <= #TCQ 'b0;
match_flag_and <= #TCQ MATCH_ALL_ONE;
match_flag_or <= #TCQ MATCH_ALL_ONE;
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
valid_window_cnt <= 2'd0;
stage_cnt <= #TCQ 2'b00;
right_edge_found <= #TCQ 1'b0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
num_samples_done_ind <= #TCQ 'b0;
fine_delay_sel <= #TCQ 'b0;
fine_dly_error <= #TCQ 'b0;
edge_det_error <= #TCQ 'b0;
complex_pi_incdec_done <= #TCQ 1'b0;
complex_init_pi_dec_done_r <= #TCQ 1'b0;
end else begin
case (prbs_state_r)
PRBS_IDLE: begin
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin
if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin
prbs_state_r <= #TCQ PRBS_DONE;
reset_rd_addr <= #TCQ 1'b1;
end else begin
new_cnt_dqs_r <= #TCQ 1'b1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
PRBS_NEW_DQS_WAIT: begin
reset_rd_addr <= #TCQ 'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_prech_req_r <= #TCQ 1'b0;
stage_cnt <= #TCQ 2'b0;
match_flag_and <= #TCQ MATCH_ALL_ONE;
match_flag_or <= #TCQ MATCH_ALL_ONE;
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
if (cnt_wait_state) begin
new_cnt_dqs_r <= #TCQ 1'b0;
prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE;
//For normal, it doesn't have initial pi incdec
complex_pi_incdec_done <= #TCQ fine_calib? complex_pi_incdec_done: 1'b1;
end
end
// Check for presence of data eye edge. During this state, we
// sample the read data multiple times, and look for changes
// in the read data, specifically:
// 1. A change in the read data compared with the value of
// read data from the previous delay tap. This indicates
// that the most recent tap delay increment has moved us
// into either a new window, or moved/kept us in the
// transition/jitter region between windows. Note that this
// condition only needs to be checked for once, and for
// logistical purposes, we check this soon after entering
// this state (see comment in PRBS_PAT_COMPARE below for
// why this is done)
// 2. A change in the read data while we are in this state
// (i.e. in the absence of a tap delay increment). This
// indicates that we're close enough to a window edge that
// jitter will cause the read data to change even in the
// absence of a tap delay change
PRBS_PAT_COMPARE: begin
// Continue to sample read data and look for edges until the
// appropriate time interval (shorter for simulation-only,
// much, much longer for actual h/w) has elapsed
//comparision started - wait for next PI movement after read
complex_pi_incdec_done <= #TCQ 1'b0; //need to be wait for new incdec done
if (num_samples_done_r) begin
if (prbs_dqs_tap_limit_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
else if (compare_err_latch || (prbs_dqs_tap_cnt_r == 'd0)) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
prbs_found_1st_edge_r <= #TCQ 1'b1;
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (prbs_found_1st_edge_r) begin
prbs_found_2nd_edge_r <= #TCQ 1'b1;
prbs_2nd_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
end else begin
// Otherwise, an edge was found (just not the "second" edge)
// Assuming DQS is in the correct window at tap 0 of Phaser IN
// fine tap. The first edge found is the right edge of the valid
// window and is the beginning of the jitter region hence done!
if (compare_err_latch)
prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
else
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_inc_tap_cnt <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;
end
end else begin
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
if (prbs_found_1st_edge_r)
//prbs_state_r <= #TCQ PRBS_INC_DQS;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC;
else
//prbs_state_r <= #TCQ PRBS_DEC_DQS;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
end
// Increment Phaser_IN delay for DQS
PRBS_INC_DQS: begin
prbs_state_r <= #TCQ PRBS_INC_DQS_WAIT;
if (prbs_inc_tap_cnt > 'd0)
prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1;
if (~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
// only all INC is done, incdec done is asserted
PRBS_INC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_inc_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_INC_DQS; //centering
else begin
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
complex_pi_incdec_done <= #TCQ 1'b1;
end
end
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: The amount to be decrement by is calculated, not the
// absolute setting for DQS.
// CENTER compensation with shift by 1
//wait finishing the read before PI dec to center
PRBS_CALC_TAPS: begin
if (center_comp) begin
prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj;
fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end else begin //No center compensation
if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin
// Both edges detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_2nd_edge_taps_r -
prbs_1st_edge_taps_r)>>1) + 1 + pi_adj;
edge_det_error <= #TCQ edge_det_error? 1'b1:
(prbs_1st_edge_taps_r >= prbs_2nd_edge_taps_r);
end else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r) begin
// Only left edge detected
prbs_dec_tap_cnt
<= #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj;
end else begin
// No edges detected
edge_det_error <= #TCQ 1'b1;
prbs_dec_tap_cnt
<= #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj;
end
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
//wait finishing the read before PI dec to center
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
PRBS_DEC_DQS: begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
if (prbs_dec_tap_cnt > 'd0)
prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1;
if (prbs_dec_tap_cnt == 6'b000001) begin
prbs_state_r <= #TCQ PRBS_NEXT_DQS;
//only all DEC is done, incdec done is asserted
complex_pi_incdec_done <= #TCQ 1'b1;
end else
prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT;
end
PRBS_DEC_DQS_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
if (prbs_dec_tap_cnt > 'd0)
prbs_state_r <= #TCQ PRBS_DEC_DQS;
else begin
//PI movement is done, go to read and compare
complex_pi_incdec_done <= #TCQ 1'b1;
prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
end
end
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
PRBS_NEXT_DQS: begin
//Need to do initial dec for per-bit algorithm
complex_init_pi_dec_done_r <= #TCQ 1'b0;
reset_rd_addr <= #TCQ 'b1;
prbs_prech_req_r <= #TCQ 1'b1;
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
prbs_found_1st_edge_r <= #TCQ 1'b0;
prbs_found_2nd_edge_r <= #TCQ 1'b0;
prbs_1st_edge_taps_r <= #TCQ 'd0;
prbs_2nd_edge_taps_r <= #TCQ 'd0;
largest_left_edge <= #TCQ 6'b000000;
smallest_right_edge <= #TCQ 6'b111111;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
prbs_last_byte_done <= #TCQ 1'b1;
end
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin
prbs_prech_req_r <= #TCQ 1'b0;
if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
// All DQS groups done
prbs_state_r <= #TCQ PRBS_DONE;
end else begin
// Process next DQS group
new_cnt_dqs_r <= #TCQ 1'b1;
prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1;
prbs_state_r <= #TCQ PRBS_NEW_DQS_PREWAIT;
end
end
end
PRBS_NEW_DQS_PREWAIT: begin
if (cnt_wait_state) begin
prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
end
end
PRBS_CALC_TAPS_PRE:
begin
//Wait for new PI movement
complex_pi_incdec_done <= #TCQ 1'b0;
prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT;
if(center_comp && ~fine_calib) begin
if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r;
else largest_left_edge <= #TCQ 6'd0;
if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r;
else smallest_right_edge <= #TCQ 6'd63;
end
end
//wait for center compensation
PRBS_CALC_TAPS_WAIT:
begin
prbs_state_r <= #TCQ PRBS_CALC_TAPS;
end
//if it is fine_inc stage (first/second stage): dec to 0
//if it is fine_dec stage (third stage): dec to center
FINE_PI_DEC: begin
fine_delay_sel <= #TCQ 'b0;
if(fine_pi_dec_cnt > 0) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b0;
fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1;
end
prbs_state_r <= #TCQ FINE_PI_DEC_WAIT;
end
//wait for phaser_in tap decrement.
//if first/second stage is done, goes to FINE_PI_INC
//if last stage is done, goes to NEXT_DQS
//All PI DEC is done, incdec done is asserted
FINE_PI_DEC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if(cnt_wait_state) begin
if(fine_pi_dec_cnt >0)
prbs_state_r <= #TCQ FINE_PI_DEC;
else begin
complex_pi_incdec_done <= #TCQ 1'b1;
if(fine_inc_stage)
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT; //start from pi tap "0"
else
prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE; //finish the process and go to the next DQS
end
end
end
//finish the read before PI increament
RD_DONE_WAIT_FOR_PI_INC_INC: begin
if(complex_act_start)
prbs_state_r <= #TCQ fine_calib? FINE_PI_INC: PRBS_INC_DQS;
end
FINE_PI_INC: begin
//prevent left edge update after valid window found
if(|left_edge_updated && ~no_err_win_detected_latch) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r- (MIN_WIN-1);
if (no_err_win_detected) begin
//ignore previous right edge updated if valid window shown after
right_edge_found <= #TCQ 'b0;
end else if(|right_edge_found_pb && ~right_edge_found) begin
smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ;
right_edge_found <= #TCQ 'b1;
end
//until minimum window is detected, left edge can be updated
//once minimum window is detected, no further left edge update will be done
if(no_err_win_detected) no_err_win_detected_latch <= #TCQ 1'b1;
prbs_state_r <= #TCQ FINE_PI_INC_WAIT;
if(~prbs_dqs_tap_limit_r) begin
prbs_tap_en_r <= #TCQ 1'b1;
prbs_tap_inc_r <= #TCQ 1'b1;
end
end
//wait for phase_in tap increment
//need to do pattern compare for every bit
FINE_PI_INC_WAIT: begin
prbs_tap_en_r <= #TCQ 1'b0;
prbs_tap_inc_r <= #TCQ 1'b0;
if (cnt_wait_state) begin
prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;
//PI movement is done, go to read and compare
complex_pi_incdec_done <= #TCQ 1'b1;
end
end
//compare per bit data and update flags,left/right edge
FINE_PAT_COMPARE_PER_BIT: begin
//comparision started - initial pi dec is done, wait for another pi movement after read
complex_init_pi_dec_done_r <= #TCQ 1'b1;
complex_pi_incdec_done <= #TCQ 1'b0;
if(num_samples_done_r) begin //sampling boundary
//update and_flag - shift and add
match_flag_and <= #TCQ {match_flag_and[MIN_WIN-2:0],compare_err_pb_and};
match_flag_or <= #TCQ {match_flag_or[MIN_WIN-2:0],compare_err_pb_or};
//to solve false left/right edge detection
if({match_flag_or[MIN_WIN-2:0],compare_err_pb_or} == MIN_PASS) begin //if it detect minimum window
no_err_win_detected <= #TCQ 1'b1;
valid_window_cnt <= #TCQ valid_window_cnt + 'd1;
end else begin
no_err_win_detected <= #TCQ 1'b0;
end
//if it is consecutive 8 passing taps followed by fail or tap limit (finish the search)
//don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage
//Or if all right edge are found
if((match_flag_and == MIN_PASS && compare_err_pb_and && (prbs_dqs_tap_cnt_r > MIN_WIN )) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin
prbs_state_r <= #TCQ FINE_CALC_TAPS;
//if all right edge are alined (all right edge found at the same time), update smallest right edge in here
//doesnt need to set right_edge_found to 1 since it is not used after this stage
if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1;
end else begin
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_INC; //keep increase until all fail
end
num_samples_done_ind <= num_samples_done_r;
end
end
//for fine_inc stage, inc all fine delay
//for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain)
// put phaser_in taps to the center
FINE_CALC_TAPS: begin
if(num_samples_done_ind || num_samples_done_r) begin
num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set
right_edge_found <= #TCQ 1'b0; //reset right edge found
match_flag_and <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits
match_flag_or <= #TCQ MATCH_ALL_ONE; //reset match flag for all bits
no_err_win_detected <= #TCQ 1'b0;
no_err_win_detected_latch <= #TCQ 1'b0;
prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT;
valid_window_cnt <= #TCQ 2'd0; //reset valid window counter
end
end
FINE_CALC_TAPS_WAIT: begin //wait for ROM read out
if(stage_cnt == 'd2) begin //last stage : back to center
if(center_comp) begin
fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ; //going to the center value & shift by 1
fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error;
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj; //going to the center value & shift left by 1
fine_dly_error <= #TCQ 1'b0;
end
end else begin
fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r;
end
if (bit_cnt == DRAM_WIDTH) begin
fine_delay_sel <= #TCQ 'b1;
stage_cnt <= #TCQ stage_cnt + 1;
prbs_state_r <= #TCQ RD_DONE_WAIT_FOR_PI_INC_DEC;
end
end
//wait for finishing the read before PI movement
RD_DONE_WAIT_FOR_PI_INC_DEC: begin
if (complex_act_start & ~complex_rdlvl_err)
prbs_state_r <= #TCQ fine_calib? FINE_PI_DEC: PRBS_DEC_DQS;
end
// Done with this stage of calibration
PRBS_DONE: begin
prbs_prech_req_r <= #TCQ 1'b0;
prbs_last_byte_done <= #TCQ 1'b0;
prbs_rdlvl_done <= #TCQ ~complex_rdlvl_err;
reset_rd_addr <= #TCQ 1'b0;
end
endcase
end
//ROM generation for dec counter
always @ (largest_left_edge or smallest_right_edge) begin
case ({largest_left_edge, smallest_right_edge})
12'd0 : mem_out_dec = 6'b111111;
12'd1 : mem_out_dec = 6'b111111;
12'd2 : mem_out_dec = 6'b111111;
12'd3 : mem_out_dec = 6'b111111;
12'd4 : mem_out_dec = 6'b111111;
12'd5 : mem_out_dec = 6'b111111;
12'd6 : mem_out_dec = 6'b000100;
12'd7 : mem_out_dec = 6'b000101;
12'd8 : mem_out_dec = 6'b000101;
12'd9 : mem_out_dec = 6'b000110;
12'd10 : mem_out_dec = 6'b000110;
12'd11 : mem_out_dec = 6'b000111;
12'd12 : mem_out_dec = 6'b001000;
12'd13 : mem_out_dec = 6'b001000;
12'd14 : mem_out_dec = 6'b001001;
12'd15 : mem_out_dec = 6'b001010;
12'd16 : mem_out_dec = 6'b001010;
12'd17 : mem_out_dec = 6'b001011;
12'd18 : mem_out_dec = 6'b001011;
12'd19 : mem_out_dec = 6'b001100;
12'd20 : mem_out_dec = 6'b001100;
12'd21 : mem_out_dec = 6'b001100;
12'd22 : mem_out_dec = 6'b001100;
12'd23 : mem_out_dec = 6'b001101;
12'd24 : mem_out_dec = 6'b001100;
12'd25 : mem_out_dec = 6'b001100;
12'd26 : mem_out_dec = 6'b001101;
12'd27 : mem_out_dec = 6'b001110;
12'd28 : mem_out_dec = 6'b001110;
12'd29 : mem_out_dec = 6'b001111;
12'd30 : mem_out_dec = 6'b010000;
12'd31 : mem_out_dec = 6'b010001;
12'd32 : mem_out_dec = 6'b010001;
12'd33 : mem_out_dec = 6'b010010;
12'd34 : mem_out_dec = 6'b010010;
12'd35 : mem_out_dec = 6'b010010;
12'd36 : mem_out_dec = 6'b010011;
12'd37 : mem_out_dec = 6'b010100;
12'd38 : mem_out_dec = 6'b010100;
12'd39 : mem_out_dec = 6'b010101;
12'd40 : mem_out_dec = 6'b010101;
12'd41 : mem_out_dec = 6'b010110;
12'd42 : mem_out_dec = 6'b010110;
12'd43 : mem_out_dec = 6'b010111;
12'd44 : mem_out_dec = 6'b011000;
12'd45 : mem_out_dec = 6'b011001;
12'd46 : mem_out_dec = 6'b011001;
12'd47 : mem_out_dec = 6'b011010;
12'd48 : mem_out_dec = 6'b011010;
12'd49 : mem_out_dec = 6'b011011;
12'd50 : mem_out_dec = 6'b011011;
12'd51 : mem_out_dec = 6'b011100;
12'd52 : mem_out_dec = 6'b011100;
12'd53 : mem_out_dec = 6'b011100;
12'd54 : mem_out_dec = 6'b011100;
12'd55 : mem_out_dec = 6'b011100;
12'd56 : mem_out_dec = 6'b011100;
12'd57 : mem_out_dec = 6'b011100;
12'd58 : mem_out_dec = 6'b011100;
12'd59 : mem_out_dec = 6'b011101;
12'd60 : mem_out_dec = 6'b011110;
12'd61 : mem_out_dec = 6'b011111;
12'd62 : mem_out_dec = 6'b100000;
12'd63 : mem_out_dec = 6'b100000;
12'd64 : mem_out_dec = 6'b111111;
12'd65 : mem_out_dec = 6'b111111;
12'd66 : mem_out_dec = 6'b111111;
12'd67 : mem_out_dec = 6'b111111;
12'd68 : mem_out_dec = 6'b111111;
12'd69 : mem_out_dec = 6'b111111;
12'd70 : mem_out_dec = 6'b111111;
12'd71 : mem_out_dec = 6'b000100;
12'd72 : mem_out_dec = 6'b000100;
12'd73 : mem_out_dec = 6'b000101;
12'd74 : mem_out_dec = 6'b000110;
12'd75 : mem_out_dec = 6'b000111;
12'd76 : mem_out_dec = 6'b000111;
12'd77 : mem_out_dec = 6'b001000;
12'd78 : mem_out_dec = 6'b001001;
12'd79 : mem_out_dec = 6'b001001;
12'd80 : mem_out_dec = 6'b001010;
12'd81 : mem_out_dec = 6'b001010;
12'd82 : mem_out_dec = 6'b001011;
12'd83 : mem_out_dec = 6'b001011;
12'd84 : mem_out_dec = 6'b001011;
12'd85 : mem_out_dec = 6'b001011;
12'd86 : mem_out_dec = 6'b001011;
12'd87 : mem_out_dec = 6'b001100;
12'd88 : mem_out_dec = 6'b001011;
12'd89 : mem_out_dec = 6'b001100;
12'd90 : mem_out_dec = 6'b001100;
12'd91 : mem_out_dec = 6'b001101;
12'd92 : mem_out_dec = 6'b001110;
12'd93 : mem_out_dec = 6'b001111;
12'd94 : mem_out_dec = 6'b001111;
12'd95 : mem_out_dec = 6'b010000;
12'd96 : mem_out_dec = 6'b010001;
12'd97 : mem_out_dec = 6'b010001;
12'd98 : mem_out_dec = 6'b010010;
12'd99 : mem_out_dec = 6'b010010;
12'd100 : mem_out_dec = 6'b010011;
12'd101 : mem_out_dec = 6'b010011;
12'd102 : mem_out_dec = 6'b010100;
12'd103 : mem_out_dec = 6'b010100;
12'd104 : mem_out_dec = 6'b010100;
12'd105 : mem_out_dec = 6'b010101;
12'd106 : mem_out_dec = 6'b010110;
12'd107 : mem_out_dec = 6'b010111;
12'd108 : mem_out_dec = 6'b010111;
12'd109 : mem_out_dec = 6'b011000;
12'd110 : mem_out_dec = 6'b011001;
12'd111 : mem_out_dec = 6'b011001;
12'd112 : mem_out_dec = 6'b011010;
12'd113 : mem_out_dec = 6'b011010;
12'd114 : mem_out_dec = 6'b011011;
12'd115 : mem_out_dec = 6'b011011;
12'd116 : mem_out_dec = 6'b011011;
12'd117 : mem_out_dec = 6'b011011;
12'd118 : mem_out_dec = 6'b011011;
12'd119 : mem_out_dec = 6'b011011;
12'd120 : mem_out_dec = 6'b011011;
12'd121 : mem_out_dec = 6'b011011;
12'd122 : mem_out_dec = 6'b011100;
12'd123 : mem_out_dec = 6'b011101;
12'd124 : mem_out_dec = 6'b011110;
12'd125 : mem_out_dec = 6'b011110;
12'd126 : mem_out_dec = 6'b011111;
12'd127 : mem_out_dec = 6'b100000;
12'd128 : mem_out_dec = 6'b111111;
12'd129 : mem_out_dec = 6'b111111;
12'd130 : mem_out_dec = 6'b111111;
12'd131 : mem_out_dec = 6'b111111;
12'd132 : mem_out_dec = 6'b111111;
12'd133 : mem_out_dec = 6'b111111;
12'd134 : mem_out_dec = 6'b111111;
12'd135 : mem_out_dec = 6'b111111;
12'd136 : mem_out_dec = 6'b000100;
12'd137 : mem_out_dec = 6'b000101;
12'd138 : mem_out_dec = 6'b000101;
12'd139 : mem_out_dec = 6'b000110;
12'd140 : mem_out_dec = 6'b000110;
12'd141 : mem_out_dec = 6'b000111;
12'd142 : mem_out_dec = 6'b001000;
12'd143 : mem_out_dec = 6'b001001;
12'd144 : mem_out_dec = 6'b001001;
12'd145 : mem_out_dec = 6'b001010;
12'd146 : mem_out_dec = 6'b001010;
12'd147 : mem_out_dec = 6'b001010;
12'd148 : mem_out_dec = 6'b001010;
12'd149 : mem_out_dec = 6'b001010;
12'd150 : mem_out_dec = 6'b001010;
12'd151 : mem_out_dec = 6'b001011;
12'd152 : mem_out_dec = 6'b001010;
12'd153 : mem_out_dec = 6'b001011;
12'd154 : mem_out_dec = 6'b001100;
12'd155 : mem_out_dec = 6'b001101;
12'd156 : mem_out_dec = 6'b001101;
12'd157 : mem_out_dec = 6'b001110;
12'd158 : mem_out_dec = 6'b001111;
12'd159 : mem_out_dec = 6'b010000;
12'd160 : mem_out_dec = 6'b010000;
12'd161 : mem_out_dec = 6'b010001;
12'd162 : mem_out_dec = 6'b010001;
12'd163 : mem_out_dec = 6'b010010;
12'd164 : mem_out_dec = 6'b010010;
12'd165 : mem_out_dec = 6'b010011;
12'd166 : mem_out_dec = 6'b010011;
12'd167 : mem_out_dec = 6'b010100;
12'd168 : mem_out_dec = 6'b010100;
12'd169 : mem_out_dec = 6'b010101;
12'd170 : mem_out_dec = 6'b010101;
12'd171 : mem_out_dec = 6'b010110;
12'd172 : mem_out_dec = 6'b010111;
12'd173 : mem_out_dec = 6'b010111;
12'd174 : mem_out_dec = 6'b011000;
12'd175 : mem_out_dec = 6'b011001;
12'd176 : mem_out_dec = 6'b011001;
12'd177 : mem_out_dec = 6'b011010;
12'd178 : mem_out_dec = 6'b011010;
12'd179 : mem_out_dec = 6'b011010;
12'd180 : mem_out_dec = 6'b011010;
12'd181 : mem_out_dec = 6'b011010;
12'd182 : mem_out_dec = 6'b011010;
12'd183 : mem_out_dec = 6'b011010;
12'd184 : mem_out_dec = 6'b011010;
12'd185 : mem_out_dec = 6'b011011;
12'd186 : mem_out_dec = 6'b011100;
12'd187 : mem_out_dec = 6'b011100;
12'd188 : mem_out_dec = 6'b011101;
12'd189 : mem_out_dec = 6'b011110;
12'd190 : mem_out_dec = 6'b011111;
12'd191 : mem_out_dec = 6'b100000;
12'd192 : mem_out_dec = 6'b111111;
12'd193 : mem_out_dec = 6'b111111;
12'd194 : mem_out_dec = 6'b111111;
12'd195 : mem_out_dec = 6'b111111;
12'd196 : mem_out_dec = 6'b111111;
12'd197 : mem_out_dec = 6'b111111;
12'd198 : mem_out_dec = 6'b111111;
12'd199 : mem_out_dec = 6'b111111;
12'd200 : mem_out_dec = 6'b111111;
12'd201 : mem_out_dec = 6'b000100;
12'd202 : mem_out_dec = 6'b000100;
12'd203 : mem_out_dec = 6'b000101;
12'd204 : mem_out_dec = 6'b000110;
12'd205 : mem_out_dec = 6'b000111;
12'd206 : mem_out_dec = 6'b001000;
12'd207 : mem_out_dec = 6'b001000;
12'd208 : mem_out_dec = 6'b001001;
12'd209 : mem_out_dec = 6'b001001;
12'd210 : mem_out_dec = 6'b001001;
12'd211 : mem_out_dec = 6'b001001;
12'd212 : mem_out_dec = 6'b001001;
12'd213 : mem_out_dec = 6'b001001;
12'd214 : mem_out_dec = 6'b001001;
12'd215 : mem_out_dec = 6'b001010;
12'd216 : mem_out_dec = 6'b001010;
12'd217 : mem_out_dec = 6'b001011;
12'd218 : mem_out_dec = 6'b001011;
12'd219 : mem_out_dec = 6'b001100;
12'd220 : mem_out_dec = 6'b001101;
12'd221 : mem_out_dec = 6'b001110;
12'd222 : mem_out_dec = 6'b001111;
12'd223 : mem_out_dec = 6'b001111;
12'd224 : mem_out_dec = 6'b010000;
12'd225 : mem_out_dec = 6'b010000;
12'd226 : mem_out_dec = 6'b010001;
12'd227 : mem_out_dec = 6'b010001;
12'd228 : mem_out_dec = 6'b010010;
12'd229 : mem_out_dec = 6'b010010;
12'd230 : mem_out_dec = 6'b010011;
12'd231 : mem_out_dec = 6'b010011;
12'd232 : mem_out_dec = 6'b010011;
12'd233 : mem_out_dec = 6'b010100;
12'd234 : mem_out_dec = 6'b010100;
12'd235 : mem_out_dec = 6'b010101;
12'd236 : mem_out_dec = 6'b010110;
12'd237 : mem_out_dec = 6'b010111;
12'd238 : mem_out_dec = 6'b011000;
12'd239 : mem_out_dec = 6'b011000;
12'd240 : mem_out_dec = 6'b011001;
12'd241 : mem_out_dec = 6'b011001;
12'd242 : mem_out_dec = 6'b011001;
12'd243 : mem_out_dec = 6'b011001;
12'd244 : mem_out_dec = 6'b011001;
12'd245 : mem_out_dec = 6'b011001;
12'd246 : mem_out_dec = 6'b011001;
12'd247 : mem_out_dec = 6'b011001;
12'd248 : mem_out_dec = 6'b011010;
12'd249 : mem_out_dec = 6'b011010;
12'd250 : mem_out_dec = 6'b011011;
12'd251 : mem_out_dec = 6'b011100;
12'd252 : mem_out_dec = 6'b011101;
12'd253 : mem_out_dec = 6'b011110;
12'd254 : mem_out_dec = 6'b011110;
12'd255 : mem_out_dec = 6'b011111;
12'd256 : mem_out_dec = 6'b111111;
12'd257 : mem_out_dec = 6'b111111;
12'd258 : mem_out_dec = 6'b111111;
12'd259 : mem_out_dec = 6'b111111;
12'd260 : mem_out_dec = 6'b111111;
12'd261 : mem_out_dec = 6'b111111;
12'd262 : mem_out_dec = 6'b111111;
12'd263 : mem_out_dec = 6'b111111;
12'd264 : mem_out_dec = 6'b111111;
12'd265 : mem_out_dec = 6'b111111;
12'd266 : mem_out_dec = 6'b000100;
12'd267 : mem_out_dec = 6'b000101;
12'd268 : mem_out_dec = 6'b000110;
12'd269 : mem_out_dec = 6'b000110;
12'd270 : mem_out_dec = 6'b000111;
12'd271 : mem_out_dec = 6'b001000;
12'd272 : mem_out_dec = 6'b001000;
12'd273 : mem_out_dec = 6'b001000;
12'd274 : mem_out_dec = 6'b001000;
12'd275 : mem_out_dec = 6'b001000;
12'd276 : mem_out_dec = 6'b001000;
12'd277 : mem_out_dec = 6'b001000;
12'd278 : mem_out_dec = 6'b001000;
12'd279 : mem_out_dec = 6'b001001;
12'd280 : mem_out_dec = 6'b001001;
12'd281 : mem_out_dec = 6'b001010;
12'd282 : mem_out_dec = 6'b001011;
12'd283 : mem_out_dec = 6'b001100;
12'd284 : mem_out_dec = 6'b001101;
12'd285 : mem_out_dec = 6'b001101;
12'd286 : mem_out_dec = 6'b001110;
12'd287 : mem_out_dec = 6'b001111;
12'd288 : mem_out_dec = 6'b001111;
12'd289 : mem_out_dec = 6'b010000;
12'd290 : mem_out_dec = 6'b010000;
12'd291 : mem_out_dec = 6'b010001;
12'd292 : mem_out_dec = 6'b010001;
12'd293 : mem_out_dec = 6'b010010;
12'd294 : mem_out_dec = 6'b010010;
12'd295 : mem_out_dec = 6'b010011;
12'd296 : mem_out_dec = 6'b010010;
12'd297 : mem_out_dec = 6'b010011;
12'd298 : mem_out_dec = 6'b010100;
12'd299 : mem_out_dec = 6'b010101;
12'd300 : mem_out_dec = 6'b010110;
12'd301 : mem_out_dec = 6'b010110;
12'd302 : mem_out_dec = 6'b010111;
12'd303 : mem_out_dec = 6'b011000;
12'd304 : mem_out_dec = 6'b011000;
12'd305 : mem_out_dec = 6'b011000;
12'd306 : mem_out_dec = 6'b011000;
12'd307 : mem_out_dec = 6'b011000;
12'd308 : mem_out_dec = 6'b011000;
12'd309 : mem_out_dec = 6'b011000;
12'd310 : mem_out_dec = 6'b011000;
12'd311 : mem_out_dec = 6'b011001;
12'd312 : mem_out_dec = 6'b011001;
12'd313 : mem_out_dec = 6'b011010;
12'd314 : mem_out_dec = 6'b011011;
12'd315 : mem_out_dec = 6'b011100;
12'd316 : mem_out_dec = 6'b011100;
12'd317 : mem_out_dec = 6'b011101;
12'd318 : mem_out_dec = 6'b011110;
12'd319 : mem_out_dec = 6'b011111;
12'd320 : mem_out_dec = 6'b111111;
12'd321 : mem_out_dec = 6'b111111;
12'd322 : mem_out_dec = 6'b111111;
12'd323 : mem_out_dec = 6'b111111;
12'd324 : mem_out_dec = 6'b111111;
12'd325 : mem_out_dec = 6'b111111;
12'd326 : mem_out_dec = 6'b111111;
12'd327 : mem_out_dec = 6'b111111;
12'd328 : mem_out_dec = 6'b111111;
12'd329 : mem_out_dec = 6'b111111;
12'd330 : mem_out_dec = 6'b111111;
12'd331 : mem_out_dec = 6'b000100;
12'd332 : mem_out_dec = 6'b000101;
12'd333 : mem_out_dec = 6'b000110;
12'd334 : mem_out_dec = 6'b000111;
12'd335 : mem_out_dec = 6'b001000;
12'd336 : mem_out_dec = 6'b000111;
12'd337 : mem_out_dec = 6'b000111;
12'd338 : mem_out_dec = 6'b000111;
12'd339 : mem_out_dec = 6'b000111;
12'd340 : mem_out_dec = 6'b000111;
12'd341 : mem_out_dec = 6'b000111;
12'd342 : mem_out_dec = 6'b001000;
12'd343 : mem_out_dec = 6'b001001;
12'd344 : mem_out_dec = 6'b001001;
12'd345 : mem_out_dec = 6'b001010;
12'd346 : mem_out_dec = 6'b001011;
12'd347 : mem_out_dec = 6'b001011;
12'd348 : mem_out_dec = 6'b001100;
12'd349 : mem_out_dec = 6'b001101;
12'd350 : mem_out_dec = 6'b001110;
12'd351 : mem_out_dec = 6'b001110;
12'd352 : mem_out_dec = 6'b001111;
12'd353 : mem_out_dec = 6'b001111;
12'd354 : mem_out_dec = 6'b010000;
12'd355 : mem_out_dec = 6'b010000;
12'd356 : mem_out_dec = 6'b010001;
12'd357 : mem_out_dec = 6'b010001;
12'd358 : mem_out_dec = 6'b010001;
12'd359 : mem_out_dec = 6'b010010;
12'd360 : mem_out_dec = 6'b010010;
12'd361 : mem_out_dec = 6'b010011;
12'd362 : mem_out_dec = 6'b010100;
12'd363 : mem_out_dec = 6'b010100;
12'd364 : mem_out_dec = 6'b010101;
12'd365 : mem_out_dec = 6'b010110;
12'd366 : mem_out_dec = 6'b010111;
12'd367 : mem_out_dec = 6'b011000;
12'd368 : mem_out_dec = 6'b010111;
12'd369 : mem_out_dec = 6'b010111;
12'd370 : mem_out_dec = 6'b010111;
12'd371 : mem_out_dec = 6'b010111;
12'd372 : mem_out_dec = 6'b010111;
12'd373 : mem_out_dec = 6'b010111;
12'd374 : mem_out_dec = 6'b011000;
12'd375 : mem_out_dec = 6'b011001;
12'd376 : mem_out_dec = 6'b011001;
12'd377 : mem_out_dec = 6'b011010;
12'd378 : mem_out_dec = 6'b011010;
12'd379 : mem_out_dec = 6'b011011;
12'd380 : mem_out_dec = 6'b011100;
12'd381 : mem_out_dec = 6'b011101;
12'd382 : mem_out_dec = 6'b011101;
12'd383 : mem_out_dec = 6'b011110;
12'd384 : mem_out_dec = 6'b111111;
12'd385 : mem_out_dec = 6'b111111;
12'd386 : mem_out_dec = 6'b111111;
12'd387 : mem_out_dec = 6'b111111;
12'd388 : mem_out_dec = 6'b111111;
12'd389 : mem_out_dec = 6'b111111;
12'd390 : mem_out_dec = 6'b111111;
12'd391 : mem_out_dec = 6'b111111;
12'd392 : mem_out_dec = 6'b111111;
12'd393 : mem_out_dec = 6'b111111;
12'd394 : mem_out_dec = 6'b111111;
12'd395 : mem_out_dec = 6'b111111;
12'd396 : mem_out_dec = 6'b000101;
12'd397 : mem_out_dec = 6'b000110;
12'd398 : mem_out_dec = 6'b000110;
12'd399 : mem_out_dec = 6'b000111;
12'd400 : mem_out_dec = 6'b000110;
12'd401 : mem_out_dec = 6'b000110;
12'd402 : mem_out_dec = 6'b000110;
12'd403 : mem_out_dec = 6'b000110;
12'd404 : mem_out_dec = 6'b000110;
12'd405 : mem_out_dec = 6'b000111;
12'd406 : mem_out_dec = 6'b001000;
12'd407 : mem_out_dec = 6'b001000;
12'd408 : mem_out_dec = 6'b001001;
12'd409 : mem_out_dec = 6'b001001;
12'd410 : mem_out_dec = 6'b001010;
12'd411 : mem_out_dec = 6'b001011;
12'd412 : mem_out_dec = 6'b001100;
12'd413 : mem_out_dec = 6'b001100;
12'd414 : mem_out_dec = 6'b001101;
12'd415 : mem_out_dec = 6'b001110;
12'd416 : mem_out_dec = 6'b001110;
12'd417 : mem_out_dec = 6'b001111;
12'd418 : mem_out_dec = 6'b001111;
12'd419 : mem_out_dec = 6'b010000;
12'd420 : mem_out_dec = 6'b010000;
12'd421 : mem_out_dec = 6'b010000;
12'd422 : mem_out_dec = 6'b010001;
12'd423 : mem_out_dec = 6'b010001;
12'd424 : mem_out_dec = 6'b010010;
12'd425 : mem_out_dec = 6'b010011;
12'd426 : mem_out_dec = 6'b010011;
12'd427 : mem_out_dec = 6'b010100;
12'd428 : mem_out_dec = 6'b010101;
12'd429 : mem_out_dec = 6'b010110;
12'd430 : mem_out_dec = 6'b010111;
12'd431 : mem_out_dec = 6'b010111;
12'd432 : mem_out_dec = 6'b010110;
12'd433 : mem_out_dec = 6'b010110;
12'd434 : mem_out_dec = 6'b010110;
12'd435 : mem_out_dec = 6'b010110;
12'd436 : mem_out_dec = 6'b010110;
12'd437 : mem_out_dec = 6'b010111;
12'd438 : mem_out_dec = 6'b010111;
12'd439 : mem_out_dec = 6'b011000;
12'd440 : mem_out_dec = 6'b011001;
12'd441 : mem_out_dec = 6'b011001;
12'd442 : mem_out_dec = 6'b011010;
12'd443 : mem_out_dec = 6'b011011;
12'd444 : mem_out_dec = 6'b011011;
12'd445 : mem_out_dec = 6'b011100;
12'd446 : mem_out_dec = 6'b011101;
12'd447 : mem_out_dec = 6'b011110;
12'd448 : mem_out_dec = 6'b111111;
12'd449 : mem_out_dec = 6'b111111;
12'd450 : mem_out_dec = 6'b111111;
12'd451 : mem_out_dec = 6'b111111;
12'd452 : mem_out_dec = 6'b111111;
12'd453 : mem_out_dec = 6'b111111;
12'd454 : mem_out_dec = 6'b111111;
12'd455 : mem_out_dec = 6'b111111;
12'd456 : mem_out_dec = 6'b111111;
12'd457 : mem_out_dec = 6'b111111;
12'd458 : mem_out_dec = 6'b111111;
12'd459 : mem_out_dec = 6'b111111;
12'd460 : mem_out_dec = 6'b111111;
12'd461 : mem_out_dec = 6'b000101;
12'd462 : mem_out_dec = 6'b000110;
12'd463 : mem_out_dec = 6'b000110;
12'd464 : mem_out_dec = 6'b000110;
12'd465 : mem_out_dec = 6'b000110;
12'd466 : mem_out_dec = 6'b000110;
12'd467 : mem_out_dec = 6'b000110;
12'd468 : mem_out_dec = 6'b000110;
12'd469 : mem_out_dec = 6'b000111;
12'd470 : mem_out_dec = 6'b000111;
12'd471 : mem_out_dec = 6'b001000;
12'd472 : mem_out_dec = 6'b001000;
12'd473 : mem_out_dec = 6'b001001;
12'd474 : mem_out_dec = 6'b001010;
12'd475 : mem_out_dec = 6'b001011;
12'd476 : mem_out_dec = 6'b001011;
12'd477 : mem_out_dec = 6'b001100;
12'd478 : mem_out_dec = 6'b001101;
12'd479 : mem_out_dec = 6'b001110;
12'd480 : mem_out_dec = 6'b001110;
12'd481 : mem_out_dec = 6'b001110;
12'd482 : mem_out_dec = 6'b001111;
12'd483 : mem_out_dec = 6'b001111;
12'd484 : mem_out_dec = 6'b010000;
12'd485 : mem_out_dec = 6'b010000;
12'd486 : mem_out_dec = 6'b010000;
12'd487 : mem_out_dec = 6'b010001;
12'd488 : mem_out_dec = 6'b010001;
12'd489 : mem_out_dec = 6'b010010;
12'd490 : mem_out_dec = 6'b010011;
12'd491 : mem_out_dec = 6'b010100;
12'd492 : mem_out_dec = 6'b010101;
12'd493 : mem_out_dec = 6'b010101;
12'd494 : mem_out_dec = 6'b010110;
12'd495 : mem_out_dec = 6'b010110;
12'd496 : mem_out_dec = 6'b010110;
12'd497 : mem_out_dec = 6'b010110;
12'd498 : mem_out_dec = 6'b010101;
12'd499 : mem_out_dec = 6'b010101;
12'd500 : mem_out_dec = 6'b010110;
12'd501 : mem_out_dec = 6'b010111;
12'd502 : mem_out_dec = 6'b010111;
12'd503 : mem_out_dec = 6'b011000;
12'd504 : mem_out_dec = 6'b011000;
12'd505 : mem_out_dec = 6'b011001;
12'd506 : mem_out_dec = 6'b011010;
12'd507 : mem_out_dec = 6'b011010;
12'd508 : mem_out_dec = 6'b011011;
12'd509 : mem_out_dec = 6'b011100;
12'd510 : mem_out_dec = 6'b011101;
12'd511 : mem_out_dec = 6'b011101;
12'd512 : mem_out_dec = 6'b111111;
12'd513 : mem_out_dec = 6'b111111;
12'd514 : mem_out_dec = 6'b111111;
12'd515 : mem_out_dec = 6'b111111;
12'd516 : mem_out_dec = 6'b111111;
12'd517 : mem_out_dec = 6'b111111;
12'd518 : mem_out_dec = 6'b111111;
12'd519 : mem_out_dec = 6'b111111;
12'd520 : mem_out_dec = 6'b111111;
12'd521 : mem_out_dec = 6'b111111;
12'd522 : mem_out_dec = 6'b111111;
12'd523 : mem_out_dec = 6'b111111;
12'd524 : mem_out_dec = 6'b111111;
12'd525 : mem_out_dec = 6'b111111;
12'd526 : mem_out_dec = 6'b000100;
12'd527 : mem_out_dec = 6'b000101;
12'd528 : mem_out_dec = 6'b000100;
12'd529 : mem_out_dec = 6'b000100;
12'd530 : mem_out_dec = 6'b000100;
12'd531 : mem_out_dec = 6'b000101;
12'd532 : mem_out_dec = 6'b000101;
12'd533 : mem_out_dec = 6'b000110;
12'd534 : mem_out_dec = 6'b000111;
12'd535 : mem_out_dec = 6'b000111;
12'd536 : mem_out_dec = 6'b000111;
12'd537 : mem_out_dec = 6'b001000;
12'd538 : mem_out_dec = 6'b001001;
12'd539 : mem_out_dec = 6'b001010;
12'd540 : mem_out_dec = 6'b001011;
12'd541 : mem_out_dec = 6'b001011;
12'd542 : mem_out_dec = 6'b001100;
12'd543 : mem_out_dec = 6'b001101;
12'd544 : mem_out_dec = 6'b001101;
12'd545 : mem_out_dec = 6'b001101;
12'd546 : mem_out_dec = 6'b001110;
12'd547 : mem_out_dec = 6'b001110;
12'd548 : mem_out_dec = 6'b001110;
12'd549 : mem_out_dec = 6'b001111;
12'd550 : mem_out_dec = 6'b010000;
12'd551 : mem_out_dec = 6'b010000;
12'd552 : mem_out_dec = 6'b010001;
12'd553 : mem_out_dec = 6'b010001;
12'd554 : mem_out_dec = 6'b010010;
12'd555 : mem_out_dec = 6'b010010;
12'd556 : mem_out_dec = 6'b010011;
12'd557 : mem_out_dec = 6'b010100;
12'd558 : mem_out_dec = 6'b010100;
12'd559 : mem_out_dec = 6'b010100;
12'd560 : mem_out_dec = 6'b010100;
12'd561 : mem_out_dec = 6'b010100;
12'd562 : mem_out_dec = 6'b010100;
12'd563 : mem_out_dec = 6'b010101;
12'd564 : mem_out_dec = 6'b010101;
12'd565 : mem_out_dec = 6'b010110;
12'd566 : mem_out_dec = 6'b010111;
12'd567 : mem_out_dec = 6'b010111;
12'd568 : mem_out_dec = 6'b010111;
12'd569 : mem_out_dec = 6'b011000;
12'd570 : mem_out_dec = 6'b011001;
12'd571 : mem_out_dec = 6'b011010;
12'd572 : mem_out_dec = 6'b011010;
12'd573 : mem_out_dec = 6'b011011;
12'd574 : mem_out_dec = 6'b011100;
12'd575 : mem_out_dec = 6'b011101;
12'd576 : mem_out_dec = 6'b111111;
12'd577 : mem_out_dec = 6'b111111;
12'd578 : mem_out_dec = 6'b111111;
12'd579 : mem_out_dec = 6'b111111;
12'd580 : mem_out_dec = 6'b111111;
12'd581 : mem_out_dec = 6'b111111;
12'd582 : mem_out_dec = 6'b111111;
12'd583 : mem_out_dec = 6'b111111;
12'd584 : mem_out_dec = 6'b111111;
12'd585 : mem_out_dec = 6'b111111;
12'd586 : mem_out_dec = 6'b111111;
12'd587 : mem_out_dec = 6'b111111;
12'd588 : mem_out_dec = 6'b111111;
12'd589 : mem_out_dec = 6'b111111;
12'd590 : mem_out_dec = 6'b111111;
12'd591 : mem_out_dec = 6'b000100;
12'd592 : mem_out_dec = 6'b000011;
12'd593 : mem_out_dec = 6'b000011;
12'd594 : mem_out_dec = 6'b000100;
12'd595 : mem_out_dec = 6'b000101;
12'd596 : mem_out_dec = 6'b000101;
12'd597 : mem_out_dec = 6'b000110;
12'd598 : mem_out_dec = 6'b000110;
12'd599 : mem_out_dec = 6'b000111;
12'd600 : mem_out_dec = 6'b000111;
12'd601 : mem_out_dec = 6'b001000;
12'd602 : mem_out_dec = 6'b001001;
12'd603 : mem_out_dec = 6'b001010;
12'd604 : mem_out_dec = 6'b001010;
12'd605 : mem_out_dec = 6'b001011;
12'd606 : mem_out_dec = 6'b001100;
12'd607 : mem_out_dec = 6'b001101;
12'd608 : mem_out_dec = 6'b001101;
12'd609 : mem_out_dec = 6'b001101;
12'd610 : mem_out_dec = 6'b001110;
12'd611 : mem_out_dec = 6'b001110;
12'd612 : mem_out_dec = 6'b001110;
12'd613 : mem_out_dec = 6'b001111;
12'd614 : mem_out_dec = 6'b010000;
12'd615 : mem_out_dec = 6'b010000;
12'd616 : mem_out_dec = 6'b010000;
12'd617 : mem_out_dec = 6'b010001;
12'd618 : mem_out_dec = 6'b010001;
12'd619 : mem_out_dec = 6'b010010;
12'd620 : mem_out_dec = 6'b010010;
12'd621 : mem_out_dec = 6'b010011;
12'd622 : mem_out_dec = 6'b010011;
12'd623 : mem_out_dec = 6'b010100;
12'd624 : mem_out_dec = 6'b010011;
12'd625 : mem_out_dec = 6'b010011;
12'd626 : mem_out_dec = 6'b010100;
12'd627 : mem_out_dec = 6'b010100;
12'd628 : mem_out_dec = 6'b010101;
12'd629 : mem_out_dec = 6'b010110;
12'd630 : mem_out_dec = 6'b010110;
12'd631 : mem_out_dec = 6'b010111;
12'd632 : mem_out_dec = 6'b010111;
12'd633 : mem_out_dec = 6'b011000;
12'd634 : mem_out_dec = 6'b011001;
12'd635 : mem_out_dec = 6'b011001;
12'd636 : mem_out_dec = 6'b011010;
12'd637 : mem_out_dec = 6'b011011;
12'd638 : mem_out_dec = 6'b011100;
12'd639 : mem_out_dec = 6'b011100;
12'd640 : mem_out_dec = 6'b111111;
12'd641 : mem_out_dec = 6'b111111;
12'd642 : mem_out_dec = 6'b111111;
12'd643 : mem_out_dec = 6'b111111;
12'd644 : mem_out_dec = 6'b111111;
12'd645 : mem_out_dec = 6'b111111;
12'd646 : mem_out_dec = 6'b111111;
12'd647 : mem_out_dec = 6'b111111;
12'd648 : mem_out_dec = 6'b111111;
12'd649 : mem_out_dec = 6'b111111;
12'd650 : mem_out_dec = 6'b111111;
12'd651 : mem_out_dec = 6'b111111;
12'd652 : mem_out_dec = 6'b111111;
12'd653 : mem_out_dec = 6'b111111;
12'd654 : mem_out_dec = 6'b111111;
12'd655 : mem_out_dec = 6'b111111;
12'd656 : mem_out_dec = 6'b000011;
12'd657 : mem_out_dec = 6'b000011;
12'd658 : mem_out_dec = 6'b000100;
12'd659 : mem_out_dec = 6'b000100;
12'd660 : mem_out_dec = 6'b000101;
12'd661 : mem_out_dec = 6'b000110;
12'd662 : mem_out_dec = 6'b000110;
12'd663 : mem_out_dec = 6'b000111;
12'd664 : mem_out_dec = 6'b000111;
12'd665 : mem_out_dec = 6'b001000;
12'd666 : mem_out_dec = 6'b001001;
12'd667 : mem_out_dec = 6'b001001;
12'd668 : mem_out_dec = 6'b001010;
12'd669 : mem_out_dec = 6'b001011;
12'd670 : mem_out_dec = 6'b001100;
12'd671 : mem_out_dec = 6'b001100;
12'd672 : mem_out_dec = 6'b001100;
12'd673 : mem_out_dec = 6'b001101;
12'd674 : mem_out_dec = 6'b001101;
12'd675 : mem_out_dec = 6'b001101;
12'd676 : mem_out_dec = 6'b001110;
12'd677 : mem_out_dec = 6'b001111;
12'd678 : mem_out_dec = 6'b001111;
12'd679 : mem_out_dec = 6'b010000;
12'd680 : mem_out_dec = 6'b010000;
12'd681 : mem_out_dec = 6'b010000;
12'd682 : mem_out_dec = 6'b010001;
12'd683 : mem_out_dec = 6'b010001;
12'd684 : mem_out_dec = 6'b010010;
12'd685 : mem_out_dec = 6'b010010;
12'd686 : mem_out_dec = 6'b010011;
12'd687 : mem_out_dec = 6'b010011;
12'd688 : mem_out_dec = 6'b010011;
12'd689 : mem_out_dec = 6'b010011;
12'd690 : mem_out_dec = 6'b010100;
12'd691 : mem_out_dec = 6'b010100;
12'd692 : mem_out_dec = 6'b010101;
12'd693 : mem_out_dec = 6'b010101;
12'd694 : mem_out_dec = 6'b010110;
12'd695 : mem_out_dec = 6'b010111;
12'd696 : mem_out_dec = 6'b010111;
12'd697 : mem_out_dec = 6'b011000;
12'd698 : mem_out_dec = 6'b011000;
12'd699 : mem_out_dec = 6'b011001;
12'd700 : mem_out_dec = 6'b011010;
12'd701 : mem_out_dec = 6'b011011;
12'd702 : mem_out_dec = 6'b011011;
12'd703 : mem_out_dec = 6'b011100;
12'd704 : mem_out_dec = 6'b111111;
12'd705 : mem_out_dec = 6'b111111;
12'd706 : mem_out_dec = 6'b111111;
12'd707 : mem_out_dec = 6'b111111;
12'd708 : mem_out_dec = 6'b111111;
12'd709 : mem_out_dec = 6'b111111;
12'd710 : mem_out_dec = 6'b111111;
12'd711 : mem_out_dec = 6'b111111;
12'd712 : mem_out_dec = 6'b111111;
12'd713 : mem_out_dec = 6'b111111;
12'd714 : mem_out_dec = 6'b111111;
12'd715 : mem_out_dec = 6'b111111;
12'd716 : mem_out_dec = 6'b111111;
12'd717 : mem_out_dec = 6'b111111;
12'd718 : mem_out_dec = 6'b111111;
12'd719 : mem_out_dec = 6'b111111;
12'd720 : mem_out_dec = 6'b111111;
12'd721 : mem_out_dec = 6'b000011;
12'd722 : mem_out_dec = 6'b000100;
12'd723 : mem_out_dec = 6'b000100;
12'd724 : mem_out_dec = 6'b000101;
12'd725 : mem_out_dec = 6'b000101;
12'd726 : mem_out_dec = 6'b000110;
12'd727 : mem_out_dec = 6'b000111;
12'd728 : mem_out_dec = 6'b000111;
12'd729 : mem_out_dec = 6'b000111;
12'd730 : mem_out_dec = 6'b001000;
12'd731 : mem_out_dec = 6'b001001;
12'd732 : mem_out_dec = 6'b001010;
12'd733 : mem_out_dec = 6'b001011;
12'd734 : mem_out_dec = 6'b001011;
12'd735 : mem_out_dec = 6'b001100;
12'd736 : mem_out_dec = 6'b001100;
12'd737 : mem_out_dec = 6'b001101;
12'd738 : mem_out_dec = 6'b001101;
12'd739 : mem_out_dec = 6'b001101;
12'd740 : mem_out_dec = 6'b001110;
12'd741 : mem_out_dec = 6'b001110;
12'd742 : mem_out_dec = 6'b001111;
12'd743 : mem_out_dec = 6'b010000;
12'd744 : mem_out_dec = 6'b001111;
12'd745 : mem_out_dec = 6'b010000;
12'd746 : mem_out_dec = 6'b010000;
12'd747 : mem_out_dec = 6'b010001;
12'd748 : mem_out_dec = 6'b010001;
12'd749 : mem_out_dec = 6'b010010;
12'd750 : mem_out_dec = 6'b010010;
12'd751 : mem_out_dec = 6'b010011;
12'd752 : mem_out_dec = 6'b010010;
12'd753 : mem_out_dec = 6'b010011;
12'd754 : mem_out_dec = 6'b010011;
12'd755 : mem_out_dec = 6'b010100;
12'd756 : mem_out_dec = 6'b010101;
12'd757 : mem_out_dec = 6'b010101;
12'd758 : mem_out_dec = 6'b010110;
12'd759 : mem_out_dec = 6'b010110;
12'd760 : mem_out_dec = 6'b010111;
12'd761 : mem_out_dec = 6'b010111;
12'd762 : mem_out_dec = 6'b011000;
12'd763 : mem_out_dec = 6'b011001;
12'd764 : mem_out_dec = 6'b011010;
12'd765 : mem_out_dec = 6'b011010;
12'd766 : mem_out_dec = 6'b011011;
12'd767 : mem_out_dec = 6'b011100;
12'd768 : mem_out_dec = 6'b111111;
12'd769 : mem_out_dec = 6'b111111;
12'd770 : mem_out_dec = 6'b111111;
12'd771 : mem_out_dec = 6'b111111;
12'd772 : mem_out_dec = 6'b111111;
12'd773 : mem_out_dec = 6'b111111;
12'd774 : mem_out_dec = 6'b111111;
12'd775 : mem_out_dec = 6'b111111;
12'd776 : mem_out_dec = 6'b111111;
12'd777 : mem_out_dec = 6'b111111;
12'd778 : mem_out_dec = 6'b111111;
12'd779 : mem_out_dec = 6'b111111;
12'd780 : mem_out_dec = 6'b111111;
12'd781 : mem_out_dec = 6'b111111;
12'd782 : mem_out_dec = 6'b111111;
12'd783 : mem_out_dec = 6'b111111;
12'd784 : mem_out_dec = 6'b111111;
12'd785 : mem_out_dec = 6'b111111;
12'd786 : mem_out_dec = 6'b000011;
12'd787 : mem_out_dec = 6'b000100;
12'd788 : mem_out_dec = 6'b000101;
12'd789 : mem_out_dec = 6'b000101;
12'd790 : mem_out_dec = 6'b000110;
12'd791 : mem_out_dec = 6'b000110;
12'd792 : mem_out_dec = 6'b000110;
12'd793 : mem_out_dec = 6'b000111;
12'd794 : mem_out_dec = 6'b001000;
12'd795 : mem_out_dec = 6'b001001;
12'd796 : mem_out_dec = 6'b001010;
12'd797 : mem_out_dec = 6'b001010;
12'd798 : mem_out_dec = 6'b001011;
12'd799 : mem_out_dec = 6'b001100;
12'd800 : mem_out_dec = 6'b001100;
12'd801 : mem_out_dec = 6'b001100;
12'd802 : mem_out_dec = 6'b001101;
12'd803 : mem_out_dec = 6'b001101;
12'd804 : mem_out_dec = 6'b001110;
12'd805 : mem_out_dec = 6'b001110;
12'd806 : mem_out_dec = 6'b001111;
12'd807 : mem_out_dec = 6'b010000;
12'd808 : mem_out_dec = 6'b001111;
12'd809 : mem_out_dec = 6'b001111;
12'd810 : mem_out_dec = 6'b010000;
12'd811 : mem_out_dec = 6'b010000;
12'd812 : mem_out_dec = 6'b010001;
12'd813 : mem_out_dec = 6'b010001;
12'd814 : mem_out_dec = 6'b010010;
12'd815 : mem_out_dec = 6'b010010;
12'd816 : mem_out_dec = 6'b010010;
12'd817 : mem_out_dec = 6'b010011;
12'd818 : mem_out_dec = 6'b010011;
12'd819 : mem_out_dec = 6'b010100;
12'd820 : mem_out_dec = 6'b010100;
12'd821 : mem_out_dec = 6'b010101;
12'd822 : mem_out_dec = 6'b010110;
12'd823 : mem_out_dec = 6'b010110;
12'd824 : mem_out_dec = 6'b010110;
12'd825 : mem_out_dec = 6'b010111;
12'd826 : mem_out_dec = 6'b011000;
12'd827 : mem_out_dec = 6'b011001;
12'd828 : mem_out_dec = 6'b011001;
12'd829 : mem_out_dec = 6'b011010;
12'd830 : mem_out_dec = 6'b011011;
12'd831 : mem_out_dec = 6'b011100;
12'd832 : mem_out_dec = 6'b111111;
12'd833 : mem_out_dec = 6'b111111;
12'd834 : mem_out_dec = 6'b111111;
12'd835 : mem_out_dec = 6'b111111;
12'd836 : mem_out_dec = 6'b111111;
12'd837 : mem_out_dec = 6'b111111;
12'd838 : mem_out_dec = 6'b111111;
12'd839 : mem_out_dec = 6'b111111;
12'd840 : mem_out_dec = 6'b111111;
12'd841 : mem_out_dec = 6'b111111;
12'd842 : mem_out_dec = 6'b111111;
12'd843 : mem_out_dec = 6'b111111;
12'd844 : mem_out_dec = 6'b111111;
12'd845 : mem_out_dec = 6'b111111;
12'd846 : mem_out_dec = 6'b111111;
12'd847 : mem_out_dec = 6'b111111;
12'd848 : mem_out_dec = 6'b111111;
12'd849 : mem_out_dec = 6'b111111;
12'd850 : mem_out_dec = 6'b111111;
12'd851 : mem_out_dec = 6'b000100;
12'd852 : mem_out_dec = 6'b000100;
12'd853 : mem_out_dec = 6'b000101;
12'd854 : mem_out_dec = 6'b000101;
12'd855 : mem_out_dec = 6'b000110;
12'd856 : mem_out_dec = 6'b000110;
12'd857 : mem_out_dec = 6'b000111;
12'd858 : mem_out_dec = 6'b001000;
12'd859 : mem_out_dec = 6'b001001;
12'd860 : mem_out_dec = 6'b001001;
12'd861 : mem_out_dec = 6'b001010;
12'd862 : mem_out_dec = 6'b001011;
12'd863 : mem_out_dec = 6'b001100;
12'd864 : mem_out_dec = 6'b001100;
12'd865 : mem_out_dec = 6'b001100;
12'd866 : mem_out_dec = 6'b001100;
12'd867 : mem_out_dec = 6'b001101;
12'd868 : mem_out_dec = 6'b001101;
12'd869 : mem_out_dec = 6'b001110;
12'd870 : mem_out_dec = 6'b001111;
12'd871 : mem_out_dec = 6'b001111;
12'd872 : mem_out_dec = 6'b001110;
12'd873 : mem_out_dec = 6'b001111;
12'd874 : mem_out_dec = 6'b001111;
12'd875 : mem_out_dec = 6'b010000;
12'd876 : mem_out_dec = 6'b010000;
12'd877 : mem_out_dec = 6'b010001;
12'd878 : mem_out_dec = 6'b010001;
12'd879 : mem_out_dec = 6'b010010;
12'd880 : mem_out_dec = 6'b010010;
12'd881 : mem_out_dec = 6'b010010;
12'd882 : mem_out_dec = 6'b010011;
12'd883 : mem_out_dec = 6'b010100;
12'd884 : mem_out_dec = 6'b010100;
12'd885 : mem_out_dec = 6'b010101;
12'd886 : mem_out_dec = 6'b010101;
12'd887 : mem_out_dec = 6'b010110;
12'd888 : mem_out_dec = 6'b010110;
12'd889 : mem_out_dec = 6'b010111;
12'd890 : mem_out_dec = 6'b011000;
12'd891 : mem_out_dec = 6'b011000;
12'd892 : mem_out_dec = 6'b011001;
12'd893 : mem_out_dec = 6'b011010;
12'd894 : mem_out_dec = 6'b011011;
12'd895 : mem_out_dec = 6'b011011;
12'd896 : mem_out_dec = 6'b111111;
12'd897 : mem_out_dec = 6'b111111;
12'd898 : mem_out_dec = 6'b111111;
12'd899 : mem_out_dec = 6'b111111;
12'd900 : mem_out_dec = 6'b111111;
12'd901 : mem_out_dec = 6'b111111;
12'd902 : mem_out_dec = 6'b111111;
12'd903 : mem_out_dec = 6'b111111;
12'd904 : mem_out_dec = 6'b111111;
12'd905 : mem_out_dec = 6'b111111;
12'd906 : mem_out_dec = 6'b111111;
12'd907 : mem_out_dec = 6'b111111;
12'd908 : mem_out_dec = 6'b111111;
12'd909 : mem_out_dec = 6'b111111;
12'd910 : mem_out_dec = 6'b111111;
12'd911 : mem_out_dec = 6'b111111;
12'd912 : mem_out_dec = 6'b111111;
12'd913 : mem_out_dec = 6'b111111;
12'd914 : mem_out_dec = 6'b111111;
12'd915 : mem_out_dec = 6'b111111;
12'd916 : mem_out_dec = 6'b000100;
12'd917 : mem_out_dec = 6'b000101;
12'd918 : mem_out_dec = 6'b000101;
12'd919 : mem_out_dec = 6'b000110;
12'd920 : mem_out_dec = 6'b000110;
12'd921 : mem_out_dec = 6'b000111;
12'd922 : mem_out_dec = 6'b001000;
12'd923 : mem_out_dec = 6'b001000;
12'd924 : mem_out_dec = 6'b001001;
12'd925 : mem_out_dec = 6'b001010;
12'd926 : mem_out_dec = 6'b001011;
12'd927 : mem_out_dec = 6'b001011;
12'd928 : mem_out_dec = 6'b001011;
12'd929 : mem_out_dec = 6'b001100;
12'd930 : mem_out_dec = 6'b001100;
12'd931 : mem_out_dec = 6'b001101;
12'd932 : mem_out_dec = 6'b001101;
12'd933 : mem_out_dec = 6'b001110;
12'd934 : mem_out_dec = 6'b001110;
12'd935 : mem_out_dec = 6'b001111;
12'd936 : mem_out_dec = 6'b001110;
12'd937 : mem_out_dec = 6'b001110;
12'd938 : mem_out_dec = 6'b001111;
12'd939 : mem_out_dec = 6'b001111;
12'd940 : mem_out_dec = 6'b010000;
12'd941 : mem_out_dec = 6'b010000;
12'd942 : mem_out_dec = 6'b010001;
12'd943 : mem_out_dec = 6'b010001;
12'd944 : mem_out_dec = 6'b010010;
12'd945 : mem_out_dec = 6'b010010;
12'd946 : mem_out_dec = 6'b010011;
12'd947 : mem_out_dec = 6'b010011;
12'd948 : mem_out_dec = 6'b010100;
12'd949 : mem_out_dec = 6'b010100;
12'd950 : mem_out_dec = 6'b010101;
12'd951 : mem_out_dec = 6'b010110;
12'd952 : mem_out_dec = 6'b010110;
12'd953 : mem_out_dec = 6'b010111;
12'd954 : mem_out_dec = 6'b010111;
12'd955 : mem_out_dec = 6'b011000;
12'd956 : mem_out_dec = 6'b011001;
12'd957 : mem_out_dec = 6'b011010;
12'd958 : mem_out_dec = 6'b011010;
12'd959 : mem_out_dec = 6'b011011;
12'd960 : mem_out_dec = 6'b111111;
12'd961 : mem_out_dec = 6'b111111;
12'd962 : mem_out_dec = 6'b111111;
12'd963 : mem_out_dec = 6'b111111;
12'd964 : mem_out_dec = 6'b111111;
12'd965 : mem_out_dec = 6'b111111;
12'd966 : mem_out_dec = 6'b111111;
12'd967 : mem_out_dec = 6'b111111;
12'd968 : mem_out_dec = 6'b111111;
12'd969 : mem_out_dec = 6'b111111;
12'd970 : mem_out_dec = 6'b111111;
12'd971 : mem_out_dec = 6'b111111;
12'd972 : mem_out_dec = 6'b111111;
12'd973 : mem_out_dec = 6'b111111;
12'd974 : mem_out_dec = 6'b111111;
12'd975 : mem_out_dec = 6'b111111;
12'd976 : mem_out_dec = 6'b111111;
12'd977 : mem_out_dec = 6'b111111;
12'd978 : mem_out_dec = 6'b111111;
12'd979 : mem_out_dec = 6'b111111;
12'd980 : mem_out_dec = 6'b111111;
12'd981 : mem_out_dec = 6'b000100;
12'd982 : mem_out_dec = 6'b000101;
12'd983 : mem_out_dec = 6'b000110;
12'd984 : mem_out_dec = 6'b000110;
12'd985 : mem_out_dec = 6'b000111;
12'd986 : mem_out_dec = 6'b000111;
12'd987 : mem_out_dec = 6'b001000;
12'd988 : mem_out_dec = 6'b001001;
12'd989 : mem_out_dec = 6'b001010;
12'd990 : mem_out_dec = 6'b001010;
12'd991 : mem_out_dec = 6'b001011;
12'd992 : mem_out_dec = 6'b001011;
12'd993 : mem_out_dec = 6'b001011;
12'd994 : mem_out_dec = 6'b001100;
12'd995 : mem_out_dec = 6'b001100;
12'd996 : mem_out_dec = 6'b001101;
12'd997 : mem_out_dec = 6'b001110;
12'd998 : mem_out_dec = 6'b001110;
12'd999 : mem_out_dec = 6'b001110;
12'd1000 : mem_out_dec = 6'b001101;
12'd1001 : mem_out_dec = 6'b001110;
12'd1002 : mem_out_dec = 6'b001110;
12'd1003 : mem_out_dec = 6'b001111;
12'd1004 : mem_out_dec = 6'b001111;
12'd1005 : mem_out_dec = 6'b010000;
12'd1006 : mem_out_dec = 6'b010000;
12'd1007 : mem_out_dec = 6'b010001;
12'd1008 : mem_out_dec = 6'b010001;
12'd1009 : mem_out_dec = 6'b010010;
12'd1010 : mem_out_dec = 6'b010011;
12'd1011 : mem_out_dec = 6'b010011;
12'd1012 : mem_out_dec = 6'b010100;
12'd1013 : mem_out_dec = 6'b010100;
12'd1014 : mem_out_dec = 6'b010101;
12'd1015 : mem_out_dec = 6'b010110;
12'd1016 : mem_out_dec = 6'b010110;
12'd1017 : mem_out_dec = 6'b010110;
12'd1018 : mem_out_dec = 6'b010111;
12'd1019 : mem_out_dec = 6'b011000;
12'd1020 : mem_out_dec = 6'b011001;
12'd1021 : mem_out_dec = 6'b011001;
12'd1022 : mem_out_dec = 6'b011010;
12'd1023 : mem_out_dec = 6'b011011;
12'd1024 : mem_out_dec = 6'b111111;
12'd1025 : mem_out_dec = 6'b111111;
12'd1026 : mem_out_dec = 6'b111111;
12'd1027 : mem_out_dec = 6'b111111;
12'd1028 : mem_out_dec = 6'b111111;
12'd1029 : mem_out_dec = 6'b111111;
12'd1030 : mem_out_dec = 6'b111111;
12'd1031 : mem_out_dec = 6'b111111;
12'd1032 : mem_out_dec = 6'b111111;
12'd1033 : mem_out_dec = 6'b111111;
12'd1034 : mem_out_dec = 6'b111111;
12'd1035 : mem_out_dec = 6'b111111;
12'd1036 : mem_out_dec = 6'b111111;
12'd1037 : mem_out_dec = 6'b111111;
12'd1038 : mem_out_dec = 6'b111111;
12'd1039 : mem_out_dec = 6'b111111;
12'd1040 : mem_out_dec = 6'b111111;
12'd1041 : mem_out_dec = 6'b111111;
12'd1042 : mem_out_dec = 6'b111111;
12'd1043 : mem_out_dec = 6'b111111;
12'd1044 : mem_out_dec = 6'b111111;
12'd1045 : mem_out_dec = 6'b111111;
12'd1046 : mem_out_dec = 6'b000100;
12'd1047 : mem_out_dec = 6'b000101;
12'd1048 : mem_out_dec = 6'b000101;
12'd1049 : mem_out_dec = 6'b000110;
12'd1050 : mem_out_dec = 6'b000110;
12'd1051 : mem_out_dec = 6'b000111;
12'd1052 : mem_out_dec = 6'b001000;
12'd1053 : mem_out_dec = 6'b001001;
12'd1054 : mem_out_dec = 6'b001001;
12'd1055 : mem_out_dec = 6'b001010;
12'd1056 : mem_out_dec = 6'b001010;
12'd1057 : mem_out_dec = 6'b001011;
12'd1058 : mem_out_dec = 6'b001011;
12'd1059 : mem_out_dec = 6'b001100;
12'd1060 : mem_out_dec = 6'b001100;
12'd1061 : mem_out_dec = 6'b001100;
12'd1062 : mem_out_dec = 6'b001100;
12'd1063 : mem_out_dec = 6'b001100;
12'd1064 : mem_out_dec = 6'b001100;
12'd1065 : mem_out_dec = 6'b001100;
12'd1066 : mem_out_dec = 6'b001101;
12'd1067 : mem_out_dec = 6'b001101;
12'd1068 : mem_out_dec = 6'b001110;
12'd1069 : mem_out_dec = 6'b001111;
12'd1070 : mem_out_dec = 6'b010000;
12'd1071 : mem_out_dec = 6'b010000;
12'd1072 : mem_out_dec = 6'b010001;
12'd1073 : mem_out_dec = 6'b010001;
12'd1074 : mem_out_dec = 6'b010010;
12'd1075 : mem_out_dec = 6'b010010;
12'd1076 : mem_out_dec = 6'b010011;
12'd1077 : mem_out_dec = 6'b010011;
12'd1078 : mem_out_dec = 6'b010100;
12'd1079 : mem_out_dec = 6'b010101;
12'd1080 : mem_out_dec = 6'b010101;
12'd1081 : mem_out_dec = 6'b010110;
12'd1082 : mem_out_dec = 6'b010110;
12'd1083 : mem_out_dec = 6'b010111;
12'd1084 : mem_out_dec = 6'b011000;
12'd1085 : mem_out_dec = 6'b011000;
12'd1086 : mem_out_dec = 6'b011001;
12'd1087 : mem_out_dec = 6'b011010;
12'd1088 : mem_out_dec = 6'b111111;
12'd1089 : mem_out_dec = 6'b111111;
12'd1090 : mem_out_dec = 6'b111111;
12'd1091 : mem_out_dec = 6'b111111;
12'd1092 : mem_out_dec = 6'b111111;
12'd1093 : mem_out_dec = 6'b111111;
12'd1094 : mem_out_dec = 6'b111111;
12'd1095 : mem_out_dec = 6'b111111;
12'd1096 : mem_out_dec = 6'b111111;
12'd1097 : mem_out_dec = 6'b111111;
12'd1098 : mem_out_dec = 6'b111111;
12'd1099 : mem_out_dec = 6'b111111;
12'd1100 : mem_out_dec = 6'b111111;
12'd1101 : mem_out_dec = 6'b111111;
12'd1102 : mem_out_dec = 6'b111111;
12'd1103 : mem_out_dec = 6'b111111;
12'd1104 : mem_out_dec = 6'b111111;
12'd1105 : mem_out_dec = 6'b111111;
12'd1106 : mem_out_dec = 6'b111111;
12'd1107 : mem_out_dec = 6'b111111;
12'd1108 : mem_out_dec = 6'b111111;
12'd1109 : mem_out_dec = 6'b111111;
12'd1110 : mem_out_dec = 6'b111111;
12'd1111 : mem_out_dec = 6'b000100;
12'd1112 : mem_out_dec = 6'b000100;
12'd1113 : mem_out_dec = 6'b000101;
12'd1114 : mem_out_dec = 6'b000110;
12'd1115 : mem_out_dec = 6'b000111;
12'd1116 : mem_out_dec = 6'b000111;
12'd1117 : mem_out_dec = 6'b001000;
12'd1118 : mem_out_dec = 6'b001001;
12'd1119 : mem_out_dec = 6'b001001;
12'd1120 : mem_out_dec = 6'b001010;
12'd1121 : mem_out_dec = 6'b001010;
12'd1122 : mem_out_dec = 6'b001011;
12'd1123 : mem_out_dec = 6'b001011;
12'd1124 : mem_out_dec = 6'b001011;
12'd1125 : mem_out_dec = 6'b001011;
12'd1126 : mem_out_dec = 6'b001011;
12'd1127 : mem_out_dec = 6'b001011;
12'd1128 : mem_out_dec = 6'b001011;
12'd1129 : mem_out_dec = 6'b001011;
12'd1130 : mem_out_dec = 6'b001100;
12'd1131 : mem_out_dec = 6'b001101;
12'd1132 : mem_out_dec = 6'b001110;
12'd1133 : mem_out_dec = 6'b001110;
12'd1134 : mem_out_dec = 6'b001111;
12'd1135 : mem_out_dec = 6'b010000;
12'd1136 : mem_out_dec = 6'b010000;
12'd1137 : mem_out_dec = 6'b010001;
12'd1138 : mem_out_dec = 6'b010001;
12'd1139 : mem_out_dec = 6'b010010;
12'd1140 : mem_out_dec = 6'b010010;
12'd1141 : mem_out_dec = 6'b010011;
12'd1142 : mem_out_dec = 6'b010100;
12'd1143 : mem_out_dec = 6'b010100;
12'd1144 : mem_out_dec = 6'b010100;
12'd1145 : mem_out_dec = 6'b010101;
12'd1146 : mem_out_dec = 6'b010110;
12'd1147 : mem_out_dec = 6'b010110;
12'd1148 : mem_out_dec = 6'b010111;
12'd1149 : mem_out_dec = 6'b011000;
12'd1150 : mem_out_dec = 6'b011000;
12'd1151 : mem_out_dec = 6'b011001;
12'd1152 : mem_out_dec = 6'b111111;
12'd1153 : mem_out_dec = 6'b111111;
12'd1154 : mem_out_dec = 6'b111111;
12'd1155 : mem_out_dec = 6'b111111;
12'd1156 : mem_out_dec = 6'b111111;
12'd1157 : mem_out_dec = 6'b111111;
12'd1158 : mem_out_dec = 6'b111111;
12'd1159 : mem_out_dec = 6'b111111;
12'd1160 : mem_out_dec = 6'b111111;
12'd1161 : mem_out_dec = 6'b111111;
12'd1162 : mem_out_dec = 6'b111111;
12'd1163 : mem_out_dec = 6'b111111;
12'd1164 : mem_out_dec = 6'b111111;
12'd1165 : mem_out_dec = 6'b111111;
12'd1166 : mem_out_dec = 6'b111111;
12'd1167 : mem_out_dec = 6'b111111;
12'd1168 : mem_out_dec = 6'b111111;
12'd1169 : mem_out_dec = 6'b111111;
12'd1170 : mem_out_dec = 6'b111111;
12'd1171 : mem_out_dec = 6'b111111;
12'd1172 : mem_out_dec = 6'b111111;
12'd1173 : mem_out_dec = 6'b111111;
12'd1174 : mem_out_dec = 6'b111111;
12'd1175 : mem_out_dec = 6'b111111;
12'd1176 : mem_out_dec = 6'b000100;
12'd1177 : mem_out_dec = 6'b000101;
12'd1178 : mem_out_dec = 6'b000101;
12'd1179 : mem_out_dec = 6'b000110;
12'd1180 : mem_out_dec = 6'b000111;
12'd1181 : mem_out_dec = 6'b000111;
12'd1182 : mem_out_dec = 6'b001000;
12'd1183 : mem_out_dec = 6'b001001;
12'd1184 : mem_out_dec = 6'b001001;
12'd1185 : mem_out_dec = 6'b001010;
12'd1186 : mem_out_dec = 6'b001010;
12'd1187 : mem_out_dec = 6'b001010;
12'd1188 : mem_out_dec = 6'b001010;
12'd1189 : mem_out_dec = 6'b001010;
12'd1190 : mem_out_dec = 6'b001010;
12'd1191 : mem_out_dec = 6'b001010;
12'd1192 : mem_out_dec = 6'b001010;
12'd1193 : mem_out_dec = 6'b001011;
12'd1194 : mem_out_dec = 6'b001100;
12'd1195 : mem_out_dec = 6'b001100;
12'd1196 : mem_out_dec = 6'b001101;
12'd1197 : mem_out_dec = 6'b001110;
12'd1198 : mem_out_dec = 6'b001111;
12'd1199 : mem_out_dec = 6'b010000;
12'd1200 : mem_out_dec = 6'b010000;
12'd1201 : mem_out_dec = 6'b010000;
12'd1202 : mem_out_dec = 6'b010001;
12'd1203 : mem_out_dec = 6'b010001;
12'd1204 : mem_out_dec = 6'b010010;
12'd1205 : mem_out_dec = 6'b010011;
12'd1206 : mem_out_dec = 6'b010011;
12'd1207 : mem_out_dec = 6'b010100;
12'd1208 : mem_out_dec = 6'b010100;
12'd1209 : mem_out_dec = 6'b010100;
12'd1210 : mem_out_dec = 6'b010101;
12'd1211 : mem_out_dec = 6'b010110;
12'd1212 : mem_out_dec = 6'b010110;
12'd1213 : mem_out_dec = 6'b010111;
12'd1214 : mem_out_dec = 6'b011000;
12'd1215 : mem_out_dec = 6'b011001;
12'd1216 : mem_out_dec = 6'b111111;
12'd1217 : mem_out_dec = 6'b111111;
12'd1218 : mem_out_dec = 6'b111111;
12'd1219 : mem_out_dec = 6'b111111;
12'd1220 : mem_out_dec = 6'b111111;
12'd1221 : mem_out_dec = 6'b111111;
12'd1222 : mem_out_dec = 6'b111111;
12'd1223 : mem_out_dec = 6'b111111;
12'd1224 : mem_out_dec = 6'b111111;
12'd1225 : mem_out_dec = 6'b111111;
12'd1226 : mem_out_dec = 6'b111111;
12'd1227 : mem_out_dec = 6'b111111;
12'd1228 : mem_out_dec = 6'b111111;
12'd1229 : mem_out_dec = 6'b111111;
12'd1230 : mem_out_dec = 6'b111111;
12'd1231 : mem_out_dec = 6'b111111;
12'd1232 : mem_out_dec = 6'b111111;
12'd1233 : mem_out_dec = 6'b111111;
12'd1234 : mem_out_dec = 6'b111111;
12'd1235 : mem_out_dec = 6'b111111;
12'd1236 : mem_out_dec = 6'b111111;
12'd1237 : mem_out_dec = 6'b111111;
12'd1238 : mem_out_dec = 6'b111111;
12'd1239 : mem_out_dec = 6'b111111;
12'd1240 : mem_out_dec = 6'b111111;
12'd1241 : mem_out_dec = 6'b000100;
12'd1242 : mem_out_dec = 6'b000100;
12'd1243 : mem_out_dec = 6'b000101;
12'd1244 : mem_out_dec = 6'b000110;
12'd1245 : mem_out_dec = 6'b000111;
12'd1246 : mem_out_dec = 6'b001000;
12'd1247 : mem_out_dec = 6'b001000;
12'd1248 : mem_out_dec = 6'b001001;
12'd1249 : mem_out_dec = 6'b001001;
12'd1250 : mem_out_dec = 6'b001001;
12'd1251 : mem_out_dec = 6'b001001;
12'd1252 : mem_out_dec = 6'b001001;
12'd1253 : mem_out_dec = 6'b001001;
12'd1254 : mem_out_dec = 6'b001001;
12'd1255 : mem_out_dec = 6'b001001;
12'd1256 : mem_out_dec = 6'b001010;
12'd1257 : mem_out_dec = 6'b001010;
12'd1258 : mem_out_dec = 6'b001011;
12'd1259 : mem_out_dec = 6'b001100;
12'd1260 : mem_out_dec = 6'b001101;
12'd1261 : mem_out_dec = 6'b001110;
12'd1262 : mem_out_dec = 6'b001110;
12'd1263 : mem_out_dec = 6'b001111;
12'd1264 : mem_out_dec = 6'b001111;
12'd1265 : mem_out_dec = 6'b010000;
12'd1266 : mem_out_dec = 6'b010000;
12'd1267 : mem_out_dec = 6'b010001;
12'd1268 : mem_out_dec = 6'b010001;
12'd1269 : mem_out_dec = 6'b010010;
12'd1270 : mem_out_dec = 6'b010011;
12'd1271 : mem_out_dec = 6'b010011;
12'd1272 : mem_out_dec = 6'b010011;
12'd1273 : mem_out_dec = 6'b010100;
12'd1274 : mem_out_dec = 6'b010100;
12'd1275 : mem_out_dec = 6'b010101;
12'd1276 : mem_out_dec = 6'b010110;
12'd1277 : mem_out_dec = 6'b010111;
12'd1278 : mem_out_dec = 6'b011000;
12'd1279 : mem_out_dec = 6'b011000;
12'd1280 : mem_out_dec = 6'b111111;
12'd1281 : mem_out_dec = 6'b111111;
12'd1282 : mem_out_dec = 6'b111111;
12'd1283 : mem_out_dec = 6'b111111;
12'd1284 : mem_out_dec = 6'b111111;
12'd1285 : mem_out_dec = 6'b111111;
12'd1286 : mem_out_dec = 6'b111111;
12'd1287 : mem_out_dec = 6'b111111;
12'd1288 : mem_out_dec = 6'b111111;
12'd1289 : mem_out_dec = 6'b111111;
12'd1290 : mem_out_dec = 6'b111111;
12'd1291 : mem_out_dec = 6'b111111;
12'd1292 : mem_out_dec = 6'b111111;
12'd1293 : mem_out_dec = 6'b111111;
12'd1294 : mem_out_dec = 6'b111111;
12'd1295 : mem_out_dec = 6'b111111;
12'd1296 : mem_out_dec = 6'b111111;
12'd1297 : mem_out_dec = 6'b111111;
12'd1298 : mem_out_dec = 6'b111111;
12'd1299 : mem_out_dec = 6'b111111;
12'd1300 : mem_out_dec = 6'b111111;
12'd1301 : mem_out_dec = 6'b111111;
12'd1302 : mem_out_dec = 6'b111111;
12'd1303 : mem_out_dec = 6'b111111;
12'd1304 : mem_out_dec = 6'b111111;
12'd1305 : mem_out_dec = 6'b111111;
12'd1306 : mem_out_dec = 6'b000100;
12'd1307 : mem_out_dec = 6'b000101;
12'd1308 : mem_out_dec = 6'b000110;
12'd1309 : mem_out_dec = 6'b000110;
12'd1310 : mem_out_dec = 6'b000111;
12'd1311 : mem_out_dec = 6'b001000;
12'd1312 : mem_out_dec = 6'b001000;
12'd1313 : mem_out_dec = 6'b001000;
12'd1314 : mem_out_dec = 6'b001000;
12'd1315 : mem_out_dec = 6'b001000;
12'd1316 : mem_out_dec = 6'b001000;
12'd1317 : mem_out_dec = 6'b001000;
12'd1318 : mem_out_dec = 6'b001000;
12'd1319 : mem_out_dec = 6'b001001;
12'd1320 : mem_out_dec = 6'b001001;
12'd1321 : mem_out_dec = 6'b001010;
12'd1322 : mem_out_dec = 6'b001011;
12'd1323 : mem_out_dec = 6'b001100;
12'd1324 : mem_out_dec = 6'b001100;
12'd1325 : mem_out_dec = 6'b001101;
12'd1326 : mem_out_dec = 6'b001110;
12'd1327 : mem_out_dec = 6'b001111;
12'd1328 : mem_out_dec = 6'b001111;
12'd1329 : mem_out_dec = 6'b001111;
12'd1330 : mem_out_dec = 6'b010000;
12'd1331 : mem_out_dec = 6'b010000;
12'd1332 : mem_out_dec = 6'b010001;
12'd1333 : mem_out_dec = 6'b010001;
12'd1334 : mem_out_dec = 6'b010010;
12'd1335 : mem_out_dec = 6'b010011;
12'd1336 : mem_out_dec = 6'b010010;
12'd1337 : mem_out_dec = 6'b010011;
12'd1338 : mem_out_dec = 6'b010100;
12'd1339 : mem_out_dec = 6'b010101;
12'd1340 : mem_out_dec = 6'b010110;
12'd1341 : mem_out_dec = 6'b010110;
12'd1342 : mem_out_dec = 6'b010111;
12'd1343 : mem_out_dec = 6'b011000;
12'd1344 : mem_out_dec = 6'b111111;
12'd1345 : mem_out_dec = 6'b111111;
12'd1346 : mem_out_dec = 6'b111111;
12'd1347 : mem_out_dec = 6'b111111;
12'd1348 : mem_out_dec = 6'b111111;
12'd1349 : mem_out_dec = 6'b111111;
12'd1350 : mem_out_dec = 6'b111111;
12'd1351 : mem_out_dec = 6'b111111;
12'd1352 : mem_out_dec = 6'b111111;
12'd1353 : mem_out_dec = 6'b111111;
12'd1354 : mem_out_dec = 6'b111111;
12'd1355 : mem_out_dec = 6'b111111;
12'd1356 : mem_out_dec = 6'b111111;
12'd1357 : mem_out_dec = 6'b111111;
12'd1358 : mem_out_dec = 6'b111111;
12'd1359 : mem_out_dec = 6'b111111;
12'd1360 : mem_out_dec = 6'b111111;
12'd1361 : mem_out_dec = 6'b111111;
12'd1362 : mem_out_dec = 6'b111111;
12'd1363 : mem_out_dec = 6'b111111;
12'd1364 : mem_out_dec = 6'b111111;
12'd1365 : mem_out_dec = 6'b111111;
12'd1366 : mem_out_dec = 6'b111111;
12'd1367 : mem_out_dec = 6'b111111;
12'd1368 : mem_out_dec = 6'b111111;
12'd1369 : mem_out_dec = 6'b111111;
12'd1370 : mem_out_dec = 6'b111111;
12'd1371 : mem_out_dec = 6'b000101;
12'd1372 : mem_out_dec = 6'b000101;
12'd1373 : mem_out_dec = 6'b000110;
12'd1374 : mem_out_dec = 6'b000111;
12'd1375 : mem_out_dec = 6'b001000;
12'd1376 : mem_out_dec = 6'b000111;
12'd1377 : mem_out_dec = 6'b000111;
12'd1378 : mem_out_dec = 6'b000111;
12'd1379 : mem_out_dec = 6'b000111;
12'd1380 : mem_out_dec = 6'b000111;
12'd1381 : mem_out_dec = 6'b000111;
12'd1382 : mem_out_dec = 6'b001000;
12'd1383 : mem_out_dec = 6'b001001;
12'd1384 : mem_out_dec = 6'b001001;
12'd1385 : mem_out_dec = 6'b001010;
12'd1386 : mem_out_dec = 6'b001010;
12'd1387 : mem_out_dec = 6'b001011;
12'd1388 : mem_out_dec = 6'b001100;
12'd1389 : mem_out_dec = 6'b001101;
12'd1390 : mem_out_dec = 6'b001110;
12'd1391 : mem_out_dec = 6'b001110;
12'd1392 : mem_out_dec = 6'b001111;
12'd1393 : mem_out_dec = 6'b001111;
12'd1394 : mem_out_dec = 6'b010000;
12'd1395 : mem_out_dec = 6'b010000;
12'd1396 : mem_out_dec = 6'b010001;
12'd1397 : mem_out_dec = 6'b010001;
12'd1398 : mem_out_dec = 6'b010010;
12'd1399 : mem_out_dec = 6'b010010;
12'd1400 : mem_out_dec = 6'b010010;
12'd1401 : mem_out_dec = 6'b010011;
12'd1402 : mem_out_dec = 6'b010100;
12'd1403 : mem_out_dec = 6'b010100;
12'd1404 : mem_out_dec = 6'b010101;
12'd1405 : mem_out_dec = 6'b010110;
12'd1406 : mem_out_dec = 6'b010111;
12'd1407 : mem_out_dec = 6'b010111;
12'd1408 : mem_out_dec = 6'b111111;
12'd1409 : mem_out_dec = 6'b111111;
12'd1410 : mem_out_dec = 6'b111111;
12'd1411 : mem_out_dec = 6'b111111;
12'd1412 : mem_out_dec = 6'b111111;
12'd1413 : mem_out_dec = 6'b111111;
12'd1414 : mem_out_dec = 6'b111111;
12'd1415 : mem_out_dec = 6'b111111;
12'd1416 : mem_out_dec = 6'b111111;
12'd1417 : mem_out_dec = 6'b111111;
12'd1418 : mem_out_dec = 6'b111111;
12'd1419 : mem_out_dec = 6'b111111;
12'd1420 : mem_out_dec = 6'b111111;
12'd1421 : mem_out_dec = 6'b111111;
12'd1422 : mem_out_dec = 6'b111111;
12'd1423 : mem_out_dec = 6'b111111;
12'd1424 : mem_out_dec = 6'b111111;
12'd1425 : mem_out_dec = 6'b111111;
12'd1426 : mem_out_dec = 6'b111111;
12'd1427 : mem_out_dec = 6'b111111;
12'd1428 : mem_out_dec = 6'b111111;
12'd1429 : mem_out_dec = 6'b111111;
12'd1430 : mem_out_dec = 6'b111111;
12'd1431 : mem_out_dec = 6'b111111;
12'd1432 : mem_out_dec = 6'b111111;
12'd1433 : mem_out_dec = 6'b111111;
12'd1434 : mem_out_dec = 6'b111111;
12'd1435 : mem_out_dec = 6'b111111;
12'd1436 : mem_out_dec = 6'b000101;
12'd1437 : mem_out_dec = 6'b000110;
12'd1438 : mem_out_dec = 6'b000111;
12'd1439 : mem_out_dec = 6'b000111;
12'd1440 : mem_out_dec = 6'b000110;
12'd1441 : mem_out_dec = 6'b000110;
12'd1442 : mem_out_dec = 6'b000110;
12'd1443 : mem_out_dec = 6'b000110;
12'd1444 : mem_out_dec = 6'b000110;
12'd1445 : mem_out_dec = 6'b000111;
12'd1446 : mem_out_dec = 6'b000111;
12'd1447 : mem_out_dec = 6'b001000;
12'd1448 : mem_out_dec = 6'b001001;
12'd1449 : mem_out_dec = 6'b001001;
12'd1450 : mem_out_dec = 6'b001010;
12'd1451 : mem_out_dec = 6'b001011;
12'd1452 : mem_out_dec = 6'b001100;
12'd1453 : mem_out_dec = 6'b001100;
12'd1454 : mem_out_dec = 6'b001101;
12'd1455 : mem_out_dec = 6'b001110;
12'd1456 : mem_out_dec = 6'b001110;
12'd1457 : mem_out_dec = 6'b001111;
12'd1458 : mem_out_dec = 6'b001111;
12'd1459 : mem_out_dec = 6'b010000;
12'd1460 : mem_out_dec = 6'b010000;
12'd1461 : mem_out_dec = 6'b010001;
12'd1462 : mem_out_dec = 6'b010001;
12'd1463 : mem_out_dec = 6'b010010;
12'd1464 : mem_out_dec = 6'b010010;
12'd1465 : mem_out_dec = 6'b010011;
12'd1466 : mem_out_dec = 6'b010011;
12'd1467 : mem_out_dec = 6'b010100;
12'd1468 : mem_out_dec = 6'b010101;
12'd1469 : mem_out_dec = 6'b010110;
12'd1470 : mem_out_dec = 6'b010110;
12'd1471 : mem_out_dec = 6'b010111;
12'd1472 : mem_out_dec = 6'b111111;
12'd1473 : mem_out_dec = 6'b111111;
12'd1474 : mem_out_dec = 6'b111111;
12'd1475 : mem_out_dec = 6'b111111;
12'd1476 : mem_out_dec = 6'b111111;
12'd1477 : mem_out_dec = 6'b111111;
12'd1478 : mem_out_dec = 6'b111111;
12'd1479 : mem_out_dec = 6'b111111;
12'd1480 : mem_out_dec = 6'b111111;
12'd1481 : mem_out_dec = 6'b111111;
12'd1482 : mem_out_dec = 6'b111111;
12'd1483 : mem_out_dec = 6'b111111;
12'd1484 : mem_out_dec = 6'b111111;
12'd1485 : mem_out_dec = 6'b111111;
12'd1486 : mem_out_dec = 6'b111111;
12'd1487 : mem_out_dec = 6'b111111;
12'd1488 : mem_out_dec = 6'b111111;
12'd1489 : mem_out_dec = 6'b111111;
12'd1490 : mem_out_dec = 6'b111111;
12'd1491 : mem_out_dec = 6'b111111;
12'd1492 : mem_out_dec = 6'b111111;
12'd1493 : mem_out_dec = 6'b111111;
12'd1494 : mem_out_dec = 6'b111111;
12'd1495 : mem_out_dec = 6'b111111;
12'd1496 : mem_out_dec = 6'b111111;
12'd1497 : mem_out_dec = 6'b111111;
12'd1498 : mem_out_dec = 6'b111111;
12'd1499 : mem_out_dec = 6'b111111;
12'd1500 : mem_out_dec = 6'b111111;
12'd1501 : mem_out_dec = 6'b000101;
12'd1502 : mem_out_dec = 6'b000110;
12'd1503 : mem_out_dec = 6'b000110;
12'd1504 : mem_out_dec = 6'b000110;
12'd1505 : mem_out_dec = 6'b000110;
12'd1506 : mem_out_dec = 6'b000101;
12'd1507 : mem_out_dec = 6'b000101;
12'd1508 : mem_out_dec = 6'b000110;
12'd1509 : mem_out_dec = 6'b000111;
12'd1510 : mem_out_dec = 6'b000111;
12'd1511 : mem_out_dec = 6'b001000;
12'd1512 : mem_out_dec = 6'b001000;
12'd1513 : mem_out_dec = 6'b001001;
12'd1514 : mem_out_dec = 6'b001010;
12'd1515 : mem_out_dec = 6'b001011;
12'd1516 : mem_out_dec = 6'b001011;
12'd1517 : mem_out_dec = 6'b001100;
12'd1518 : mem_out_dec = 6'b001101;
12'd1519 : mem_out_dec = 6'b001110;
12'd1520 : mem_out_dec = 6'b001110;
12'd1521 : mem_out_dec = 6'b001110;
12'd1522 : mem_out_dec = 6'b001111;
12'd1523 : mem_out_dec = 6'b001111;
12'd1524 : mem_out_dec = 6'b010000;
12'd1525 : mem_out_dec = 6'b010000;
12'd1526 : mem_out_dec = 6'b010001;
12'd1527 : mem_out_dec = 6'b010001;
12'd1528 : mem_out_dec = 6'b010001;
12'd1529 : mem_out_dec = 6'b010010;
12'd1530 : mem_out_dec = 6'b010011;
12'd1531 : mem_out_dec = 6'b010100;
12'd1532 : mem_out_dec = 6'b010101;
12'd1533 : mem_out_dec = 6'b010101;
12'd1534 : mem_out_dec = 6'b010110;
12'd1535 : mem_out_dec = 6'b010110;
12'd1536 : mem_out_dec = 6'b111111;
12'd1537 : mem_out_dec = 6'b111111;
12'd1538 : mem_out_dec = 6'b111111;
12'd1539 : mem_out_dec = 6'b111111;
12'd1540 : mem_out_dec = 6'b111111;
12'd1541 : mem_out_dec = 6'b111111;
12'd1542 : mem_out_dec = 6'b111111;
12'd1543 : mem_out_dec = 6'b111111;
12'd1544 : mem_out_dec = 6'b111111;
12'd1545 : mem_out_dec = 6'b111111;
12'd1546 : mem_out_dec = 6'b111111;
12'd1547 : mem_out_dec = 6'b111111;
12'd1548 : mem_out_dec = 6'b111111;
12'd1549 : mem_out_dec = 6'b111111;
12'd1550 : mem_out_dec = 6'b111111;
12'd1551 : mem_out_dec = 6'b111111;
12'd1552 : mem_out_dec = 6'b111111;
12'd1553 : mem_out_dec = 6'b111111;
12'd1554 : mem_out_dec = 6'b111111;
12'd1555 : mem_out_dec = 6'b111111;
12'd1556 : mem_out_dec = 6'b111111;
12'd1557 : mem_out_dec = 6'b111111;
12'd1558 : mem_out_dec = 6'b111111;
12'd1559 : mem_out_dec = 6'b111111;
12'd1560 : mem_out_dec = 6'b111111;
12'd1561 : mem_out_dec = 6'b111111;
12'd1562 : mem_out_dec = 6'b111111;
12'd1563 : mem_out_dec = 6'b111111;
12'd1564 : mem_out_dec = 6'b111111;
12'd1565 : mem_out_dec = 6'b111111;
12'd1566 : mem_out_dec = 6'b000100;
12'd1567 : mem_out_dec = 6'b000100;
12'd1568 : mem_out_dec = 6'b000100;
12'd1569 : mem_out_dec = 6'b000100;
12'd1570 : mem_out_dec = 6'b000100;
12'd1571 : mem_out_dec = 6'b000101;
12'd1572 : mem_out_dec = 6'b000101;
12'd1573 : mem_out_dec = 6'b000110;
12'd1574 : mem_out_dec = 6'b000111;
12'd1575 : mem_out_dec = 6'b000111;
12'd1576 : mem_out_dec = 6'b000111;
12'd1577 : mem_out_dec = 6'b001000;
12'd1578 : mem_out_dec = 6'b001001;
12'd1579 : mem_out_dec = 6'b001010;
12'd1580 : mem_out_dec = 6'b001010;
12'd1581 : mem_out_dec = 6'b001011;
12'd1582 : mem_out_dec = 6'b001100;
12'd1583 : mem_out_dec = 6'b001101;
12'd1584 : mem_out_dec = 6'b001101;
12'd1585 : mem_out_dec = 6'b001101;
12'd1586 : mem_out_dec = 6'b001110;
12'd1587 : mem_out_dec = 6'b001110;
12'd1588 : mem_out_dec = 6'b001111;
12'd1589 : mem_out_dec = 6'b001111;
12'd1590 : mem_out_dec = 6'b010000;
12'd1591 : mem_out_dec = 6'b010001;
12'd1592 : mem_out_dec = 6'b010001;
12'd1593 : mem_out_dec = 6'b010001;
12'd1594 : mem_out_dec = 6'b010010;
12'd1595 : mem_out_dec = 6'b010010;
12'd1596 : mem_out_dec = 6'b010011;
12'd1597 : mem_out_dec = 6'b010011;
12'd1598 : mem_out_dec = 6'b010100;
12'd1599 : mem_out_dec = 6'b010100;
12'd1600 : mem_out_dec = 6'b111111;
12'd1601 : mem_out_dec = 6'b111111;
12'd1602 : mem_out_dec = 6'b111111;
12'd1603 : mem_out_dec = 6'b111111;
12'd1604 : mem_out_dec = 6'b111111;
12'd1605 : mem_out_dec = 6'b111111;
12'd1606 : mem_out_dec = 6'b111111;
12'd1607 : mem_out_dec = 6'b111111;
12'd1608 : mem_out_dec = 6'b111111;
12'd1609 : mem_out_dec = 6'b111111;
12'd1610 : mem_out_dec = 6'b111111;
12'd1611 : mem_out_dec = 6'b111111;
12'd1612 : mem_out_dec = 6'b111111;
12'd1613 : mem_out_dec = 6'b111111;
12'd1614 : mem_out_dec = 6'b111111;
12'd1615 : mem_out_dec = 6'b111111;
12'd1616 : mem_out_dec = 6'b111111;
12'd1617 : mem_out_dec = 6'b111111;
12'd1618 : mem_out_dec = 6'b111111;
12'd1619 : mem_out_dec = 6'b111111;
12'd1620 : mem_out_dec = 6'b111111;
12'd1621 : mem_out_dec = 6'b111111;
12'd1622 : mem_out_dec = 6'b111111;
12'd1623 : mem_out_dec = 6'b111111;
12'd1624 : mem_out_dec = 6'b111111;
12'd1625 : mem_out_dec = 6'b111111;
12'd1626 : mem_out_dec = 6'b111111;
12'd1627 : mem_out_dec = 6'b111111;
12'd1628 : mem_out_dec = 6'b111111;
12'd1629 : mem_out_dec = 6'b111111;
12'd1630 : mem_out_dec = 6'b111111;
12'd1631 : mem_out_dec = 6'b000100;
12'd1632 : mem_out_dec = 6'b000011;
12'd1633 : mem_out_dec = 6'b000011;
12'd1634 : mem_out_dec = 6'b000100;
12'd1635 : mem_out_dec = 6'b000100;
12'd1636 : mem_out_dec = 6'b000101;
12'd1637 : mem_out_dec = 6'b000110;
12'd1638 : mem_out_dec = 6'b000110;
12'd1639 : mem_out_dec = 6'b000111;
12'd1640 : mem_out_dec = 6'b000111;
12'd1641 : mem_out_dec = 6'b001000;
12'd1642 : mem_out_dec = 6'b001001;
12'd1643 : mem_out_dec = 6'b001001;
12'd1644 : mem_out_dec = 6'b001010;
12'd1645 : mem_out_dec = 6'b001011;
12'd1646 : mem_out_dec = 6'b001100;
12'd1647 : mem_out_dec = 6'b001101;
12'd1648 : mem_out_dec = 6'b001101;
12'd1649 : mem_out_dec = 6'b001101;
12'd1650 : mem_out_dec = 6'b001110;
12'd1651 : mem_out_dec = 6'b001110;
12'd1652 : mem_out_dec = 6'b001110;
12'd1653 : mem_out_dec = 6'b001111;
12'd1654 : mem_out_dec = 6'b010000;
12'd1655 : mem_out_dec = 6'b010000;
12'd1656 : mem_out_dec = 6'b010001;
12'd1657 : mem_out_dec = 6'b010001;
12'd1658 : mem_out_dec = 6'b010001;
12'd1659 : mem_out_dec = 6'b010010;
12'd1660 : mem_out_dec = 6'b010010;
12'd1661 : mem_out_dec = 6'b010011;
12'd1662 : mem_out_dec = 6'b010011;
12'd1663 : mem_out_dec = 6'b010100;
12'd1664 : mem_out_dec = 6'b111111;
12'd1665 : mem_out_dec = 6'b111111;
12'd1666 : mem_out_dec = 6'b111111;
12'd1667 : mem_out_dec = 6'b111111;
12'd1668 : mem_out_dec = 6'b111111;
12'd1669 : mem_out_dec = 6'b111111;
12'd1670 : mem_out_dec = 6'b111111;
12'd1671 : mem_out_dec = 6'b111111;
12'd1672 : mem_out_dec = 6'b111111;
12'd1673 : mem_out_dec = 6'b111111;
12'd1674 : mem_out_dec = 6'b111111;
12'd1675 : mem_out_dec = 6'b111111;
12'd1676 : mem_out_dec = 6'b111111;
12'd1677 : mem_out_dec = 6'b111111;
12'd1678 : mem_out_dec = 6'b111111;
12'd1679 : mem_out_dec = 6'b111111;
12'd1680 : mem_out_dec = 6'b111111;
12'd1681 : mem_out_dec = 6'b111111;
12'd1682 : mem_out_dec = 6'b111111;
12'd1683 : mem_out_dec = 6'b111111;
12'd1684 : mem_out_dec = 6'b111111;
12'd1685 : mem_out_dec = 6'b111111;
12'd1686 : mem_out_dec = 6'b111111;
12'd1687 : mem_out_dec = 6'b111111;
12'd1688 : mem_out_dec = 6'b111111;
12'd1689 : mem_out_dec = 6'b111111;
12'd1690 : mem_out_dec = 6'b111111;
12'd1691 : mem_out_dec = 6'b111111;
12'd1692 : mem_out_dec = 6'b111111;
12'd1693 : mem_out_dec = 6'b111111;
12'd1694 : mem_out_dec = 6'b111111;
12'd1695 : mem_out_dec = 6'b111111;
12'd1696 : mem_out_dec = 6'b000011;
12'd1697 : mem_out_dec = 6'b000011;
12'd1698 : mem_out_dec = 6'b000100;
12'd1699 : mem_out_dec = 6'b000100;
12'd1700 : mem_out_dec = 6'b000101;
12'd1701 : mem_out_dec = 6'b000101;
12'd1702 : mem_out_dec = 6'b000110;
12'd1703 : mem_out_dec = 6'b000111;
12'd1704 : mem_out_dec = 6'b000111;
12'd1705 : mem_out_dec = 6'b001000;
12'd1706 : mem_out_dec = 6'b001000;
12'd1707 : mem_out_dec = 6'b001001;
12'd1708 : mem_out_dec = 6'b001010;
12'd1709 : mem_out_dec = 6'b001011;
12'd1710 : mem_out_dec = 6'b001100;
12'd1711 : mem_out_dec = 6'b001100;
12'd1712 : mem_out_dec = 6'b001100;
12'd1713 : mem_out_dec = 6'b001101;
12'd1714 : mem_out_dec = 6'b001101;
12'd1715 : mem_out_dec = 6'b001110;
12'd1716 : mem_out_dec = 6'b001110;
12'd1717 : mem_out_dec = 6'b001111;
12'd1718 : mem_out_dec = 6'b001111;
12'd1719 : mem_out_dec = 6'b010000;
12'd1720 : mem_out_dec = 6'b010000;
12'd1721 : mem_out_dec = 6'b010000;
12'd1722 : mem_out_dec = 6'b010001;
12'd1723 : mem_out_dec = 6'b010001;
12'd1724 : mem_out_dec = 6'b010010;
12'd1725 : mem_out_dec = 6'b010010;
12'd1726 : mem_out_dec = 6'b010011;
12'd1727 : mem_out_dec = 6'b010011;
12'd1728 : mem_out_dec = 6'b111111;
12'd1729 : mem_out_dec = 6'b111111;
12'd1730 : mem_out_dec = 6'b111111;
12'd1731 : mem_out_dec = 6'b111111;
12'd1732 : mem_out_dec = 6'b111111;
12'd1733 : mem_out_dec = 6'b111111;
12'd1734 : mem_out_dec = 6'b111111;
12'd1735 : mem_out_dec = 6'b111111;
12'd1736 : mem_out_dec = 6'b111111;
12'd1737 : mem_out_dec = 6'b111111;
12'd1738 : mem_out_dec = 6'b111111;
12'd1739 : mem_out_dec = 6'b111111;
12'd1740 : mem_out_dec = 6'b111111;
12'd1741 : mem_out_dec = 6'b111111;
12'd1742 : mem_out_dec = 6'b111111;
12'd1743 : mem_out_dec = 6'b111111;
12'd1744 : mem_out_dec = 6'b111111;
12'd1745 : mem_out_dec = 6'b111111;
12'd1746 : mem_out_dec = 6'b111111;
12'd1747 : mem_out_dec = 6'b111111;
12'd1748 : mem_out_dec = 6'b111111;
12'd1749 : mem_out_dec = 6'b111111;
12'd1750 : mem_out_dec = 6'b111111;
12'd1751 : mem_out_dec = 6'b111111;
12'd1752 : mem_out_dec = 6'b111111;
12'd1753 : mem_out_dec = 6'b111111;
12'd1754 : mem_out_dec = 6'b111111;
12'd1755 : mem_out_dec = 6'b111111;
12'd1756 : mem_out_dec = 6'b111111;
12'd1757 : mem_out_dec = 6'b111111;
12'd1758 : mem_out_dec = 6'b111111;
12'd1759 : mem_out_dec = 6'b111111;
12'd1760 : mem_out_dec = 6'b111111;
12'd1761 : mem_out_dec = 6'b000011;
12'd1762 : mem_out_dec = 6'b000011;
12'd1763 : mem_out_dec = 6'b000100;
12'd1764 : mem_out_dec = 6'b000101;
12'd1765 : mem_out_dec = 6'b000101;
12'd1766 : mem_out_dec = 6'b000110;
12'd1767 : mem_out_dec = 6'b000111;
12'd1768 : mem_out_dec = 6'b000111;
12'd1769 : mem_out_dec = 6'b000111;
12'd1770 : mem_out_dec = 6'b001000;
12'd1771 : mem_out_dec = 6'b001001;
12'd1772 : mem_out_dec = 6'b001010;
12'd1773 : mem_out_dec = 6'b001011;
12'd1774 : mem_out_dec = 6'b001011;
12'd1775 : mem_out_dec = 6'b001100;
12'd1776 : mem_out_dec = 6'b001100;
12'd1777 : mem_out_dec = 6'b001101;
12'd1778 : mem_out_dec = 6'b001101;
12'd1779 : mem_out_dec = 6'b001101;
12'd1780 : mem_out_dec = 6'b001110;
12'd1781 : mem_out_dec = 6'b001111;
12'd1782 : mem_out_dec = 6'b001111;
12'd1783 : mem_out_dec = 6'b010000;
12'd1784 : mem_out_dec = 6'b010000;
12'd1785 : mem_out_dec = 6'b010000;
12'd1786 : mem_out_dec = 6'b010000;
12'd1787 : mem_out_dec = 6'b010001;
12'd1788 : mem_out_dec = 6'b010001;
12'd1789 : mem_out_dec = 6'b010010;
12'd1790 : mem_out_dec = 6'b010010;
12'd1791 : mem_out_dec = 6'b010011;
12'd1792 : mem_out_dec = 6'b111111;
12'd1793 : mem_out_dec = 6'b111111;
12'd1794 : mem_out_dec = 6'b111111;
12'd1795 : mem_out_dec = 6'b111111;
12'd1796 : mem_out_dec = 6'b111111;
12'd1797 : mem_out_dec = 6'b111111;
12'd1798 : mem_out_dec = 6'b111111;
12'd1799 : mem_out_dec = 6'b111111;
12'd1800 : mem_out_dec = 6'b111111;
12'd1801 : mem_out_dec = 6'b111111;
12'd1802 : mem_out_dec = 6'b111111;
12'd1803 : mem_out_dec = 6'b111111;
12'd1804 : mem_out_dec = 6'b111111;
12'd1805 : mem_out_dec = 6'b111111;
12'd1806 : mem_out_dec = 6'b111111;
12'd1807 : mem_out_dec = 6'b111111;
12'd1808 : mem_out_dec = 6'b111111;
12'd1809 : mem_out_dec = 6'b111111;
12'd1810 : mem_out_dec = 6'b111111;
12'd1811 : mem_out_dec = 6'b111111;
12'd1812 : mem_out_dec = 6'b111111;
12'd1813 : mem_out_dec = 6'b111111;
12'd1814 : mem_out_dec = 6'b111111;
12'd1815 : mem_out_dec = 6'b111111;
12'd1816 : mem_out_dec = 6'b111111;
12'd1817 : mem_out_dec = 6'b111111;
12'd1818 : mem_out_dec = 6'b111111;
12'd1819 : mem_out_dec = 6'b111111;
12'd1820 : mem_out_dec = 6'b111111;
12'd1821 : mem_out_dec = 6'b111111;
12'd1822 : mem_out_dec = 6'b111111;
12'd1823 : mem_out_dec = 6'b111111;
12'd1824 : mem_out_dec = 6'b111111;
12'd1825 : mem_out_dec = 6'b111111;
12'd1826 : mem_out_dec = 6'b000011;
12'd1827 : mem_out_dec = 6'b000100;
12'd1828 : mem_out_dec = 6'b000100;
12'd1829 : mem_out_dec = 6'b000101;
12'd1830 : mem_out_dec = 6'b000110;
12'd1831 : mem_out_dec = 6'b000110;
12'd1832 : mem_out_dec = 6'b000110;
12'd1833 : mem_out_dec = 6'b000111;
12'd1834 : mem_out_dec = 6'b001000;
12'd1835 : mem_out_dec = 6'b001001;
12'd1836 : mem_out_dec = 6'b001010;
12'd1837 : mem_out_dec = 6'b001010;
12'd1838 : mem_out_dec = 6'b001011;
12'd1839 : mem_out_dec = 6'b001100;
12'd1840 : mem_out_dec = 6'b001100;
12'd1841 : mem_out_dec = 6'b001100;
12'd1842 : mem_out_dec = 6'b001101;
12'd1843 : mem_out_dec = 6'b001101;
12'd1844 : mem_out_dec = 6'b001110;
12'd1845 : mem_out_dec = 6'b001110;
12'd1846 : mem_out_dec = 6'b001111;
12'd1847 : mem_out_dec = 6'b010000;
12'd1848 : mem_out_dec = 6'b001111;
12'd1849 : mem_out_dec = 6'b001111;
12'd1850 : mem_out_dec = 6'b010000;
12'd1851 : mem_out_dec = 6'b010000;
12'd1852 : mem_out_dec = 6'b010001;
12'd1853 : mem_out_dec = 6'b010001;
12'd1854 : mem_out_dec = 6'b010010;
12'd1855 : mem_out_dec = 6'b010010;
12'd1856 : mem_out_dec = 6'b111111;
12'd1857 : mem_out_dec = 6'b111111;
12'd1858 : mem_out_dec = 6'b111111;
12'd1859 : mem_out_dec = 6'b111111;
12'd1860 : mem_out_dec = 6'b111111;
12'd1861 : mem_out_dec = 6'b111111;
12'd1862 : mem_out_dec = 6'b111111;
12'd1863 : mem_out_dec = 6'b111111;
12'd1864 : mem_out_dec = 6'b111111;
12'd1865 : mem_out_dec = 6'b111111;
12'd1866 : mem_out_dec = 6'b111111;
12'd1867 : mem_out_dec = 6'b111111;
12'd1868 : mem_out_dec = 6'b111111;
12'd1869 : mem_out_dec = 6'b111111;
12'd1870 : mem_out_dec = 6'b111111;
12'd1871 : mem_out_dec = 6'b111111;
12'd1872 : mem_out_dec = 6'b111111;
12'd1873 : mem_out_dec = 6'b111111;
12'd1874 : mem_out_dec = 6'b111111;
12'd1875 : mem_out_dec = 6'b111111;
12'd1876 : mem_out_dec = 6'b111111;
12'd1877 : mem_out_dec = 6'b111111;
12'd1878 : mem_out_dec = 6'b111111;
12'd1879 : mem_out_dec = 6'b111111;
12'd1880 : mem_out_dec = 6'b111111;
12'd1881 : mem_out_dec = 6'b111111;
12'd1882 : mem_out_dec = 6'b111111;
12'd1883 : mem_out_dec = 6'b111111;
12'd1884 : mem_out_dec = 6'b111111;
12'd1885 : mem_out_dec = 6'b111111;
12'd1886 : mem_out_dec = 6'b111111;
12'd1887 : mem_out_dec = 6'b111111;
12'd1888 : mem_out_dec = 6'b111111;
12'd1889 : mem_out_dec = 6'b111111;
12'd1890 : mem_out_dec = 6'b111111;
12'd1891 : mem_out_dec = 6'b000100;
12'd1892 : mem_out_dec = 6'b000100;
12'd1893 : mem_out_dec = 6'b000101;
12'd1894 : mem_out_dec = 6'b000101;
12'd1895 : mem_out_dec = 6'b000110;
12'd1896 : mem_out_dec = 6'b000110;
12'd1897 : mem_out_dec = 6'b000111;
12'd1898 : mem_out_dec = 6'b001000;
12'd1899 : mem_out_dec = 6'b001001;
12'd1900 : mem_out_dec = 6'b001001;
12'd1901 : mem_out_dec = 6'b001010;
12'd1902 : mem_out_dec = 6'b001011;
12'd1903 : mem_out_dec = 6'b001100;
12'd1904 : mem_out_dec = 6'b001100;
12'd1905 : mem_out_dec = 6'b001100;
12'd1906 : mem_out_dec = 6'b001100;
12'd1907 : mem_out_dec = 6'b001101;
12'd1908 : mem_out_dec = 6'b001110;
12'd1909 : mem_out_dec = 6'b001110;
12'd1910 : mem_out_dec = 6'b001111;
12'd1911 : mem_out_dec = 6'b001111;
12'd1912 : mem_out_dec = 6'b001111;
12'd1913 : mem_out_dec = 6'b001111;
12'd1914 : mem_out_dec = 6'b001111;
12'd1915 : mem_out_dec = 6'b010000;
12'd1916 : mem_out_dec = 6'b010000;
12'd1917 : mem_out_dec = 6'b010001;
12'd1918 : mem_out_dec = 6'b010001;
12'd1919 : mem_out_dec = 6'b010010;
12'd1920 : mem_out_dec = 6'b111111;
12'd1921 : mem_out_dec = 6'b111111;
12'd1922 : mem_out_dec = 6'b111111;
12'd1923 : mem_out_dec = 6'b111111;
12'd1924 : mem_out_dec = 6'b111111;
12'd1925 : mem_out_dec = 6'b111111;
12'd1926 : mem_out_dec = 6'b111111;
12'd1927 : mem_out_dec = 6'b111111;
12'd1928 : mem_out_dec = 6'b111111;
12'd1929 : mem_out_dec = 6'b111111;
12'd1930 : mem_out_dec = 6'b111111;
12'd1931 : mem_out_dec = 6'b111111;
12'd1932 : mem_out_dec = 6'b111111;
12'd1933 : mem_out_dec = 6'b111111;
12'd1934 : mem_out_dec = 6'b111111;
12'd1935 : mem_out_dec = 6'b111111;
12'd1936 : mem_out_dec = 6'b111111;
12'd1937 : mem_out_dec = 6'b111111;
12'd1938 : mem_out_dec = 6'b111111;
12'd1939 : mem_out_dec = 6'b111111;
12'd1940 : mem_out_dec = 6'b111111;
12'd1941 : mem_out_dec = 6'b111111;
12'd1942 : mem_out_dec = 6'b111111;
12'd1943 : mem_out_dec = 6'b111111;
12'd1944 : mem_out_dec = 6'b111111;
12'd1945 : mem_out_dec = 6'b111111;
12'd1946 : mem_out_dec = 6'b111111;
12'd1947 : mem_out_dec = 6'b111111;
12'd1948 : mem_out_dec = 6'b111111;
12'd1949 : mem_out_dec = 6'b111111;
12'd1950 : mem_out_dec = 6'b111111;
12'd1951 : mem_out_dec = 6'b111111;
12'd1952 : mem_out_dec = 6'b111111;
12'd1953 : mem_out_dec = 6'b111111;
12'd1954 : mem_out_dec = 6'b111111;
12'd1955 : mem_out_dec = 6'b111111;
12'd1956 : mem_out_dec = 6'b000100;
12'd1957 : mem_out_dec = 6'b000101;
12'd1958 : mem_out_dec = 6'b000101;
12'd1959 : mem_out_dec = 6'b000110;
12'd1960 : mem_out_dec = 6'b000110;
12'd1961 : mem_out_dec = 6'b000111;
12'd1962 : mem_out_dec = 6'b001000;
12'd1963 : mem_out_dec = 6'b001000;
12'd1964 : mem_out_dec = 6'b001001;
12'd1965 : mem_out_dec = 6'b001010;
12'd1966 : mem_out_dec = 6'b001011;
12'd1967 : mem_out_dec = 6'b001011;
12'd1968 : mem_out_dec = 6'b001011;
12'd1969 : mem_out_dec = 6'b001100;
12'd1970 : mem_out_dec = 6'b001100;
12'd1971 : mem_out_dec = 6'b001101;
12'd1972 : mem_out_dec = 6'b001101;
12'd1973 : mem_out_dec = 6'b001110;
12'd1974 : mem_out_dec = 6'b001111;
12'd1975 : mem_out_dec = 6'b001111;
12'd1976 : mem_out_dec = 6'b001110;
12'd1977 : mem_out_dec = 6'b001110;
12'd1978 : mem_out_dec = 6'b001111;
12'd1979 : mem_out_dec = 6'b001111;
12'd1980 : mem_out_dec = 6'b010000;
12'd1981 : mem_out_dec = 6'b010000;
12'd1982 : mem_out_dec = 6'b010001;
12'd1983 : mem_out_dec = 6'b010001;
12'd1984 : mem_out_dec = 6'b111111;
12'd1985 : mem_out_dec = 6'b111111;
12'd1986 : mem_out_dec = 6'b111111;
12'd1987 : mem_out_dec = 6'b111111;
12'd1988 : mem_out_dec = 6'b111111;
12'd1989 : mem_out_dec = 6'b111111;
12'd1990 : mem_out_dec = 6'b111111;
12'd1991 : mem_out_dec = 6'b111111;
12'd1992 : mem_out_dec = 6'b111111;
12'd1993 : mem_out_dec = 6'b111111;
12'd1994 : mem_out_dec = 6'b111111;
12'd1995 : mem_out_dec = 6'b111111;
12'd1996 : mem_out_dec = 6'b111111;
12'd1997 : mem_out_dec = 6'b111111;
12'd1998 : mem_out_dec = 6'b111111;
12'd1999 : mem_out_dec = 6'b111111;
12'd2000 : mem_out_dec = 6'b111111;
12'd2001 : mem_out_dec = 6'b111111;
12'd2002 : mem_out_dec = 6'b111111;
12'd2003 : mem_out_dec = 6'b111111;
12'd2004 : mem_out_dec = 6'b111111;
12'd2005 : mem_out_dec = 6'b111111;
12'd2006 : mem_out_dec = 6'b111111;
12'd2007 : mem_out_dec = 6'b111111;
12'd2008 : mem_out_dec = 6'b111111;
12'd2009 : mem_out_dec = 6'b111111;
12'd2010 : mem_out_dec = 6'b111111;
12'd2011 : mem_out_dec = 6'b111111;
12'd2012 : mem_out_dec = 6'b111111;
12'd2013 : mem_out_dec = 6'b111111;
12'd2014 : mem_out_dec = 6'b111111;
12'd2015 : mem_out_dec = 6'b111111;
12'd2016 : mem_out_dec = 6'b111111;
12'd2017 : mem_out_dec = 6'b111111;
12'd2018 : mem_out_dec = 6'b111111;
12'd2019 : mem_out_dec = 6'b111111;
12'd2020 : mem_out_dec = 6'b111111;
12'd2021 : mem_out_dec = 6'b000100;
12'd2022 : mem_out_dec = 6'b000101;
12'd2023 : mem_out_dec = 6'b000110;
12'd2024 : mem_out_dec = 6'b000110;
12'd2025 : mem_out_dec = 6'b000111;
12'd2026 : mem_out_dec = 6'b000111;
12'd2027 : mem_out_dec = 6'b001000;
12'd2028 : mem_out_dec = 6'b001001;
12'd2029 : mem_out_dec = 6'b001010;
12'd2030 : mem_out_dec = 6'b001010;
12'd2031 : mem_out_dec = 6'b001011;
12'd2032 : mem_out_dec = 6'b001011;
12'd2033 : mem_out_dec = 6'b001011;
12'd2034 : mem_out_dec = 6'b001100;
12'd2035 : mem_out_dec = 6'b001101;
12'd2036 : mem_out_dec = 6'b001101;
12'd2037 : mem_out_dec = 6'b001110;
12'd2038 : mem_out_dec = 6'b001110;
12'd2039 : mem_out_dec = 6'b001110;
12'd2040 : mem_out_dec = 6'b001101;
12'd2041 : mem_out_dec = 6'b001110;
12'd2042 : mem_out_dec = 6'b001110;
12'd2043 : mem_out_dec = 6'b001111;
12'd2044 : mem_out_dec = 6'b001111;
12'd2045 : mem_out_dec = 6'b010000;
12'd2046 : mem_out_dec = 6'b010000;
12'd2047 : mem_out_dec = 6'b010001;
12'd2048 : mem_out_dec = 6'b111111;
12'd2049 : mem_out_dec = 6'b111111;
12'd2050 : mem_out_dec = 6'b111111;
12'd2051 : mem_out_dec = 6'b111111;
12'd2052 : mem_out_dec = 6'b111111;
12'd2053 : mem_out_dec = 6'b111111;
12'd2054 : mem_out_dec = 6'b111111;
12'd2055 : mem_out_dec = 6'b111111;
12'd2056 : mem_out_dec = 6'b111111;
12'd2057 : mem_out_dec = 6'b111111;
12'd2058 : mem_out_dec = 6'b111111;
12'd2059 : mem_out_dec = 6'b111111;
12'd2060 : mem_out_dec = 6'b111111;
12'd2061 : mem_out_dec = 6'b111111;
12'd2062 : mem_out_dec = 6'b111111;
12'd2063 : mem_out_dec = 6'b111111;
12'd2064 : mem_out_dec = 6'b111111;
12'd2065 : mem_out_dec = 6'b111111;
12'd2066 : mem_out_dec = 6'b111111;
12'd2067 : mem_out_dec = 6'b111111;
12'd2068 : mem_out_dec = 6'b111111;
12'd2069 : mem_out_dec = 6'b111111;
12'd2070 : mem_out_dec = 6'b111111;
12'd2071 : mem_out_dec = 6'b111111;
12'd2072 : mem_out_dec = 6'b111111;
12'd2073 : mem_out_dec = 6'b111111;
12'd2074 : mem_out_dec = 6'b111111;
12'd2075 : mem_out_dec = 6'b111111;
12'd2076 : mem_out_dec = 6'b111111;
12'd2077 : mem_out_dec = 6'b111111;
12'd2078 : mem_out_dec = 6'b111111;
12'd2079 : mem_out_dec = 6'b111111;
12'd2080 : mem_out_dec = 6'b111111;
12'd2081 : mem_out_dec = 6'b111111;
12'd2082 : mem_out_dec = 6'b111111;
12'd2083 : mem_out_dec = 6'b111111;
12'd2084 : mem_out_dec = 6'b111111;
12'd2085 : mem_out_dec = 6'b111111;
12'd2086 : mem_out_dec = 6'b000100;
12'd2087 : mem_out_dec = 6'b000101;
12'd2088 : mem_out_dec = 6'b000101;
12'd2089 : mem_out_dec = 6'b000110;
12'd2090 : mem_out_dec = 6'b000110;
12'd2091 : mem_out_dec = 6'b000111;
12'd2092 : mem_out_dec = 6'b001000;
12'd2093 : mem_out_dec = 6'b001001;
12'd2094 : mem_out_dec = 6'b001001;
12'd2095 : mem_out_dec = 6'b001010;
12'd2096 : mem_out_dec = 6'b001010;
12'd2097 : mem_out_dec = 6'b001011;
12'd2098 : mem_out_dec = 6'b001011;
12'd2099 : mem_out_dec = 6'b001100;
12'd2100 : mem_out_dec = 6'b001100;
12'd2101 : mem_out_dec = 6'b001100;
12'd2102 : mem_out_dec = 6'b001100;
12'd2103 : mem_out_dec = 6'b001101;
12'd2104 : mem_out_dec = 6'b001100;
12'd2105 : mem_out_dec = 6'b001100;
12'd2106 : mem_out_dec = 6'b001101;
12'd2107 : mem_out_dec = 6'b001101;
12'd2108 : mem_out_dec = 6'b001110;
12'd2109 : mem_out_dec = 6'b001111;
12'd2110 : mem_out_dec = 6'b010000;
12'd2111 : mem_out_dec = 6'b010000;
12'd2112 : mem_out_dec = 6'b111111;
12'd2113 : mem_out_dec = 6'b111111;
12'd2114 : mem_out_dec = 6'b111111;
12'd2115 : mem_out_dec = 6'b111111;
12'd2116 : mem_out_dec = 6'b111111;
12'd2117 : mem_out_dec = 6'b111111;
12'd2118 : mem_out_dec = 6'b111111;
12'd2119 : mem_out_dec = 6'b111111;
12'd2120 : mem_out_dec = 6'b111111;
12'd2121 : mem_out_dec = 6'b111111;
12'd2122 : mem_out_dec = 6'b111111;
12'd2123 : mem_out_dec = 6'b111111;
12'd2124 : mem_out_dec = 6'b111111;
12'd2125 : mem_out_dec = 6'b111111;
12'd2126 : mem_out_dec = 6'b111111;
12'd2127 : mem_out_dec = 6'b111111;
12'd2128 : mem_out_dec = 6'b111111;
12'd2129 : mem_out_dec = 6'b111111;
12'd2130 : mem_out_dec = 6'b111111;
12'd2131 : mem_out_dec = 6'b111111;
12'd2132 : mem_out_dec = 6'b111111;
12'd2133 : mem_out_dec = 6'b111111;
12'd2134 : mem_out_dec = 6'b111111;
12'd2135 : mem_out_dec = 6'b111111;
12'd2136 : mem_out_dec = 6'b111111;
12'd2137 : mem_out_dec = 6'b111111;
12'd2138 : mem_out_dec = 6'b111111;
12'd2139 : mem_out_dec = 6'b111111;
12'd2140 : mem_out_dec = 6'b111111;
12'd2141 : mem_out_dec = 6'b111111;
12'd2142 : mem_out_dec = 6'b111111;
12'd2143 : mem_out_dec = 6'b111111;
12'd2144 : mem_out_dec = 6'b111111;
12'd2145 : mem_out_dec = 6'b111111;
12'd2146 : mem_out_dec = 6'b111111;
12'd2147 : mem_out_dec = 6'b111111;
12'd2148 : mem_out_dec = 6'b111111;
12'd2149 : mem_out_dec = 6'b111111;
12'd2150 : mem_out_dec = 6'b111111;
12'd2151 : mem_out_dec = 6'b000100;
12'd2152 : mem_out_dec = 6'b000100;
12'd2153 : mem_out_dec = 6'b000101;
12'd2154 : mem_out_dec = 6'b000110;
12'd2155 : mem_out_dec = 6'b000111;
12'd2156 : mem_out_dec = 6'b000111;
12'd2157 : mem_out_dec = 6'b001000;
12'd2158 : mem_out_dec = 6'b001001;
12'd2159 : mem_out_dec = 6'b001001;
12'd2160 : mem_out_dec = 6'b001010;
12'd2161 : mem_out_dec = 6'b001010;
12'd2162 : mem_out_dec = 6'b001011;
12'd2163 : mem_out_dec = 6'b001011;
12'd2164 : mem_out_dec = 6'b001011;
12'd2165 : mem_out_dec = 6'b001011;
12'd2166 : mem_out_dec = 6'b001011;
12'd2167 : mem_out_dec = 6'b001100;
12'd2168 : mem_out_dec = 6'b001011;
12'd2169 : mem_out_dec = 6'b001011;
12'd2170 : mem_out_dec = 6'b001100;
12'd2171 : mem_out_dec = 6'b001101;
12'd2172 : mem_out_dec = 6'b001110;
12'd2173 : mem_out_dec = 6'b001110;
12'd2174 : mem_out_dec = 6'b001111;
12'd2175 : mem_out_dec = 6'b010000;
12'd2176 : mem_out_dec = 6'b111111;
12'd2177 : mem_out_dec = 6'b111111;
12'd2178 : mem_out_dec = 6'b111111;
12'd2179 : mem_out_dec = 6'b111111;
12'd2180 : mem_out_dec = 6'b111111;
12'd2181 : mem_out_dec = 6'b111111;
12'd2182 : mem_out_dec = 6'b111111;
12'd2183 : mem_out_dec = 6'b111111;
12'd2184 : mem_out_dec = 6'b111111;
12'd2185 : mem_out_dec = 6'b111111;
12'd2186 : mem_out_dec = 6'b111111;
12'd2187 : mem_out_dec = 6'b111111;
12'd2188 : mem_out_dec = 6'b111111;
12'd2189 : mem_out_dec = 6'b111111;
12'd2190 : mem_out_dec = 6'b111111;
12'd2191 : mem_out_dec = 6'b111111;
12'd2192 : mem_out_dec = 6'b111111;
12'd2193 : mem_out_dec = 6'b111111;
12'd2194 : mem_out_dec = 6'b111111;
12'd2195 : mem_out_dec = 6'b111111;
12'd2196 : mem_out_dec = 6'b111111;
12'd2197 : mem_out_dec = 6'b111111;
12'd2198 : mem_out_dec = 6'b111111;
12'd2199 : mem_out_dec = 6'b111111;
12'd2200 : mem_out_dec = 6'b111111;
12'd2201 : mem_out_dec = 6'b111111;
12'd2202 : mem_out_dec = 6'b111111;
12'd2203 : mem_out_dec = 6'b111111;
12'd2204 : mem_out_dec = 6'b111111;
12'd2205 : mem_out_dec = 6'b111111;
12'd2206 : mem_out_dec = 6'b111111;
12'd2207 : mem_out_dec = 6'b111111;
12'd2208 : mem_out_dec = 6'b111111;
12'd2209 : mem_out_dec = 6'b111111;
12'd2210 : mem_out_dec = 6'b111111;
12'd2211 : mem_out_dec = 6'b111111;
12'd2212 : mem_out_dec = 6'b111111;
12'd2213 : mem_out_dec = 6'b111111;
12'd2214 : mem_out_dec = 6'b111111;
12'd2215 : mem_out_dec = 6'b111111;
12'd2216 : mem_out_dec = 6'b000100;
12'd2217 : mem_out_dec = 6'b000101;
12'd2218 : mem_out_dec = 6'b000101;
12'd2219 : mem_out_dec = 6'b000110;
12'd2220 : mem_out_dec = 6'b000111;
12'd2221 : mem_out_dec = 6'b000111;
12'd2222 : mem_out_dec = 6'b001000;
12'd2223 : mem_out_dec = 6'b001001;
12'd2224 : mem_out_dec = 6'b001001;
12'd2225 : mem_out_dec = 6'b001010;
12'd2226 : mem_out_dec = 6'b001010;
12'd2227 : mem_out_dec = 6'b001010;
12'd2228 : mem_out_dec = 6'b001010;
12'd2229 : mem_out_dec = 6'b001010;
12'd2230 : mem_out_dec = 6'b001010;
12'd2231 : mem_out_dec = 6'b001010;
12'd2232 : mem_out_dec = 6'b001010;
12'd2233 : mem_out_dec = 6'b001011;
12'd2234 : mem_out_dec = 6'b001100;
12'd2235 : mem_out_dec = 6'b001100;
12'd2236 : mem_out_dec = 6'b001101;
12'd2237 : mem_out_dec = 6'b001110;
12'd2238 : mem_out_dec = 6'b001111;
12'd2239 : mem_out_dec = 6'b010000;
12'd2240 : mem_out_dec = 6'b111111;
12'd2241 : mem_out_dec = 6'b111111;
12'd2242 : mem_out_dec = 6'b111111;
12'd2243 : mem_out_dec = 6'b111111;
12'd2244 : mem_out_dec = 6'b111111;
12'd2245 : mem_out_dec = 6'b111111;
12'd2246 : mem_out_dec = 6'b111111;
12'd2247 : mem_out_dec = 6'b111111;
12'd2248 : mem_out_dec = 6'b111111;
12'd2249 : mem_out_dec = 6'b111111;
12'd2250 : mem_out_dec = 6'b111111;
12'd2251 : mem_out_dec = 6'b111111;
12'd2252 : mem_out_dec = 6'b111111;
12'd2253 : mem_out_dec = 6'b111111;
12'd2254 : mem_out_dec = 6'b111111;
12'd2255 : mem_out_dec = 6'b111111;
12'd2256 : mem_out_dec = 6'b111111;
12'd2257 : mem_out_dec = 6'b111111;
12'd2258 : mem_out_dec = 6'b111111;
12'd2259 : mem_out_dec = 6'b111111;
12'd2260 : mem_out_dec = 6'b111111;
12'd2261 : mem_out_dec = 6'b111111;
12'd2262 : mem_out_dec = 6'b111111;
12'd2263 : mem_out_dec = 6'b111111;
12'd2264 : mem_out_dec = 6'b111111;
12'd2265 : mem_out_dec = 6'b111111;
12'd2266 : mem_out_dec = 6'b111111;
12'd2267 : mem_out_dec = 6'b111111;
12'd2268 : mem_out_dec = 6'b111111;
12'd2269 : mem_out_dec = 6'b111111;
12'd2270 : mem_out_dec = 6'b111111;
12'd2271 : mem_out_dec = 6'b111111;
12'd2272 : mem_out_dec = 6'b111111;
12'd2273 : mem_out_dec = 6'b111111;
12'd2274 : mem_out_dec = 6'b111111;
12'd2275 : mem_out_dec = 6'b111111;
12'd2276 : mem_out_dec = 6'b111111;
12'd2277 : mem_out_dec = 6'b111111;
12'd2278 : mem_out_dec = 6'b111111;
12'd2279 : mem_out_dec = 6'b111111;
12'd2280 : mem_out_dec = 6'b111111;
12'd2281 : mem_out_dec = 6'b000100;
12'd2282 : mem_out_dec = 6'b000101;
12'd2283 : mem_out_dec = 6'b000101;
12'd2284 : mem_out_dec = 6'b000110;
12'd2285 : mem_out_dec = 6'b000111;
12'd2286 : mem_out_dec = 6'b001000;
12'd2287 : mem_out_dec = 6'b001001;
12'd2288 : mem_out_dec = 6'b001001;
12'd2289 : mem_out_dec = 6'b001001;
12'd2290 : mem_out_dec = 6'b001001;
12'd2291 : mem_out_dec = 6'b001001;
12'd2292 : mem_out_dec = 6'b001001;
12'd2293 : mem_out_dec = 6'b001001;
12'd2294 : mem_out_dec = 6'b001001;
12'd2295 : mem_out_dec = 6'b001001;
12'd2296 : mem_out_dec = 6'b001010;
12'd2297 : mem_out_dec = 6'b001010;
12'd2298 : mem_out_dec = 6'b001011;
12'd2299 : mem_out_dec = 6'b001100;
12'd2300 : mem_out_dec = 6'b001101;
12'd2301 : mem_out_dec = 6'b001110;
12'd2302 : mem_out_dec = 6'b001110;
12'd2303 : mem_out_dec = 6'b001111;
12'd2304 : mem_out_dec = 6'b111111;
12'd2305 : mem_out_dec = 6'b111111;
12'd2306 : mem_out_dec = 6'b111111;
12'd2307 : mem_out_dec = 6'b111111;
12'd2308 : mem_out_dec = 6'b111111;
12'd2309 : mem_out_dec = 6'b111111;
12'd2310 : mem_out_dec = 6'b111111;
12'd2311 : mem_out_dec = 6'b111111;
12'd2312 : mem_out_dec = 6'b111111;
12'd2313 : mem_out_dec = 6'b111111;
12'd2314 : mem_out_dec = 6'b111111;
12'd2315 : mem_out_dec = 6'b111111;
12'd2316 : mem_out_dec = 6'b111111;
12'd2317 : mem_out_dec = 6'b111111;
12'd2318 : mem_out_dec = 6'b111111;
12'd2319 : mem_out_dec = 6'b111111;
12'd2320 : mem_out_dec = 6'b111111;
12'd2321 : mem_out_dec = 6'b111111;
12'd2322 : mem_out_dec = 6'b111111;
12'd2323 : mem_out_dec = 6'b111111;
12'd2324 : mem_out_dec = 6'b111111;
12'd2325 : mem_out_dec = 6'b111111;
12'd2326 : mem_out_dec = 6'b111111;
12'd2327 : mem_out_dec = 6'b111111;
12'd2328 : mem_out_dec = 6'b111111;
12'd2329 : mem_out_dec = 6'b111111;
12'd2330 : mem_out_dec = 6'b111111;
12'd2331 : mem_out_dec = 6'b111111;
12'd2332 : mem_out_dec = 6'b111111;
12'd2333 : mem_out_dec = 6'b111111;
12'd2334 : mem_out_dec = 6'b111111;
12'd2335 : mem_out_dec = 6'b111111;
12'd2336 : mem_out_dec = 6'b111111;
12'd2337 : mem_out_dec = 6'b111111;
12'd2338 : mem_out_dec = 6'b111111;
12'd2339 : mem_out_dec = 6'b111111;
12'd2340 : mem_out_dec = 6'b111111;
12'd2341 : mem_out_dec = 6'b111111;
12'd2342 : mem_out_dec = 6'b111111;
12'd2343 : mem_out_dec = 6'b111111;
12'd2344 : mem_out_dec = 6'b111111;
12'd2345 : mem_out_dec = 6'b111111;
12'd2346 : mem_out_dec = 6'b000100;
12'd2347 : mem_out_dec = 6'b000101;
12'd2348 : mem_out_dec = 6'b000110;
12'd2349 : mem_out_dec = 6'b000111;
12'd2350 : mem_out_dec = 6'b000111;
12'd2351 : mem_out_dec = 6'b001000;
12'd2352 : mem_out_dec = 6'b001000;
12'd2353 : mem_out_dec = 6'b001000;
12'd2354 : mem_out_dec = 6'b001000;
12'd2355 : mem_out_dec = 6'b001000;
12'd2356 : mem_out_dec = 6'b001000;
12'd2357 : mem_out_dec = 6'b001000;
12'd2358 : mem_out_dec = 6'b001000;
12'd2359 : mem_out_dec = 6'b001001;
12'd2360 : mem_out_dec = 6'b001001;
12'd2361 : mem_out_dec = 6'b001010;
12'd2362 : mem_out_dec = 6'b001011;
12'd2363 : mem_out_dec = 6'b001100;
12'd2364 : mem_out_dec = 6'b001100;
12'd2365 : mem_out_dec = 6'b001101;
12'd2366 : mem_out_dec = 6'b001110;
12'd2367 : mem_out_dec = 6'b001111;
12'd2368 : mem_out_dec = 6'b111111;
12'd2369 : mem_out_dec = 6'b111111;
12'd2370 : mem_out_dec = 6'b111111;
12'd2371 : mem_out_dec = 6'b111111;
12'd2372 : mem_out_dec = 6'b111111;
12'd2373 : mem_out_dec = 6'b111111;
12'd2374 : mem_out_dec = 6'b111111;
12'd2375 : mem_out_dec = 6'b111111;
12'd2376 : mem_out_dec = 6'b111111;
12'd2377 : mem_out_dec = 6'b111111;
12'd2378 : mem_out_dec = 6'b111111;
12'd2379 : mem_out_dec = 6'b111111;
12'd2380 : mem_out_dec = 6'b111111;
12'd2381 : mem_out_dec = 6'b111111;
12'd2382 : mem_out_dec = 6'b111111;
12'd2383 : mem_out_dec = 6'b111111;
12'd2384 : mem_out_dec = 6'b111111;
12'd2385 : mem_out_dec = 6'b111111;
12'd2386 : mem_out_dec = 6'b111111;
12'd2387 : mem_out_dec = 6'b111111;
12'd2388 : mem_out_dec = 6'b111111;
12'd2389 : mem_out_dec = 6'b111111;
12'd2390 : mem_out_dec = 6'b111111;
12'd2391 : mem_out_dec = 6'b111111;
12'd2392 : mem_out_dec = 6'b111111;
12'd2393 : mem_out_dec = 6'b111111;
12'd2394 : mem_out_dec = 6'b111111;
12'd2395 : mem_out_dec = 6'b111111;
12'd2396 : mem_out_dec = 6'b111111;
12'd2397 : mem_out_dec = 6'b111111;
12'd2398 : mem_out_dec = 6'b111111;
12'd2399 : mem_out_dec = 6'b111111;
12'd2400 : mem_out_dec = 6'b111111;
12'd2401 : mem_out_dec = 6'b111111;
12'd2402 : mem_out_dec = 6'b111111;
12'd2403 : mem_out_dec = 6'b111111;
12'd2404 : mem_out_dec = 6'b111111;
12'd2405 : mem_out_dec = 6'b111111;
12'd2406 : mem_out_dec = 6'b111111;
12'd2407 : mem_out_dec = 6'b111111;
12'd2408 : mem_out_dec = 6'b111111;
12'd2409 : mem_out_dec = 6'b111111;
12'd2410 : mem_out_dec = 6'b111111;
12'd2411 : mem_out_dec = 6'b000101;
12'd2412 : mem_out_dec = 6'b000101;
12'd2413 : mem_out_dec = 6'b000110;
12'd2414 : mem_out_dec = 6'b000111;
12'd2415 : mem_out_dec = 6'b001000;
12'd2416 : mem_out_dec = 6'b000111;
12'd2417 : mem_out_dec = 6'b000111;
12'd2418 : mem_out_dec = 6'b000111;
12'd2419 : mem_out_dec = 6'b000111;
12'd2420 : mem_out_dec = 6'b000111;
12'd2421 : mem_out_dec = 6'b000111;
12'd2422 : mem_out_dec = 6'b001000;
12'd2423 : mem_out_dec = 6'b001001;
12'd2424 : mem_out_dec = 6'b001001;
12'd2425 : mem_out_dec = 6'b001010;
12'd2426 : mem_out_dec = 6'b001010;
12'd2427 : mem_out_dec = 6'b001011;
12'd2428 : mem_out_dec = 6'b001100;
12'd2429 : mem_out_dec = 6'b001101;
12'd2430 : mem_out_dec = 6'b001101;
12'd2431 : mem_out_dec = 6'b001110;
12'd2432 : mem_out_dec = 6'b111111;
12'd2433 : mem_out_dec = 6'b111111;
12'd2434 : mem_out_dec = 6'b111111;
12'd2435 : mem_out_dec = 6'b111111;
12'd2436 : mem_out_dec = 6'b111111;
12'd2437 : mem_out_dec = 6'b111111;
12'd2438 : mem_out_dec = 6'b111111;
12'd2439 : mem_out_dec = 6'b111111;
12'd2440 : mem_out_dec = 6'b111111;
12'd2441 : mem_out_dec = 6'b111111;
12'd2442 : mem_out_dec = 6'b111111;
12'd2443 : mem_out_dec = 6'b111111;
12'd2444 : mem_out_dec = 6'b111111;
12'd2445 : mem_out_dec = 6'b111111;
12'd2446 : mem_out_dec = 6'b111111;
12'd2447 : mem_out_dec = 6'b111111;
12'd2448 : mem_out_dec = 6'b111111;
12'd2449 : mem_out_dec = 6'b111111;
12'd2450 : mem_out_dec = 6'b111111;
12'd2451 : mem_out_dec = 6'b111111;
12'd2452 : mem_out_dec = 6'b111111;
12'd2453 : mem_out_dec = 6'b111111;
12'd2454 : mem_out_dec = 6'b111111;
12'd2455 : mem_out_dec = 6'b111111;
12'd2456 : mem_out_dec = 6'b111111;
12'd2457 : mem_out_dec = 6'b111111;
12'd2458 : mem_out_dec = 6'b111111;
12'd2459 : mem_out_dec = 6'b111111;
12'd2460 : mem_out_dec = 6'b111111;
12'd2461 : mem_out_dec = 6'b111111;
12'd2462 : mem_out_dec = 6'b111111;
12'd2463 : mem_out_dec = 6'b111111;
12'd2464 : mem_out_dec = 6'b111111;
12'd2465 : mem_out_dec = 6'b111111;
12'd2466 : mem_out_dec = 6'b111111;
12'd2467 : mem_out_dec = 6'b111111;
12'd2468 : mem_out_dec = 6'b111111;
12'd2469 : mem_out_dec = 6'b111111;
12'd2470 : mem_out_dec = 6'b111111;
12'd2471 : mem_out_dec = 6'b111111;
12'd2472 : mem_out_dec = 6'b111111;
12'd2473 : mem_out_dec = 6'b111111;
12'd2474 : mem_out_dec = 6'b111111;
12'd2475 : mem_out_dec = 6'b111111;
12'd2476 : mem_out_dec = 6'b000101;
12'd2477 : mem_out_dec = 6'b000110;
12'd2478 : mem_out_dec = 6'b000111;
12'd2479 : mem_out_dec = 6'b000111;
12'd2480 : mem_out_dec = 6'b000110;
12'd2481 : mem_out_dec = 6'b000110;
12'd2482 : mem_out_dec = 6'b000110;
12'd2483 : mem_out_dec = 6'b000110;
12'd2484 : mem_out_dec = 6'b000110;
12'd2485 : mem_out_dec = 6'b000111;
12'd2486 : mem_out_dec = 6'b000111;
12'd2487 : mem_out_dec = 6'b001000;
12'd2488 : mem_out_dec = 6'b001001;
12'd2489 : mem_out_dec = 6'b001001;
12'd2490 : mem_out_dec = 6'b001010;
12'd2491 : mem_out_dec = 6'b001011;
12'd2492 : mem_out_dec = 6'b001011;
12'd2493 : mem_out_dec = 6'b001100;
12'd2494 : mem_out_dec = 6'b001101;
12'd2495 : mem_out_dec = 6'b001110;
12'd2496 : mem_out_dec = 6'b111111;
12'd2497 : mem_out_dec = 6'b111111;
12'd2498 : mem_out_dec = 6'b111111;
12'd2499 : mem_out_dec = 6'b111111;
12'd2500 : mem_out_dec = 6'b111111;
12'd2501 : mem_out_dec = 6'b111111;
12'd2502 : mem_out_dec = 6'b111111;
12'd2503 : mem_out_dec = 6'b111111;
12'd2504 : mem_out_dec = 6'b111111;
12'd2505 : mem_out_dec = 6'b111111;
12'd2506 : mem_out_dec = 6'b111111;
12'd2507 : mem_out_dec = 6'b111111;
12'd2508 : mem_out_dec = 6'b111111;
12'd2509 : mem_out_dec = 6'b111111;
12'd2510 : mem_out_dec = 6'b111111;
12'd2511 : mem_out_dec = 6'b111111;
12'd2512 : mem_out_dec = 6'b111111;
12'd2513 : mem_out_dec = 6'b111111;
12'd2514 : mem_out_dec = 6'b111111;
12'd2515 : mem_out_dec = 6'b111111;
12'd2516 : mem_out_dec = 6'b111111;
12'd2517 : mem_out_dec = 6'b111111;
12'd2518 : mem_out_dec = 6'b111111;
12'd2519 : mem_out_dec = 6'b111111;
12'd2520 : mem_out_dec = 6'b111111;
12'd2521 : mem_out_dec = 6'b111111;
12'd2522 : mem_out_dec = 6'b111111;
12'd2523 : mem_out_dec = 6'b111111;
12'd2524 : mem_out_dec = 6'b111111;
12'd2525 : mem_out_dec = 6'b111111;
12'd2526 : mem_out_dec = 6'b111111;
12'd2527 : mem_out_dec = 6'b111111;
12'd2528 : mem_out_dec = 6'b111111;
12'd2529 : mem_out_dec = 6'b111111;
12'd2530 : mem_out_dec = 6'b111111;
12'd2531 : mem_out_dec = 6'b111111;
12'd2532 : mem_out_dec = 6'b111111;
12'd2533 : mem_out_dec = 6'b111111;
12'd2534 : mem_out_dec = 6'b111111;
12'd2535 : mem_out_dec = 6'b111111;
12'd2536 : mem_out_dec = 6'b111111;
12'd2537 : mem_out_dec = 6'b111111;
12'd2538 : mem_out_dec = 6'b111111;
12'd2539 : mem_out_dec = 6'b111111;
12'd2540 : mem_out_dec = 6'b111111;
12'd2541 : mem_out_dec = 6'b000101;
12'd2542 : mem_out_dec = 6'b000110;
12'd2543 : mem_out_dec = 6'b000110;
12'd2544 : mem_out_dec = 6'b000110;
12'd2545 : mem_out_dec = 6'b000110;
12'd2546 : mem_out_dec = 6'b000101;
12'd2547 : mem_out_dec = 6'b000101;
12'd2548 : mem_out_dec = 6'b000110;
12'd2549 : mem_out_dec = 6'b000111;
12'd2550 : mem_out_dec = 6'b000111;
12'd2551 : mem_out_dec = 6'b001000;
12'd2552 : mem_out_dec = 6'b001000;
12'd2553 : mem_out_dec = 6'b001001;
12'd2554 : mem_out_dec = 6'b001010;
12'd2555 : mem_out_dec = 6'b001010;
12'd2556 : mem_out_dec = 6'b001011;
12'd2557 : mem_out_dec = 6'b001100;
12'd2558 : mem_out_dec = 6'b001101;
12'd2559 : mem_out_dec = 6'b001101;
12'd2560 : mem_out_dec = 6'b111111;
12'd2561 : mem_out_dec = 6'b111111;
12'd2562 : mem_out_dec = 6'b111111;
12'd2563 : mem_out_dec = 6'b111111;
12'd2564 : mem_out_dec = 6'b111111;
12'd2565 : mem_out_dec = 6'b111111;
12'd2566 : mem_out_dec = 6'b111111;
12'd2567 : mem_out_dec = 6'b111111;
12'd2568 : mem_out_dec = 6'b111111;
12'd2569 : mem_out_dec = 6'b111111;
12'd2570 : mem_out_dec = 6'b111111;
12'd2571 : mem_out_dec = 6'b111111;
12'd2572 : mem_out_dec = 6'b111111;
12'd2573 : mem_out_dec = 6'b111111;
12'd2574 : mem_out_dec = 6'b111111;
12'd2575 : mem_out_dec = 6'b111111;
12'd2576 : mem_out_dec = 6'b111111;
12'd2577 : mem_out_dec = 6'b111111;
12'd2578 : mem_out_dec = 6'b111111;
12'd2579 : mem_out_dec = 6'b111111;
12'd2580 : mem_out_dec = 6'b111111;
12'd2581 : mem_out_dec = 6'b111111;
12'd2582 : mem_out_dec = 6'b111111;
12'd2583 : mem_out_dec = 6'b111111;
12'd2584 : mem_out_dec = 6'b111111;
12'd2585 : mem_out_dec = 6'b111111;
12'd2586 : mem_out_dec = 6'b111111;
12'd2587 : mem_out_dec = 6'b111111;
12'd2588 : mem_out_dec = 6'b111111;
12'd2589 : mem_out_dec = 6'b111111;
12'd2590 : mem_out_dec = 6'b111111;
12'd2591 : mem_out_dec = 6'b111111;
12'd2592 : mem_out_dec = 6'b111111;
12'd2593 : mem_out_dec = 6'b111111;
12'd2594 : mem_out_dec = 6'b111111;
12'd2595 : mem_out_dec = 6'b111111;
12'd2596 : mem_out_dec = 6'b111111;
12'd2597 : mem_out_dec = 6'b111111;
12'd2598 : mem_out_dec = 6'b111111;
12'd2599 : mem_out_dec = 6'b111111;
12'd2600 : mem_out_dec = 6'b111111;
12'd2601 : mem_out_dec = 6'b111111;
12'd2602 : mem_out_dec = 6'b111111;
12'd2603 : mem_out_dec = 6'b111111;
12'd2604 : mem_out_dec = 6'b111111;
12'd2605 : mem_out_dec = 6'b111111;
12'd2606 : mem_out_dec = 6'b000100;
12'd2607 : mem_out_dec = 6'b000101;
12'd2608 : mem_out_dec = 6'b000100;
12'd2609 : mem_out_dec = 6'b000100;
12'd2610 : mem_out_dec = 6'b000100;
12'd2611 : mem_out_dec = 6'b000101;
12'd2612 : mem_out_dec = 6'b000101;
12'd2613 : mem_out_dec = 6'b000110;
12'd2614 : mem_out_dec = 6'b000111;
12'd2615 : mem_out_dec = 6'b000111;
12'd2616 : mem_out_dec = 6'b000111;
12'd2617 : mem_out_dec = 6'b001000;
12'd2618 : mem_out_dec = 6'b001001;
12'd2619 : mem_out_dec = 6'b001010;
12'd2620 : mem_out_dec = 6'b001010;
12'd2621 : mem_out_dec = 6'b001011;
12'd2622 : mem_out_dec = 6'b001100;
12'd2623 : mem_out_dec = 6'b001101;
12'd2624 : mem_out_dec = 6'b111111;
12'd2625 : mem_out_dec = 6'b111111;
12'd2626 : mem_out_dec = 6'b111111;
12'd2627 : mem_out_dec = 6'b111111;
12'd2628 : mem_out_dec = 6'b111111;
12'd2629 : mem_out_dec = 6'b111111;
12'd2630 : mem_out_dec = 6'b111111;
12'd2631 : mem_out_dec = 6'b111111;
12'd2632 : mem_out_dec = 6'b111111;
12'd2633 : mem_out_dec = 6'b111111;
12'd2634 : mem_out_dec = 6'b111111;
12'd2635 : mem_out_dec = 6'b111111;
12'd2636 : mem_out_dec = 6'b111111;
12'd2637 : mem_out_dec = 6'b111111;
12'd2638 : mem_out_dec = 6'b111111;
12'd2639 : mem_out_dec = 6'b111111;
12'd2640 : mem_out_dec = 6'b111111;
12'd2641 : mem_out_dec = 6'b111111;
12'd2642 : mem_out_dec = 6'b111111;
12'd2643 : mem_out_dec = 6'b111111;
12'd2644 : mem_out_dec = 6'b111111;
12'd2645 : mem_out_dec = 6'b111111;
12'd2646 : mem_out_dec = 6'b111111;
12'd2647 : mem_out_dec = 6'b111111;
12'd2648 : mem_out_dec = 6'b111111;
12'd2649 : mem_out_dec = 6'b111111;
12'd2650 : mem_out_dec = 6'b111111;
12'd2651 : mem_out_dec = 6'b111111;
12'd2652 : mem_out_dec = 6'b111111;
12'd2653 : mem_out_dec = 6'b111111;
12'd2654 : mem_out_dec = 6'b111111;
12'd2655 : mem_out_dec = 6'b111111;
12'd2656 : mem_out_dec = 6'b111111;
12'd2657 : mem_out_dec = 6'b111111;
12'd2658 : mem_out_dec = 6'b111111;
12'd2659 : mem_out_dec = 6'b111111;
12'd2660 : mem_out_dec = 6'b111111;
12'd2661 : mem_out_dec = 6'b111111;
12'd2662 : mem_out_dec = 6'b111111;
12'd2663 : mem_out_dec = 6'b111111;
12'd2664 : mem_out_dec = 6'b111111;
12'd2665 : mem_out_dec = 6'b111111;
12'd2666 : mem_out_dec = 6'b111111;
12'd2667 : mem_out_dec = 6'b111111;
12'd2668 : mem_out_dec = 6'b111111;
12'd2669 : mem_out_dec = 6'b111111;
12'd2670 : mem_out_dec = 6'b111111;
12'd2671 : mem_out_dec = 6'b000100;
12'd2672 : mem_out_dec = 6'b000011;
12'd2673 : mem_out_dec = 6'b000011;
12'd2674 : mem_out_dec = 6'b000100;
12'd2675 : mem_out_dec = 6'b000100;
12'd2676 : mem_out_dec = 6'b000101;
12'd2677 : mem_out_dec = 6'b000110;
12'd2678 : mem_out_dec = 6'b000110;
12'd2679 : mem_out_dec = 6'b000111;
12'd2680 : mem_out_dec = 6'b000111;
12'd2681 : mem_out_dec = 6'b001000;
12'd2682 : mem_out_dec = 6'b001001;
12'd2683 : mem_out_dec = 6'b001001;
12'd2684 : mem_out_dec = 6'b001010;
12'd2685 : mem_out_dec = 6'b001011;
12'd2686 : mem_out_dec = 6'b001100;
12'd2687 : mem_out_dec = 6'b001100;
12'd2688 : mem_out_dec = 6'b111111;
12'd2689 : mem_out_dec = 6'b111111;
12'd2690 : mem_out_dec = 6'b111111;
12'd2691 : mem_out_dec = 6'b111111;
12'd2692 : mem_out_dec = 6'b111111;
12'd2693 : mem_out_dec = 6'b111111;
12'd2694 : mem_out_dec = 6'b111111;
12'd2695 : mem_out_dec = 6'b111111;
12'd2696 : mem_out_dec = 6'b111111;
12'd2697 : mem_out_dec = 6'b111111;
12'd2698 : mem_out_dec = 6'b111111;
12'd2699 : mem_out_dec = 6'b111111;
12'd2700 : mem_out_dec = 6'b111111;
12'd2701 : mem_out_dec = 6'b111111;
12'd2702 : mem_out_dec = 6'b111111;
12'd2703 : mem_out_dec = 6'b111111;
12'd2704 : mem_out_dec = 6'b111111;
12'd2705 : mem_out_dec = 6'b111111;
12'd2706 : mem_out_dec = 6'b111111;
12'd2707 : mem_out_dec = 6'b111111;
12'd2708 : mem_out_dec = 6'b111111;
12'd2709 : mem_out_dec = 6'b111111;
12'd2710 : mem_out_dec = 6'b111111;
12'd2711 : mem_out_dec = 6'b111111;
12'd2712 : mem_out_dec = 6'b111111;
12'd2713 : mem_out_dec = 6'b111111;
12'd2714 : mem_out_dec = 6'b111111;
12'd2715 : mem_out_dec = 6'b111111;
12'd2716 : mem_out_dec = 6'b111111;
12'd2717 : mem_out_dec = 6'b111111;
12'd2718 : mem_out_dec = 6'b111111;
12'd2719 : mem_out_dec = 6'b111111;
12'd2720 : mem_out_dec = 6'b111111;
12'd2721 : mem_out_dec = 6'b111111;
12'd2722 : mem_out_dec = 6'b111111;
12'd2723 : mem_out_dec = 6'b111111;
12'd2724 : mem_out_dec = 6'b111111;
12'd2725 : mem_out_dec = 6'b111111;
12'd2726 : mem_out_dec = 6'b111111;
12'd2727 : mem_out_dec = 6'b111111;
12'd2728 : mem_out_dec = 6'b111111;
12'd2729 : mem_out_dec = 6'b111111;
12'd2730 : mem_out_dec = 6'b111111;
12'd2731 : mem_out_dec = 6'b111111;
12'd2732 : mem_out_dec = 6'b111111;
12'd2733 : mem_out_dec = 6'b111111;
12'd2734 : mem_out_dec = 6'b111111;
12'd2735 : mem_out_dec = 6'b111111;
12'd2736 : mem_out_dec = 6'b000011;
12'd2737 : mem_out_dec = 6'b000011;
12'd2738 : mem_out_dec = 6'b000100;
12'd2739 : mem_out_dec = 6'b000100;
12'd2740 : mem_out_dec = 6'b000101;
12'd2741 : mem_out_dec = 6'b000101;
12'd2742 : mem_out_dec = 6'b000110;
12'd2743 : mem_out_dec = 6'b000111;
12'd2744 : mem_out_dec = 6'b000111;
12'd2745 : mem_out_dec = 6'b001000;
12'd2746 : mem_out_dec = 6'b001000;
12'd2747 : mem_out_dec = 6'b001001;
12'd2748 : mem_out_dec = 6'b001010;
12'd2749 : mem_out_dec = 6'b001011;
12'd2750 : mem_out_dec = 6'b001011;
12'd2751 : mem_out_dec = 6'b001100;
12'd2752 : mem_out_dec = 6'b111111;
12'd2753 : mem_out_dec = 6'b111111;
12'd2754 : mem_out_dec = 6'b111111;
12'd2755 : mem_out_dec = 6'b111111;
12'd2756 : mem_out_dec = 6'b111111;
12'd2757 : mem_out_dec = 6'b111111;
12'd2758 : mem_out_dec = 6'b111111;
12'd2759 : mem_out_dec = 6'b111111;
12'd2760 : mem_out_dec = 6'b111111;
12'd2761 : mem_out_dec = 6'b111111;
12'd2762 : mem_out_dec = 6'b111111;
12'd2763 : mem_out_dec = 6'b111111;
12'd2764 : mem_out_dec = 6'b111111;
12'd2765 : mem_out_dec = 6'b111111;
12'd2766 : mem_out_dec = 6'b111111;
12'd2767 : mem_out_dec = 6'b111111;
12'd2768 : mem_out_dec = 6'b111111;
12'd2769 : mem_out_dec = 6'b111111;
12'd2770 : mem_out_dec = 6'b111111;
12'd2771 : mem_out_dec = 6'b111111;
12'd2772 : mem_out_dec = 6'b111111;
12'd2773 : mem_out_dec = 6'b111111;
12'd2774 : mem_out_dec = 6'b111111;
12'd2775 : mem_out_dec = 6'b111111;
12'd2776 : mem_out_dec = 6'b111111;
12'd2777 : mem_out_dec = 6'b111111;
12'd2778 : mem_out_dec = 6'b111111;
12'd2779 : mem_out_dec = 6'b111111;
12'd2780 : mem_out_dec = 6'b111111;
12'd2781 : mem_out_dec = 6'b111111;
12'd2782 : mem_out_dec = 6'b111111;
12'd2783 : mem_out_dec = 6'b111111;
12'd2784 : mem_out_dec = 6'b111111;
12'd2785 : mem_out_dec = 6'b111111;
12'd2786 : mem_out_dec = 6'b111111;
12'd2787 : mem_out_dec = 6'b111111;
12'd2788 : mem_out_dec = 6'b111111;
12'd2789 : mem_out_dec = 6'b111111;
12'd2790 : mem_out_dec = 6'b111111;
12'd2791 : mem_out_dec = 6'b111111;
12'd2792 : mem_out_dec = 6'b111111;
12'd2793 : mem_out_dec = 6'b111111;
12'd2794 : mem_out_dec = 6'b111111;
12'd2795 : mem_out_dec = 6'b111111;
12'd2796 : mem_out_dec = 6'b111111;
12'd2797 : mem_out_dec = 6'b111111;
12'd2798 : mem_out_dec = 6'b111111;
12'd2799 : mem_out_dec = 6'b111111;
12'd2800 : mem_out_dec = 6'b111111;
12'd2801 : mem_out_dec = 6'b000011;
12'd2802 : mem_out_dec = 6'b000011;
12'd2803 : mem_out_dec = 6'b000100;
12'd2804 : mem_out_dec = 6'b000101;
12'd2805 : mem_out_dec = 6'b000101;
12'd2806 : mem_out_dec = 6'b000110;
12'd2807 : mem_out_dec = 6'b000111;
12'd2808 : mem_out_dec = 6'b000111;
12'd2809 : mem_out_dec = 6'b000111;
12'd2810 : mem_out_dec = 6'b001000;
12'd2811 : mem_out_dec = 6'b001001;
12'd2812 : mem_out_dec = 6'b001010;
12'd2813 : mem_out_dec = 6'b001010;
12'd2814 : mem_out_dec = 6'b001011;
12'd2815 : mem_out_dec = 6'b001100;
12'd2816 : mem_out_dec = 6'b111111;
12'd2817 : mem_out_dec = 6'b111111;
12'd2818 : mem_out_dec = 6'b111111;
12'd2819 : mem_out_dec = 6'b111111;
12'd2820 : mem_out_dec = 6'b111111;
12'd2821 : mem_out_dec = 6'b111111;
12'd2822 : mem_out_dec = 6'b111111;
12'd2823 : mem_out_dec = 6'b111111;
12'd2824 : mem_out_dec = 6'b111111;
12'd2825 : mem_out_dec = 6'b111111;
12'd2826 : mem_out_dec = 6'b111111;
12'd2827 : mem_out_dec = 6'b111111;
12'd2828 : mem_out_dec = 6'b111111;
12'd2829 : mem_out_dec = 6'b111111;
12'd2830 : mem_out_dec = 6'b111111;
12'd2831 : mem_out_dec = 6'b111111;
12'd2832 : mem_out_dec = 6'b111111;
12'd2833 : mem_out_dec = 6'b111111;
12'd2834 : mem_out_dec = 6'b111111;
12'd2835 : mem_out_dec = 6'b111111;
12'd2836 : mem_out_dec = 6'b111111;
12'd2837 : mem_out_dec = 6'b111111;
12'd2838 : mem_out_dec = 6'b111111;
12'd2839 : mem_out_dec = 6'b111111;
12'd2840 : mem_out_dec = 6'b111111;
12'd2841 : mem_out_dec = 6'b111111;
12'd2842 : mem_out_dec = 6'b111111;
12'd2843 : mem_out_dec = 6'b111111;
12'd2844 : mem_out_dec = 6'b111111;
12'd2845 : mem_out_dec = 6'b111111;
12'd2846 : mem_out_dec = 6'b111111;
12'd2847 : mem_out_dec = 6'b111111;
12'd2848 : mem_out_dec = 6'b111111;
12'd2849 : mem_out_dec = 6'b111111;
12'd2850 : mem_out_dec = 6'b111111;
12'd2851 : mem_out_dec = 6'b111111;
12'd2852 : mem_out_dec = 6'b111111;
12'd2853 : mem_out_dec = 6'b111111;
12'd2854 : mem_out_dec = 6'b111111;
12'd2855 : mem_out_dec = 6'b111111;
12'd2856 : mem_out_dec = 6'b111111;
12'd2857 : mem_out_dec = 6'b111111;
12'd2858 : mem_out_dec = 6'b111111;
12'd2859 : mem_out_dec = 6'b111111;
12'd2860 : mem_out_dec = 6'b111111;
12'd2861 : mem_out_dec = 6'b111111;
12'd2862 : mem_out_dec = 6'b111111;
12'd2863 : mem_out_dec = 6'b111111;
12'd2864 : mem_out_dec = 6'b111111;
12'd2865 : mem_out_dec = 6'b111111;
12'd2866 : mem_out_dec = 6'b000011;
12'd2867 : mem_out_dec = 6'b000100;
12'd2868 : mem_out_dec = 6'b000100;
12'd2869 : mem_out_dec = 6'b000101;
12'd2870 : mem_out_dec = 6'b000110;
12'd2871 : mem_out_dec = 6'b000110;
12'd2872 : mem_out_dec = 6'b000110;
12'd2873 : mem_out_dec = 6'b000111;
12'd2874 : mem_out_dec = 6'b001000;
12'd2875 : mem_out_dec = 6'b001001;
12'd2876 : mem_out_dec = 6'b001001;
12'd2877 : mem_out_dec = 6'b001010;
12'd2878 : mem_out_dec = 6'b001011;
12'd2879 : mem_out_dec = 6'b001100;
12'd2880 : mem_out_dec = 6'b111111;
12'd2881 : mem_out_dec = 6'b111111;
12'd2882 : mem_out_dec = 6'b111111;
12'd2883 : mem_out_dec = 6'b111111;
12'd2884 : mem_out_dec = 6'b111111;
12'd2885 : mem_out_dec = 6'b111111;
12'd2886 : mem_out_dec = 6'b111111;
12'd2887 : mem_out_dec = 6'b111111;
12'd2888 : mem_out_dec = 6'b111111;
12'd2889 : mem_out_dec = 6'b111111;
12'd2890 : mem_out_dec = 6'b111111;
12'd2891 : mem_out_dec = 6'b111111;
12'd2892 : mem_out_dec = 6'b111111;
12'd2893 : mem_out_dec = 6'b111111;
12'd2894 : mem_out_dec = 6'b111111;
12'd2895 : mem_out_dec = 6'b111111;
12'd2896 : mem_out_dec = 6'b111111;
12'd2897 : mem_out_dec = 6'b111111;
12'd2898 : mem_out_dec = 6'b111111;
12'd2899 : mem_out_dec = 6'b111111;
12'd2900 : mem_out_dec = 6'b111111;
12'd2901 : mem_out_dec = 6'b111111;
12'd2902 : mem_out_dec = 6'b111111;
12'd2903 : mem_out_dec = 6'b111111;
12'd2904 : mem_out_dec = 6'b111111;
12'd2905 : mem_out_dec = 6'b111111;
12'd2906 : mem_out_dec = 6'b111111;
12'd2907 : mem_out_dec = 6'b111111;
12'd2908 : mem_out_dec = 6'b111111;
12'd2909 : mem_out_dec = 6'b111111;
12'd2910 : mem_out_dec = 6'b111111;
12'd2911 : mem_out_dec = 6'b111111;
12'd2912 : mem_out_dec = 6'b111111;
12'd2913 : mem_out_dec = 6'b111111;
12'd2914 : mem_out_dec = 6'b111111;
12'd2915 : mem_out_dec = 6'b111111;
12'd2916 : mem_out_dec = 6'b111111;
12'd2917 : mem_out_dec = 6'b111111;
12'd2918 : mem_out_dec = 6'b111111;
12'd2919 : mem_out_dec = 6'b111111;
12'd2920 : mem_out_dec = 6'b111111;
12'd2921 : mem_out_dec = 6'b111111;
12'd2922 : mem_out_dec = 6'b111111;
12'd2923 : mem_out_dec = 6'b111111;
12'd2924 : mem_out_dec = 6'b111111;
12'd2925 : mem_out_dec = 6'b111111;
12'd2926 : mem_out_dec = 6'b111111;
12'd2927 : mem_out_dec = 6'b111111;
12'd2928 : mem_out_dec = 6'b111111;
12'd2929 : mem_out_dec = 6'b111111;
12'd2930 : mem_out_dec = 6'b111111;
12'd2931 : mem_out_dec = 6'b000100;
12'd2932 : mem_out_dec = 6'b000100;
12'd2933 : mem_out_dec = 6'b000101;
12'd2934 : mem_out_dec = 6'b000101;
12'd2935 : mem_out_dec = 6'b000110;
12'd2936 : mem_out_dec = 6'b000110;
12'd2937 : mem_out_dec = 6'b000111;
12'd2938 : mem_out_dec = 6'b001000;
12'd2939 : mem_out_dec = 6'b001000;
12'd2940 : mem_out_dec = 6'b001001;
12'd2941 : mem_out_dec = 6'b001010;
12'd2942 : mem_out_dec = 6'b001011;
12'd2943 : mem_out_dec = 6'b001011;
12'd2944 : mem_out_dec = 6'b111111;
12'd2945 : mem_out_dec = 6'b111111;
12'd2946 : mem_out_dec = 6'b111111;
12'd2947 : mem_out_dec = 6'b111111;
12'd2948 : mem_out_dec = 6'b111111;
12'd2949 : mem_out_dec = 6'b111111;
12'd2950 : mem_out_dec = 6'b111111;
12'd2951 : mem_out_dec = 6'b111111;
12'd2952 : mem_out_dec = 6'b111111;
12'd2953 : mem_out_dec = 6'b111111;
12'd2954 : mem_out_dec = 6'b111111;
12'd2955 : mem_out_dec = 6'b111111;
12'd2956 : mem_out_dec = 6'b111111;
12'd2957 : mem_out_dec = 6'b111111;
12'd2958 : mem_out_dec = 6'b111111;
12'd2959 : mem_out_dec = 6'b111111;
12'd2960 : mem_out_dec = 6'b111111;
12'd2961 : mem_out_dec = 6'b111111;
12'd2962 : mem_out_dec = 6'b111111;
12'd2963 : mem_out_dec = 6'b111111;
12'd2964 : mem_out_dec = 6'b111111;
12'd2965 : mem_out_dec = 6'b111111;
12'd2966 : mem_out_dec = 6'b111111;
12'd2967 : mem_out_dec = 6'b111111;
12'd2968 : mem_out_dec = 6'b111111;
12'd2969 : mem_out_dec = 6'b111111;
12'd2970 : mem_out_dec = 6'b111111;
12'd2971 : mem_out_dec = 6'b111111;
12'd2972 : mem_out_dec = 6'b111111;
12'd2973 : mem_out_dec = 6'b111111;
12'd2974 : mem_out_dec = 6'b111111;
12'd2975 : mem_out_dec = 6'b111111;
12'd2976 : mem_out_dec = 6'b111111;
12'd2977 : mem_out_dec = 6'b111111;
12'd2978 : mem_out_dec = 6'b111111;
12'd2979 : mem_out_dec = 6'b111111;
12'd2980 : mem_out_dec = 6'b111111;
12'd2981 : mem_out_dec = 6'b111111;
12'd2982 : mem_out_dec = 6'b111111;
12'd2983 : mem_out_dec = 6'b111111;
12'd2984 : mem_out_dec = 6'b111111;
12'd2985 : mem_out_dec = 6'b111111;
12'd2986 : mem_out_dec = 6'b111111;
12'd2987 : mem_out_dec = 6'b111111;
12'd2988 : mem_out_dec = 6'b111111;
12'd2989 : mem_out_dec = 6'b111111;
12'd2990 : mem_out_dec = 6'b111111;
12'd2991 : mem_out_dec = 6'b111111;
12'd2992 : mem_out_dec = 6'b111111;
12'd2993 : mem_out_dec = 6'b111111;
12'd2994 : mem_out_dec = 6'b111111;
12'd2995 : mem_out_dec = 6'b111111;
12'd2996 : mem_out_dec = 6'b000100;
12'd2997 : mem_out_dec = 6'b000101;
12'd2998 : mem_out_dec = 6'b000101;
12'd2999 : mem_out_dec = 6'b000110;
12'd3000 : mem_out_dec = 6'b000110;
12'd3001 : mem_out_dec = 6'b000111;
12'd3002 : mem_out_dec = 6'b000111;
12'd3003 : mem_out_dec = 6'b001000;
12'd3004 : mem_out_dec = 6'b001001;
12'd3005 : mem_out_dec = 6'b001010;
12'd3006 : mem_out_dec = 6'b001010;
12'd3007 : mem_out_dec = 6'b001011;
12'd3008 : mem_out_dec = 6'b111111;
12'd3009 : mem_out_dec = 6'b111111;
12'd3010 : mem_out_dec = 6'b111111;
12'd3011 : mem_out_dec = 6'b111111;
12'd3012 : mem_out_dec = 6'b111111;
12'd3013 : mem_out_dec = 6'b111111;
12'd3014 : mem_out_dec = 6'b111111;
12'd3015 : mem_out_dec = 6'b111111;
12'd3016 : mem_out_dec = 6'b111111;
12'd3017 : mem_out_dec = 6'b111111;
12'd3018 : mem_out_dec = 6'b111111;
12'd3019 : mem_out_dec = 6'b111111;
12'd3020 : mem_out_dec = 6'b111111;
12'd3021 : mem_out_dec = 6'b111111;
12'd3022 : mem_out_dec = 6'b111111;
12'd3023 : mem_out_dec = 6'b111111;
12'd3024 : mem_out_dec = 6'b111111;
12'd3025 : mem_out_dec = 6'b111111;
12'd3026 : mem_out_dec = 6'b111111;
12'd3027 : mem_out_dec = 6'b111111;
12'd3028 : mem_out_dec = 6'b111111;
12'd3029 : mem_out_dec = 6'b111111;
12'd3030 : mem_out_dec = 6'b111111;
12'd3031 : mem_out_dec = 6'b111111;
12'd3032 : mem_out_dec = 6'b111111;
12'd3033 : mem_out_dec = 6'b111111;
12'd3034 : mem_out_dec = 6'b111111;
12'd3035 : mem_out_dec = 6'b111111;
12'd3036 : mem_out_dec = 6'b111111;
12'd3037 : mem_out_dec = 6'b111111;
12'd3038 : mem_out_dec = 6'b111111;
12'd3039 : mem_out_dec = 6'b111111;
12'd3040 : mem_out_dec = 6'b111111;
12'd3041 : mem_out_dec = 6'b111111;
12'd3042 : mem_out_dec = 6'b111111;
12'd3043 : mem_out_dec = 6'b111111;
12'd3044 : mem_out_dec = 6'b111111;
12'd3045 : mem_out_dec = 6'b111111;
12'd3046 : mem_out_dec = 6'b111111;
12'd3047 : mem_out_dec = 6'b111111;
12'd3048 : mem_out_dec = 6'b111111;
12'd3049 : mem_out_dec = 6'b111111;
12'd3050 : mem_out_dec = 6'b111111;
12'd3051 : mem_out_dec = 6'b111111;
12'd3052 : mem_out_dec = 6'b111111;
12'd3053 : mem_out_dec = 6'b111111;
12'd3054 : mem_out_dec = 6'b111111;
12'd3055 : mem_out_dec = 6'b111111;
12'd3056 : mem_out_dec = 6'b111111;
12'd3057 : mem_out_dec = 6'b111111;
12'd3058 : mem_out_dec = 6'b111111;
12'd3059 : mem_out_dec = 6'b111111;
12'd3060 : mem_out_dec = 6'b111111;
12'd3061 : mem_out_dec = 6'b000100;
12'd3062 : mem_out_dec = 6'b000101;
12'd3063 : mem_out_dec = 6'b000110;
12'd3064 : mem_out_dec = 6'b000110;
12'd3065 : mem_out_dec = 6'b000111;
12'd3066 : mem_out_dec = 6'b000111;
12'd3067 : mem_out_dec = 6'b001000;
12'd3068 : mem_out_dec = 6'b001001;
12'd3069 : mem_out_dec = 6'b001001;
12'd3070 : mem_out_dec = 6'b001010;
12'd3071 : mem_out_dec = 6'b001011;
12'd3072 : mem_out_dec = 6'b111111;
12'd3073 : mem_out_dec = 6'b111111;
12'd3074 : mem_out_dec = 6'b111111;
12'd3075 : mem_out_dec = 6'b111111;
12'd3076 : mem_out_dec = 6'b111111;
12'd3077 : mem_out_dec = 6'b111111;
12'd3078 : mem_out_dec = 6'b111111;
12'd3079 : mem_out_dec = 6'b111111;
12'd3080 : mem_out_dec = 6'b111111;
12'd3081 : mem_out_dec = 6'b111111;
12'd3082 : mem_out_dec = 6'b111111;
12'd3083 : mem_out_dec = 6'b111111;
12'd3084 : mem_out_dec = 6'b111111;
12'd3085 : mem_out_dec = 6'b111111;
12'd3086 : mem_out_dec = 6'b111111;
12'd3087 : mem_out_dec = 6'b111111;
12'd3088 : mem_out_dec = 6'b111111;
12'd3089 : mem_out_dec = 6'b111111;
12'd3090 : mem_out_dec = 6'b111111;
12'd3091 : mem_out_dec = 6'b111111;
12'd3092 : mem_out_dec = 6'b111111;
12'd3093 : mem_out_dec = 6'b111111;
12'd3094 : mem_out_dec = 6'b111111;
12'd3095 : mem_out_dec = 6'b111111;
12'd3096 : mem_out_dec = 6'b111111;
12'd3097 : mem_out_dec = 6'b111111;
12'd3098 : mem_out_dec = 6'b111111;
12'd3099 : mem_out_dec = 6'b111111;
12'd3100 : mem_out_dec = 6'b111111;
12'd3101 : mem_out_dec = 6'b111111;
12'd3102 : mem_out_dec = 6'b111111;
12'd3103 : mem_out_dec = 6'b111111;
12'd3104 : mem_out_dec = 6'b111111;
12'd3105 : mem_out_dec = 6'b111111;
12'd3106 : mem_out_dec = 6'b111111;
12'd3107 : mem_out_dec = 6'b111111;
12'd3108 : mem_out_dec = 6'b111111;
12'd3109 : mem_out_dec = 6'b111111;
12'd3110 : mem_out_dec = 6'b111111;
12'd3111 : mem_out_dec = 6'b111111;
12'd3112 : mem_out_dec = 6'b111111;
12'd3113 : mem_out_dec = 6'b111111;
12'd3114 : mem_out_dec = 6'b111111;
12'd3115 : mem_out_dec = 6'b111111;
12'd3116 : mem_out_dec = 6'b111111;
12'd3117 : mem_out_dec = 6'b111111;
12'd3118 : mem_out_dec = 6'b111111;
12'd3119 : mem_out_dec = 6'b111111;
12'd3120 : mem_out_dec = 6'b111111;
12'd3121 : mem_out_dec = 6'b111111;
12'd3122 : mem_out_dec = 6'b111111;
12'd3123 : mem_out_dec = 6'b111111;
12'd3124 : mem_out_dec = 6'b111111;
12'd3125 : mem_out_dec = 6'b111111;
12'd3126 : mem_out_dec = 6'b000100;
12'd3127 : mem_out_dec = 6'b000101;
12'd3128 : mem_out_dec = 6'b000101;
12'd3129 : mem_out_dec = 6'b000110;
12'd3130 : mem_out_dec = 6'b000110;
12'd3131 : mem_out_dec = 6'b000111;
12'd3132 : mem_out_dec = 6'b001000;
12'd3133 : mem_out_dec = 6'b001000;
12'd3134 : mem_out_dec = 6'b001001;
12'd3135 : mem_out_dec = 6'b001010;
12'd3136 : mem_out_dec = 6'b111111;
12'd3137 : mem_out_dec = 6'b111111;
12'd3138 : mem_out_dec = 6'b111111;
12'd3139 : mem_out_dec = 6'b111111;
12'd3140 : mem_out_dec = 6'b111111;
12'd3141 : mem_out_dec = 6'b111111;
12'd3142 : mem_out_dec = 6'b111111;
12'd3143 : mem_out_dec = 6'b111111;
12'd3144 : mem_out_dec = 6'b111111;
12'd3145 : mem_out_dec = 6'b111111;
12'd3146 : mem_out_dec = 6'b111111;
12'd3147 : mem_out_dec = 6'b111111;
12'd3148 : mem_out_dec = 6'b111111;
12'd3149 : mem_out_dec = 6'b111111;
12'd3150 : mem_out_dec = 6'b111111;
12'd3151 : mem_out_dec = 6'b111111;
12'd3152 : mem_out_dec = 6'b111111;
12'd3153 : mem_out_dec = 6'b111111;
12'd3154 : mem_out_dec = 6'b111111;
12'd3155 : mem_out_dec = 6'b111111;
12'd3156 : mem_out_dec = 6'b111111;
12'd3157 : mem_out_dec = 6'b111111;
12'd3158 : mem_out_dec = 6'b111111;
12'd3159 : mem_out_dec = 6'b111111;
12'd3160 : mem_out_dec = 6'b111111;
12'd3161 : mem_out_dec = 6'b111111;
12'd3162 : mem_out_dec = 6'b111111;
12'd3163 : mem_out_dec = 6'b111111;
12'd3164 : mem_out_dec = 6'b111111;
12'd3165 : mem_out_dec = 6'b111111;
12'd3166 : mem_out_dec = 6'b111111;
12'd3167 : mem_out_dec = 6'b111111;
12'd3168 : mem_out_dec = 6'b111111;
12'd3169 : mem_out_dec = 6'b111111;
12'd3170 : mem_out_dec = 6'b111111;
12'd3171 : mem_out_dec = 6'b111111;
12'd3172 : mem_out_dec = 6'b111111;
12'd3173 : mem_out_dec = 6'b111111;
12'd3174 : mem_out_dec = 6'b111111;
12'd3175 : mem_out_dec = 6'b111111;
12'd3176 : mem_out_dec = 6'b111111;
12'd3177 : mem_out_dec = 6'b111111;
12'd3178 : mem_out_dec = 6'b111111;
12'd3179 : mem_out_dec = 6'b111111;
12'd3180 : mem_out_dec = 6'b111111;
12'd3181 : mem_out_dec = 6'b111111;
12'd3182 : mem_out_dec = 6'b111111;
12'd3183 : mem_out_dec = 6'b111111;
12'd3184 : mem_out_dec = 6'b111111;
12'd3185 : mem_out_dec = 6'b111111;
12'd3186 : mem_out_dec = 6'b111111;
12'd3187 : mem_out_dec = 6'b111111;
12'd3188 : mem_out_dec = 6'b111111;
12'd3189 : mem_out_dec = 6'b111111;
12'd3190 : mem_out_dec = 6'b111111;
12'd3191 : mem_out_dec = 6'b000100;
12'd3192 : mem_out_dec = 6'b000100;
12'd3193 : mem_out_dec = 6'b000101;
12'd3194 : mem_out_dec = 6'b000110;
12'd3195 : mem_out_dec = 6'b000110;
12'd3196 : mem_out_dec = 6'b000111;
12'd3197 : mem_out_dec = 6'b001000;
12'd3198 : mem_out_dec = 6'b001000;
12'd3199 : mem_out_dec = 6'b001001;
12'd3200 : mem_out_dec = 6'b111111;
12'd3201 : mem_out_dec = 6'b111111;
12'd3202 : mem_out_dec = 6'b111111;
12'd3203 : mem_out_dec = 6'b111111;
12'd3204 : mem_out_dec = 6'b111111;
12'd3205 : mem_out_dec = 6'b111111;
12'd3206 : mem_out_dec = 6'b111111;
12'd3207 : mem_out_dec = 6'b111111;
12'd3208 : mem_out_dec = 6'b111111;
12'd3209 : mem_out_dec = 6'b111111;
12'd3210 : mem_out_dec = 6'b111111;
12'd3211 : mem_out_dec = 6'b111111;
12'd3212 : mem_out_dec = 6'b111111;
12'd3213 : mem_out_dec = 6'b111111;
12'd3214 : mem_out_dec = 6'b111111;
12'd3215 : mem_out_dec = 6'b111111;
12'd3216 : mem_out_dec = 6'b111111;
12'd3217 : mem_out_dec = 6'b111111;
12'd3218 : mem_out_dec = 6'b111111;
12'd3219 : mem_out_dec = 6'b111111;
12'd3220 : mem_out_dec = 6'b111111;
12'd3221 : mem_out_dec = 6'b111111;
12'd3222 : mem_out_dec = 6'b111111;
12'd3223 : mem_out_dec = 6'b111111;
12'd3224 : mem_out_dec = 6'b111111;
12'd3225 : mem_out_dec = 6'b111111;
12'd3226 : mem_out_dec = 6'b111111;
12'd3227 : mem_out_dec = 6'b111111;
12'd3228 : mem_out_dec = 6'b111111;
12'd3229 : mem_out_dec = 6'b111111;
12'd3230 : mem_out_dec = 6'b111111;
12'd3231 : mem_out_dec = 6'b111111;
12'd3232 : mem_out_dec = 6'b111111;
12'd3233 : mem_out_dec = 6'b111111;
12'd3234 : mem_out_dec = 6'b111111;
12'd3235 : mem_out_dec = 6'b111111;
12'd3236 : mem_out_dec = 6'b111111;
12'd3237 : mem_out_dec = 6'b111111;
12'd3238 : mem_out_dec = 6'b111111;
12'd3239 : mem_out_dec = 6'b111111;
12'd3240 : mem_out_dec = 6'b111111;
12'd3241 : mem_out_dec = 6'b111111;
12'd3242 : mem_out_dec = 6'b111111;
12'd3243 : mem_out_dec = 6'b111111;
12'd3244 : mem_out_dec = 6'b111111;
12'd3245 : mem_out_dec = 6'b111111;
12'd3246 : mem_out_dec = 6'b111111;
12'd3247 : mem_out_dec = 6'b111111;
12'd3248 : mem_out_dec = 6'b111111;
12'd3249 : mem_out_dec = 6'b111111;
12'd3250 : mem_out_dec = 6'b111111;
12'd3251 : mem_out_dec = 6'b111111;
12'd3252 : mem_out_dec = 6'b111111;
12'd3253 : mem_out_dec = 6'b111111;
12'd3254 : mem_out_dec = 6'b111111;
12'd3255 : mem_out_dec = 6'b111111;
12'd3256 : mem_out_dec = 6'b000100;
12'd3257 : mem_out_dec = 6'b000100;
12'd3258 : mem_out_dec = 6'b000101;
12'd3259 : mem_out_dec = 6'b000110;
12'd3260 : mem_out_dec = 6'b000110;
12'd3261 : mem_out_dec = 6'b000111;
12'd3262 : mem_out_dec = 6'b001000;
12'd3263 : mem_out_dec = 6'b001001;
12'd3264 : mem_out_dec = 6'b111111;
12'd3265 : mem_out_dec = 6'b111111;
12'd3266 : mem_out_dec = 6'b111111;
12'd3267 : mem_out_dec = 6'b111111;
12'd3268 : mem_out_dec = 6'b111111;
12'd3269 : mem_out_dec = 6'b111111;
12'd3270 : mem_out_dec = 6'b111111;
12'd3271 : mem_out_dec = 6'b111111;
12'd3272 : mem_out_dec = 6'b111111;
12'd3273 : mem_out_dec = 6'b111111;
12'd3274 : mem_out_dec = 6'b111111;
12'd3275 : mem_out_dec = 6'b111111;
12'd3276 : mem_out_dec = 6'b111111;
12'd3277 : mem_out_dec = 6'b111111;
12'd3278 : mem_out_dec = 6'b111111;
12'd3279 : mem_out_dec = 6'b111111;
12'd3280 : mem_out_dec = 6'b111111;
12'd3281 : mem_out_dec = 6'b111111;
12'd3282 : mem_out_dec = 6'b111111;
12'd3283 : mem_out_dec = 6'b111111;
12'd3284 : mem_out_dec = 6'b111111;
12'd3285 : mem_out_dec = 6'b111111;
12'd3286 : mem_out_dec = 6'b111111;
12'd3287 : mem_out_dec = 6'b111111;
12'd3288 : mem_out_dec = 6'b111111;
12'd3289 : mem_out_dec = 6'b111111;
12'd3290 : mem_out_dec = 6'b111111;
12'd3291 : mem_out_dec = 6'b111111;
12'd3292 : mem_out_dec = 6'b111111;
12'd3293 : mem_out_dec = 6'b111111;
12'd3294 : mem_out_dec = 6'b111111;
12'd3295 : mem_out_dec = 6'b111111;
12'd3296 : mem_out_dec = 6'b111111;
12'd3297 : mem_out_dec = 6'b111111;
12'd3298 : mem_out_dec = 6'b111111;
12'd3299 : mem_out_dec = 6'b111111;
12'd3300 : mem_out_dec = 6'b111111;
12'd3301 : mem_out_dec = 6'b111111;
12'd3302 : mem_out_dec = 6'b111111;
12'd3303 : mem_out_dec = 6'b111111;
12'd3304 : mem_out_dec = 6'b111111;
12'd3305 : mem_out_dec = 6'b111111;
12'd3306 : mem_out_dec = 6'b111111;
12'd3307 : mem_out_dec = 6'b111111;
12'd3308 : mem_out_dec = 6'b111111;
12'd3309 : mem_out_dec = 6'b111111;
12'd3310 : mem_out_dec = 6'b111111;
12'd3311 : mem_out_dec = 6'b111111;
12'd3312 : mem_out_dec = 6'b111111;
12'd3313 : mem_out_dec = 6'b111111;
12'd3314 : mem_out_dec = 6'b111111;
12'd3315 : mem_out_dec = 6'b111111;
12'd3316 : mem_out_dec = 6'b111111;
12'd3317 : mem_out_dec = 6'b111111;
12'd3318 : mem_out_dec = 6'b111111;
12'd3319 : mem_out_dec = 6'b111111;
12'd3320 : mem_out_dec = 6'b111111;
12'd3321 : mem_out_dec = 6'b000100;
12'd3322 : mem_out_dec = 6'b000100;
12'd3323 : mem_out_dec = 6'b000101;
12'd3324 : mem_out_dec = 6'b000110;
12'd3325 : mem_out_dec = 6'b000111;
12'd3326 : mem_out_dec = 6'b001000;
12'd3327 : mem_out_dec = 6'b001000;
12'd3328 : mem_out_dec = 6'b111111;
12'd3329 : mem_out_dec = 6'b111111;
12'd3330 : mem_out_dec = 6'b111111;
12'd3331 : mem_out_dec = 6'b111111;
12'd3332 : mem_out_dec = 6'b111111;
12'd3333 : mem_out_dec = 6'b111111;
12'd3334 : mem_out_dec = 6'b111111;
12'd3335 : mem_out_dec = 6'b111111;
12'd3336 : mem_out_dec = 6'b111111;
12'd3337 : mem_out_dec = 6'b111111;
12'd3338 : mem_out_dec = 6'b111111;
12'd3339 : mem_out_dec = 6'b111111;
12'd3340 : mem_out_dec = 6'b111111;
12'd3341 : mem_out_dec = 6'b111111;
12'd3342 : mem_out_dec = 6'b111111;
12'd3343 : mem_out_dec = 6'b111111;
12'd3344 : mem_out_dec = 6'b111111;
12'd3345 : mem_out_dec = 6'b111111;
12'd3346 : mem_out_dec = 6'b111111;
12'd3347 : mem_out_dec = 6'b111111;
12'd3348 : mem_out_dec = 6'b111111;
12'd3349 : mem_out_dec = 6'b111111;
12'd3350 : mem_out_dec = 6'b111111;
12'd3351 : mem_out_dec = 6'b111111;
12'd3352 : mem_out_dec = 6'b111111;
12'd3353 : mem_out_dec = 6'b111111;
12'd3354 : mem_out_dec = 6'b111111;
12'd3355 : mem_out_dec = 6'b111111;
12'd3356 : mem_out_dec = 6'b111111;
12'd3357 : mem_out_dec = 6'b111111;
12'd3358 : mem_out_dec = 6'b111111;
12'd3359 : mem_out_dec = 6'b111111;
12'd3360 : mem_out_dec = 6'b111111;
12'd3361 : mem_out_dec = 6'b111111;
12'd3362 : mem_out_dec = 6'b111111;
12'd3363 : mem_out_dec = 6'b111111;
12'd3364 : mem_out_dec = 6'b111111;
12'd3365 : mem_out_dec = 6'b111111;
12'd3366 : mem_out_dec = 6'b111111;
12'd3367 : mem_out_dec = 6'b111111;
12'd3368 : mem_out_dec = 6'b111111;
12'd3369 : mem_out_dec = 6'b111111;
12'd3370 : mem_out_dec = 6'b111111;
12'd3371 : mem_out_dec = 6'b111111;
12'd3372 : mem_out_dec = 6'b111111;
12'd3373 : mem_out_dec = 6'b111111;
12'd3374 : mem_out_dec = 6'b111111;
12'd3375 : mem_out_dec = 6'b111111;
12'd3376 : mem_out_dec = 6'b111111;
12'd3377 : mem_out_dec = 6'b111111;
12'd3378 : mem_out_dec = 6'b111111;
12'd3379 : mem_out_dec = 6'b111111;
12'd3380 : mem_out_dec = 6'b111111;
12'd3381 : mem_out_dec = 6'b111111;
12'd3382 : mem_out_dec = 6'b111111;
12'd3383 : mem_out_dec = 6'b111111;
12'd3384 : mem_out_dec = 6'b111111;
12'd3385 : mem_out_dec = 6'b111111;
12'd3386 : mem_out_dec = 6'b000100;
12'd3387 : mem_out_dec = 6'b000101;
12'd3388 : mem_out_dec = 6'b000110;
12'd3389 : mem_out_dec = 6'b000110;
12'd3390 : mem_out_dec = 6'b000111;
12'd3391 : mem_out_dec = 6'b001000;
12'd3392 : mem_out_dec = 6'b111111;
12'd3393 : mem_out_dec = 6'b111111;
12'd3394 : mem_out_dec = 6'b111111;
12'd3395 : mem_out_dec = 6'b111111;
12'd3396 : mem_out_dec = 6'b111111;
12'd3397 : mem_out_dec = 6'b111111;
12'd3398 : mem_out_dec = 6'b111111;
12'd3399 : mem_out_dec = 6'b111111;
12'd3400 : mem_out_dec = 6'b111111;
12'd3401 : mem_out_dec = 6'b111111;
12'd3402 : mem_out_dec = 6'b111111;
12'd3403 : mem_out_dec = 6'b111111;
12'd3404 : mem_out_dec = 6'b111111;
12'd3405 : mem_out_dec = 6'b111111;
12'd3406 : mem_out_dec = 6'b111111;
12'd3407 : mem_out_dec = 6'b111111;
12'd3408 : mem_out_dec = 6'b111111;
12'd3409 : mem_out_dec = 6'b111111;
12'd3410 : mem_out_dec = 6'b111111;
12'd3411 : mem_out_dec = 6'b111111;
12'd3412 : mem_out_dec = 6'b111111;
12'd3413 : mem_out_dec = 6'b111111;
12'd3414 : mem_out_dec = 6'b111111;
12'd3415 : mem_out_dec = 6'b111111;
12'd3416 : mem_out_dec = 6'b111111;
12'd3417 : mem_out_dec = 6'b111111;
12'd3418 : mem_out_dec = 6'b111111;
12'd3419 : mem_out_dec = 6'b111111;
12'd3420 : mem_out_dec = 6'b111111;
12'd3421 : mem_out_dec = 6'b111111;
12'd3422 : mem_out_dec = 6'b111111;
12'd3423 : mem_out_dec = 6'b111111;
12'd3424 : mem_out_dec = 6'b111111;
12'd3425 : mem_out_dec = 6'b111111;
12'd3426 : mem_out_dec = 6'b111111;
12'd3427 : mem_out_dec = 6'b111111;
12'd3428 : mem_out_dec = 6'b111111;
12'd3429 : mem_out_dec = 6'b111111;
12'd3430 : mem_out_dec = 6'b111111;
12'd3431 : mem_out_dec = 6'b111111;
12'd3432 : mem_out_dec = 6'b111111;
12'd3433 : mem_out_dec = 6'b111111;
12'd3434 : mem_out_dec = 6'b111111;
12'd3435 : mem_out_dec = 6'b111111;
12'd3436 : mem_out_dec = 6'b111111;
12'd3437 : mem_out_dec = 6'b111111;
12'd3438 : mem_out_dec = 6'b111111;
12'd3439 : mem_out_dec = 6'b111111;
12'd3440 : mem_out_dec = 6'b111111;
12'd3441 : mem_out_dec = 6'b111111;
12'd3442 : mem_out_dec = 6'b111111;
12'd3443 : mem_out_dec = 6'b111111;
12'd3444 : mem_out_dec = 6'b111111;
12'd3445 : mem_out_dec = 6'b111111;
12'd3446 : mem_out_dec = 6'b111111;
12'd3447 : mem_out_dec = 6'b111111;
12'd3448 : mem_out_dec = 6'b111111;
12'd3449 : mem_out_dec = 6'b111111;
12'd3450 : mem_out_dec = 6'b111111;
12'd3451 : mem_out_dec = 6'b000100;
12'd3452 : mem_out_dec = 6'b000101;
12'd3453 : mem_out_dec = 6'b000110;
12'd3454 : mem_out_dec = 6'b000111;
12'd3455 : mem_out_dec = 6'b001000;
12'd3456 : mem_out_dec = 6'b111111;
12'd3457 : mem_out_dec = 6'b111111;
12'd3458 : mem_out_dec = 6'b111111;
12'd3459 : mem_out_dec = 6'b111111;
12'd3460 : mem_out_dec = 6'b111111;
12'd3461 : mem_out_dec = 6'b111111;
12'd3462 : mem_out_dec = 6'b111111;
12'd3463 : mem_out_dec = 6'b111111;
12'd3464 : mem_out_dec = 6'b111111;
12'd3465 : mem_out_dec = 6'b111111;
12'd3466 : mem_out_dec = 6'b111111;
12'd3467 : mem_out_dec = 6'b111111;
12'd3468 : mem_out_dec = 6'b111111;
12'd3469 : mem_out_dec = 6'b111111;
12'd3470 : mem_out_dec = 6'b111111;
12'd3471 : mem_out_dec = 6'b111111;
12'd3472 : mem_out_dec = 6'b111111;
12'd3473 : mem_out_dec = 6'b111111;
12'd3474 : mem_out_dec = 6'b111111;
12'd3475 : mem_out_dec = 6'b111111;
12'd3476 : mem_out_dec = 6'b111111;
12'd3477 : mem_out_dec = 6'b111111;
12'd3478 : mem_out_dec = 6'b111111;
12'd3479 : mem_out_dec = 6'b111111;
12'd3480 : mem_out_dec = 6'b111111;
12'd3481 : mem_out_dec = 6'b111111;
12'd3482 : mem_out_dec = 6'b111111;
12'd3483 : mem_out_dec = 6'b111111;
12'd3484 : mem_out_dec = 6'b111111;
12'd3485 : mem_out_dec = 6'b111111;
12'd3486 : mem_out_dec = 6'b111111;
12'd3487 : mem_out_dec = 6'b111111;
12'd3488 : mem_out_dec = 6'b111111;
12'd3489 : mem_out_dec = 6'b111111;
12'd3490 : mem_out_dec = 6'b111111;
12'd3491 : mem_out_dec = 6'b111111;
12'd3492 : mem_out_dec = 6'b111111;
12'd3493 : mem_out_dec = 6'b111111;
12'd3494 : mem_out_dec = 6'b111111;
12'd3495 : mem_out_dec = 6'b111111;
12'd3496 : mem_out_dec = 6'b111111;
12'd3497 : mem_out_dec = 6'b111111;
12'd3498 : mem_out_dec = 6'b111111;
12'd3499 : mem_out_dec = 6'b111111;
12'd3500 : mem_out_dec = 6'b111111;
12'd3501 : mem_out_dec = 6'b111111;
12'd3502 : mem_out_dec = 6'b111111;
12'd3503 : mem_out_dec = 6'b111111;
12'd3504 : mem_out_dec = 6'b111111;
12'd3505 : mem_out_dec = 6'b111111;
12'd3506 : mem_out_dec = 6'b111111;
12'd3507 : mem_out_dec = 6'b111111;
12'd3508 : mem_out_dec = 6'b111111;
12'd3509 : mem_out_dec = 6'b111111;
12'd3510 : mem_out_dec = 6'b111111;
12'd3511 : mem_out_dec = 6'b111111;
12'd3512 : mem_out_dec = 6'b111111;
12'd3513 : mem_out_dec = 6'b111111;
12'd3514 : mem_out_dec = 6'b111111;
12'd3515 : mem_out_dec = 6'b111111;
12'd3516 : mem_out_dec = 6'b000101;
12'd3517 : mem_out_dec = 6'b000110;
12'd3518 : mem_out_dec = 6'b000110;
12'd3519 : mem_out_dec = 6'b000111;
12'd3520 : mem_out_dec = 6'b111111;
12'd3521 : mem_out_dec = 6'b111111;
12'd3522 : mem_out_dec = 6'b111111;
12'd3523 : mem_out_dec = 6'b111111;
12'd3524 : mem_out_dec = 6'b111111;
12'd3525 : mem_out_dec = 6'b111111;
12'd3526 : mem_out_dec = 6'b111111;
12'd3527 : mem_out_dec = 6'b111111;
12'd3528 : mem_out_dec = 6'b111111;
12'd3529 : mem_out_dec = 6'b111111;
12'd3530 : mem_out_dec = 6'b111111;
12'd3531 : mem_out_dec = 6'b111111;
12'd3532 : mem_out_dec = 6'b111111;
12'd3533 : mem_out_dec = 6'b111111;
12'd3534 : mem_out_dec = 6'b111111;
12'd3535 : mem_out_dec = 6'b111111;
12'd3536 : mem_out_dec = 6'b111111;
12'd3537 : mem_out_dec = 6'b111111;
12'd3538 : mem_out_dec = 6'b111111;
12'd3539 : mem_out_dec = 6'b111111;
12'd3540 : mem_out_dec = 6'b111111;
12'd3541 : mem_out_dec = 6'b111111;
12'd3542 : mem_out_dec = 6'b111111;
12'd3543 : mem_out_dec = 6'b111111;
12'd3544 : mem_out_dec = 6'b111111;
12'd3545 : mem_out_dec = 6'b111111;
12'd3546 : mem_out_dec = 6'b111111;
12'd3547 : mem_out_dec = 6'b111111;
12'd3548 : mem_out_dec = 6'b111111;
12'd3549 : mem_out_dec = 6'b111111;
12'd3550 : mem_out_dec = 6'b111111;
12'd3551 : mem_out_dec = 6'b111111;
12'd3552 : mem_out_dec = 6'b111111;
12'd3553 : mem_out_dec = 6'b111111;
12'd3554 : mem_out_dec = 6'b111111;
12'd3555 : mem_out_dec = 6'b111111;
12'd3556 : mem_out_dec = 6'b111111;
12'd3557 : mem_out_dec = 6'b111111;
12'd3558 : mem_out_dec = 6'b111111;
12'd3559 : mem_out_dec = 6'b111111;
12'd3560 : mem_out_dec = 6'b111111;
12'd3561 : mem_out_dec = 6'b111111;
12'd3562 : mem_out_dec = 6'b111111;
12'd3563 : mem_out_dec = 6'b111111;
12'd3564 : mem_out_dec = 6'b111111;
12'd3565 : mem_out_dec = 6'b111111;
12'd3566 : mem_out_dec = 6'b111111;
12'd3567 : mem_out_dec = 6'b111111;
12'd3568 : mem_out_dec = 6'b111111;
12'd3569 : mem_out_dec = 6'b111111;
12'd3570 : mem_out_dec = 6'b111111;
12'd3571 : mem_out_dec = 6'b111111;
12'd3572 : mem_out_dec = 6'b111111;
12'd3573 : mem_out_dec = 6'b111111;
12'd3574 : mem_out_dec = 6'b111111;
12'd3575 : mem_out_dec = 6'b111111;
12'd3576 : mem_out_dec = 6'b111111;
12'd3577 : mem_out_dec = 6'b111111;
12'd3578 : mem_out_dec = 6'b111111;
12'd3579 : mem_out_dec = 6'b111111;
12'd3580 : mem_out_dec = 6'b111111;
12'd3581 : mem_out_dec = 6'b000101;
12'd3582 : mem_out_dec = 6'b000110;
12'd3583 : mem_out_dec = 6'b000110;
12'd3584 : mem_out_dec = 6'b111111;
12'd3585 : mem_out_dec = 6'b111111;
12'd3586 : mem_out_dec = 6'b111111;
12'd3587 : mem_out_dec = 6'b111111;
12'd3588 : mem_out_dec = 6'b111111;
12'd3589 : mem_out_dec = 6'b111111;
12'd3590 : mem_out_dec = 6'b111111;
12'd3591 : mem_out_dec = 6'b111111;
12'd3592 : mem_out_dec = 6'b111111;
12'd3593 : mem_out_dec = 6'b111111;
12'd3594 : mem_out_dec = 6'b111111;
12'd3595 : mem_out_dec = 6'b111111;
12'd3596 : mem_out_dec = 6'b111111;
12'd3597 : mem_out_dec = 6'b111111;
12'd3598 : mem_out_dec = 6'b111111;
12'd3599 : mem_out_dec = 6'b111111;
12'd3600 : mem_out_dec = 6'b111111;
12'd3601 : mem_out_dec = 6'b111111;
12'd3602 : mem_out_dec = 6'b111111;
12'd3603 : mem_out_dec = 6'b111111;
12'd3604 : mem_out_dec = 6'b111111;
12'd3605 : mem_out_dec = 6'b111111;
12'd3606 : mem_out_dec = 6'b111111;
12'd3607 : mem_out_dec = 6'b111111;
12'd3608 : mem_out_dec = 6'b111111;
12'd3609 : mem_out_dec = 6'b111111;
12'd3610 : mem_out_dec = 6'b111111;
12'd3611 : mem_out_dec = 6'b111111;
12'd3612 : mem_out_dec = 6'b111111;
12'd3613 : mem_out_dec = 6'b111111;
12'd3614 : mem_out_dec = 6'b111111;
12'd3615 : mem_out_dec = 6'b111111;
12'd3616 : mem_out_dec = 6'b111111;
12'd3617 : mem_out_dec = 6'b111111;
12'd3618 : mem_out_dec = 6'b111111;
12'd3619 : mem_out_dec = 6'b111111;
12'd3620 : mem_out_dec = 6'b111111;
12'd3621 : mem_out_dec = 6'b111111;
12'd3622 : mem_out_dec = 6'b111111;
12'd3623 : mem_out_dec = 6'b111111;
12'd3624 : mem_out_dec = 6'b111111;
12'd3625 : mem_out_dec = 6'b111111;
12'd3626 : mem_out_dec = 6'b111111;
12'd3627 : mem_out_dec = 6'b111111;
12'd3628 : mem_out_dec = 6'b111111;
12'd3629 : mem_out_dec = 6'b111111;
12'd3630 : mem_out_dec = 6'b111111;
12'd3631 : mem_out_dec = 6'b111111;
12'd3632 : mem_out_dec = 6'b111111;
12'd3633 : mem_out_dec = 6'b111111;
12'd3634 : mem_out_dec = 6'b111111;
12'd3635 : mem_out_dec = 6'b111111;
12'd3636 : mem_out_dec = 6'b111111;
12'd3637 : mem_out_dec = 6'b111111;
12'd3638 : mem_out_dec = 6'b111111;
12'd3639 : mem_out_dec = 6'b111111;
12'd3640 : mem_out_dec = 6'b111111;
12'd3641 : mem_out_dec = 6'b111111;
12'd3642 : mem_out_dec = 6'b111111;
12'd3643 : mem_out_dec = 6'b111111;
12'd3644 : mem_out_dec = 6'b111111;
12'd3645 : mem_out_dec = 6'b111111;
12'd3646 : mem_out_dec = 6'b000100;
12'd3647 : mem_out_dec = 6'b000101;
12'd3648 : mem_out_dec = 6'b111111;
12'd3649 : mem_out_dec = 6'b111111;
12'd3650 : mem_out_dec = 6'b111111;
12'd3651 : mem_out_dec = 6'b111111;
12'd3652 : mem_out_dec = 6'b111111;
12'd3653 : mem_out_dec = 6'b111111;
12'd3654 : mem_out_dec = 6'b111111;
12'd3655 : mem_out_dec = 6'b111111;
12'd3656 : mem_out_dec = 6'b111111;
12'd3657 : mem_out_dec = 6'b111111;
12'd3658 : mem_out_dec = 6'b111111;
12'd3659 : mem_out_dec = 6'b111111;
12'd3660 : mem_out_dec = 6'b111111;
12'd3661 : mem_out_dec = 6'b111111;
12'd3662 : mem_out_dec = 6'b111111;
12'd3663 : mem_out_dec = 6'b111111;
12'd3664 : mem_out_dec = 6'b111111;
12'd3665 : mem_out_dec = 6'b111111;
12'd3666 : mem_out_dec = 6'b111111;
12'd3667 : mem_out_dec = 6'b111111;
12'd3668 : mem_out_dec = 6'b111111;
12'd3669 : mem_out_dec = 6'b111111;
12'd3670 : mem_out_dec = 6'b111111;
12'd3671 : mem_out_dec = 6'b111111;
12'd3672 : mem_out_dec = 6'b111111;
12'd3673 : mem_out_dec = 6'b111111;
12'd3674 : mem_out_dec = 6'b111111;
12'd3675 : mem_out_dec = 6'b111111;
12'd3676 : mem_out_dec = 6'b111111;
12'd3677 : mem_out_dec = 6'b111111;
12'd3678 : mem_out_dec = 6'b111111;
12'd3679 : mem_out_dec = 6'b111111;
12'd3680 : mem_out_dec = 6'b111111;
12'd3681 : mem_out_dec = 6'b111111;
12'd3682 : mem_out_dec = 6'b111111;
12'd3683 : mem_out_dec = 6'b111111;
12'd3684 : mem_out_dec = 6'b111111;
12'd3685 : mem_out_dec = 6'b111111;
12'd3686 : mem_out_dec = 6'b111111;
12'd3687 : mem_out_dec = 6'b111111;
12'd3688 : mem_out_dec = 6'b111111;
12'd3689 : mem_out_dec = 6'b111111;
12'd3690 : mem_out_dec = 6'b111111;
12'd3691 : mem_out_dec = 6'b111111;
12'd3692 : mem_out_dec = 6'b111111;
12'd3693 : mem_out_dec = 6'b111111;
12'd3694 : mem_out_dec = 6'b111111;
12'd3695 : mem_out_dec = 6'b111111;
12'd3696 : mem_out_dec = 6'b111111;
12'd3697 : mem_out_dec = 6'b111111;
12'd3698 : mem_out_dec = 6'b111111;
12'd3699 : mem_out_dec = 6'b111111;
12'd3700 : mem_out_dec = 6'b111111;
12'd3701 : mem_out_dec = 6'b111111;
12'd3702 : mem_out_dec = 6'b111111;
12'd3703 : mem_out_dec = 6'b111111;
12'd3704 : mem_out_dec = 6'b111111;
12'd3705 : mem_out_dec = 6'b111111;
12'd3706 : mem_out_dec = 6'b111111;
12'd3707 : mem_out_dec = 6'b111111;
12'd3708 : mem_out_dec = 6'b111111;
12'd3709 : mem_out_dec = 6'b111111;
12'd3710 : mem_out_dec = 6'b111111;
12'd3711 : mem_out_dec = 6'b000100;
12'd3712 : mem_out_dec = 6'b111111;
12'd3713 : mem_out_dec = 6'b111111;
12'd3714 : mem_out_dec = 6'b111111;
12'd3715 : mem_out_dec = 6'b111111;
12'd3716 : mem_out_dec = 6'b111111;
12'd3717 : mem_out_dec = 6'b111111;
12'd3718 : mem_out_dec = 6'b111111;
12'd3719 : mem_out_dec = 6'b111111;
12'd3720 : mem_out_dec = 6'b111111;
12'd3721 : mem_out_dec = 6'b111111;
12'd3722 : mem_out_dec = 6'b111111;
12'd3723 : mem_out_dec = 6'b111111;
12'd3724 : mem_out_dec = 6'b111111;
12'd3725 : mem_out_dec = 6'b111111;
12'd3726 : mem_out_dec = 6'b111111;
12'd3727 : mem_out_dec = 6'b111111;
12'd3728 : mem_out_dec = 6'b111111;
12'd3729 : mem_out_dec = 6'b111111;
12'd3730 : mem_out_dec = 6'b111111;
12'd3731 : mem_out_dec = 6'b111111;
12'd3732 : mem_out_dec = 6'b111111;
12'd3733 : mem_out_dec = 6'b111111;
12'd3734 : mem_out_dec = 6'b111111;
12'd3735 : mem_out_dec = 6'b111111;
12'd3736 : mem_out_dec = 6'b111111;
12'd3737 : mem_out_dec = 6'b111111;
12'd3738 : mem_out_dec = 6'b111111;
12'd3739 : mem_out_dec = 6'b111111;
12'd3740 : mem_out_dec = 6'b111111;
12'd3741 : mem_out_dec = 6'b111111;
12'd3742 : mem_out_dec = 6'b111111;
12'd3743 : mem_out_dec = 6'b111111;
12'd3744 : mem_out_dec = 6'b111111;
12'd3745 : mem_out_dec = 6'b111111;
12'd3746 : mem_out_dec = 6'b111111;
12'd3747 : mem_out_dec = 6'b111111;
12'd3748 : mem_out_dec = 6'b111111;
12'd3749 : mem_out_dec = 6'b111111;
12'd3750 : mem_out_dec = 6'b111111;
12'd3751 : mem_out_dec = 6'b111111;
12'd3752 : mem_out_dec = 6'b111111;
12'd3753 : mem_out_dec = 6'b111111;
12'd3754 : mem_out_dec = 6'b111111;
12'd3755 : mem_out_dec = 6'b111111;
12'd3756 : mem_out_dec = 6'b111111;
12'd3757 : mem_out_dec = 6'b111111;
12'd3758 : mem_out_dec = 6'b111111;
12'd3759 : mem_out_dec = 6'b111111;
12'd3760 : mem_out_dec = 6'b111111;
12'd3761 : mem_out_dec = 6'b111111;
12'd3762 : mem_out_dec = 6'b111111;
12'd3763 : mem_out_dec = 6'b111111;
12'd3764 : mem_out_dec = 6'b111111;
12'd3765 : mem_out_dec = 6'b111111;
12'd3766 : mem_out_dec = 6'b111111;
12'd3767 : mem_out_dec = 6'b111111;
12'd3768 : mem_out_dec = 6'b111111;
12'd3769 : mem_out_dec = 6'b111111;
12'd3770 : mem_out_dec = 6'b111111;
12'd3771 : mem_out_dec = 6'b111111;
12'd3772 : mem_out_dec = 6'b111111;
12'd3773 : mem_out_dec = 6'b111111;
12'd3774 : mem_out_dec = 6'b111111;
12'd3775 : mem_out_dec = 6'b111111;
12'd3776 : mem_out_dec = 6'b111111;
12'd3777 : mem_out_dec = 6'b111111;
12'd3778 : mem_out_dec = 6'b111111;
12'd3779 : mem_out_dec = 6'b111111;
12'd3780 : mem_out_dec = 6'b111111;
12'd3781 : mem_out_dec = 6'b111111;
12'd3782 : mem_out_dec = 6'b111111;
12'd3783 : mem_out_dec = 6'b111111;
12'd3784 : mem_out_dec = 6'b111111;
12'd3785 : mem_out_dec = 6'b111111;
12'd3786 : mem_out_dec = 6'b111111;
12'd3787 : mem_out_dec = 6'b111111;
12'd3788 : mem_out_dec = 6'b111111;
12'd3789 : mem_out_dec = 6'b111111;
12'd3790 : mem_out_dec = 6'b111111;
12'd3791 : mem_out_dec = 6'b111111;
12'd3792 : mem_out_dec = 6'b111111;
12'd3793 : mem_out_dec = 6'b111111;
12'd3794 : mem_out_dec = 6'b111111;
12'd3795 : mem_out_dec = 6'b111111;
12'd3796 : mem_out_dec = 6'b111111;
12'd3797 : mem_out_dec = 6'b111111;
12'd3798 : mem_out_dec = 6'b111111;
12'd3799 : mem_out_dec = 6'b111111;
12'd3800 : mem_out_dec = 6'b111111;
12'd3801 : mem_out_dec = 6'b111111;
12'd3802 : mem_out_dec = 6'b111111;
12'd3803 : mem_out_dec = 6'b111111;
12'd3804 : mem_out_dec = 6'b111111;
12'd3805 : mem_out_dec = 6'b111111;
12'd3806 : mem_out_dec = 6'b111111;
12'd3807 : mem_out_dec = 6'b111111;
12'd3808 : mem_out_dec = 6'b111111;
12'd3809 : mem_out_dec = 6'b111111;
12'd3810 : mem_out_dec = 6'b111111;
12'd3811 : mem_out_dec = 6'b111111;
12'd3812 : mem_out_dec = 6'b111111;
12'd3813 : mem_out_dec = 6'b111111;
12'd3814 : mem_out_dec = 6'b111111;
12'd3815 : mem_out_dec = 6'b111111;
12'd3816 : mem_out_dec = 6'b111111;
12'd3817 : mem_out_dec = 6'b111111;
12'd3818 : mem_out_dec = 6'b111111;
12'd3819 : mem_out_dec = 6'b111111;
12'd3820 : mem_out_dec = 6'b111111;
12'd3821 : mem_out_dec = 6'b111111;
12'd3822 : mem_out_dec = 6'b111111;
12'd3823 : mem_out_dec = 6'b111111;
12'd3824 : mem_out_dec = 6'b111111;
12'd3825 : mem_out_dec = 6'b111111;
12'd3826 : mem_out_dec = 6'b111111;
12'd3827 : mem_out_dec = 6'b111111;
12'd3828 : mem_out_dec = 6'b111111;
12'd3829 : mem_out_dec = 6'b111111;
12'd3830 : mem_out_dec = 6'b111111;
12'd3831 : mem_out_dec = 6'b111111;
12'd3832 : mem_out_dec = 6'b111111;
12'd3833 : mem_out_dec = 6'b111111;
12'd3834 : mem_out_dec = 6'b111111;
12'd3835 : mem_out_dec = 6'b111111;
12'd3836 : mem_out_dec = 6'b111111;
12'd3837 : mem_out_dec = 6'b111111;
12'd3838 : mem_out_dec = 6'b111111;
12'd3839 : mem_out_dec = 6'b111111;
12'd3840 : mem_out_dec = 6'b111111;
12'd3841 : mem_out_dec = 6'b111111;
12'd3842 : mem_out_dec = 6'b111111;
12'd3843 : mem_out_dec = 6'b111111;
12'd3844 : mem_out_dec = 6'b111111;
12'd3845 : mem_out_dec = 6'b111111;
12'd3846 : mem_out_dec = 6'b111111;
12'd3847 : mem_out_dec = 6'b111111;
12'd3848 : mem_out_dec = 6'b111111;
12'd3849 : mem_out_dec = 6'b111111;
12'd3850 : mem_out_dec = 6'b111111;
12'd3851 : mem_out_dec = 6'b111111;
12'd3852 : mem_out_dec = 6'b111111;
12'd3853 : mem_out_dec = 6'b111111;
12'd3854 : mem_out_dec = 6'b111111;
12'd3855 : mem_out_dec = 6'b111111;
12'd3856 : mem_out_dec = 6'b111111;
12'd3857 : mem_out_dec = 6'b111111;
12'd3858 : mem_out_dec = 6'b111111;
12'd3859 : mem_out_dec = 6'b111111;
12'd3860 : mem_out_dec = 6'b111111;
12'd3861 : mem_out_dec = 6'b111111;
12'd3862 : mem_out_dec = 6'b111111;
12'd3863 : mem_out_dec = 6'b111111;
12'd3864 : mem_out_dec = 6'b111111;
12'd3865 : mem_out_dec = 6'b111111;
12'd3866 : mem_out_dec = 6'b111111;
12'd3867 : mem_out_dec = 6'b111111;
12'd3868 : mem_out_dec = 6'b111111;
12'd3869 : mem_out_dec = 6'b111111;
12'd3870 : mem_out_dec = 6'b111111;
12'd3871 : mem_out_dec = 6'b111111;
12'd3872 : mem_out_dec = 6'b111111;
12'd3873 : mem_out_dec = 6'b111111;
12'd3874 : mem_out_dec = 6'b111111;
12'd3875 : mem_out_dec = 6'b111111;
12'd3876 : mem_out_dec = 6'b111111;
12'd3877 : mem_out_dec = 6'b111111;
12'd3878 : mem_out_dec = 6'b111111;
12'd3879 : mem_out_dec = 6'b111111;
12'd3880 : mem_out_dec = 6'b111111;
12'd3881 : mem_out_dec = 6'b111111;
12'd3882 : mem_out_dec = 6'b111111;
12'd3883 : mem_out_dec = 6'b111111;
12'd3884 : mem_out_dec = 6'b111111;
12'd3885 : mem_out_dec = 6'b111111;
12'd3886 : mem_out_dec = 6'b111111;
12'd3887 : mem_out_dec = 6'b111111;
12'd3888 : mem_out_dec = 6'b111111;
12'd3889 : mem_out_dec = 6'b111111;
12'd3890 : mem_out_dec = 6'b111111;
12'd3891 : mem_out_dec = 6'b111111;
12'd3892 : mem_out_dec = 6'b111111;
12'd3893 : mem_out_dec = 6'b111111;
12'd3894 : mem_out_dec = 6'b111111;
12'd3895 : mem_out_dec = 6'b111111;
12'd3896 : mem_out_dec = 6'b111111;
12'd3897 : mem_out_dec = 6'b111111;
12'd3898 : mem_out_dec = 6'b111111;
12'd3899 : mem_out_dec = 6'b111111;
12'd3900 : mem_out_dec = 6'b111111;
12'd3901 : mem_out_dec = 6'b111111;
12'd3902 : mem_out_dec = 6'b111111;
12'd3903 : mem_out_dec = 6'b111111;
12'd3904 : mem_out_dec = 6'b111111;
12'd3905 : mem_out_dec = 6'b111111;
12'd3906 : mem_out_dec = 6'b111111;
12'd3907 : mem_out_dec = 6'b111111;
12'd3908 : mem_out_dec = 6'b111111;
12'd3909 : mem_out_dec = 6'b111111;
12'd3910 : mem_out_dec = 6'b111111;
12'd3911 : mem_out_dec = 6'b111111;
12'd3912 : mem_out_dec = 6'b111111;
12'd3913 : mem_out_dec = 6'b111111;
12'd3914 : mem_out_dec = 6'b111111;
12'd3915 : mem_out_dec = 6'b111111;
12'd3916 : mem_out_dec = 6'b111111;
12'd3917 : mem_out_dec = 6'b111111;
12'd3918 : mem_out_dec = 6'b111111;
12'd3919 : mem_out_dec = 6'b111111;
12'd3920 : mem_out_dec = 6'b111111;
12'd3921 : mem_out_dec = 6'b111111;
12'd3922 : mem_out_dec = 6'b111111;
12'd3923 : mem_out_dec = 6'b111111;
12'd3924 : mem_out_dec = 6'b111111;
12'd3925 : mem_out_dec = 6'b111111;
12'd3926 : mem_out_dec = 6'b111111;
12'd3927 : mem_out_dec = 6'b111111;
12'd3928 : mem_out_dec = 6'b111111;
12'd3929 : mem_out_dec = 6'b111111;
12'd3930 : mem_out_dec = 6'b111111;
12'd3931 : mem_out_dec = 6'b111111;
12'd3932 : mem_out_dec = 6'b111111;
12'd3933 : mem_out_dec = 6'b111111;
12'd3934 : mem_out_dec = 6'b111111;
12'd3935 : mem_out_dec = 6'b111111;
12'd3936 : mem_out_dec = 6'b111111;
12'd3937 : mem_out_dec = 6'b111111;
12'd3938 : mem_out_dec = 6'b111111;
12'd3939 : mem_out_dec = 6'b111111;
12'd3940 : mem_out_dec = 6'b111111;
12'd3941 : mem_out_dec = 6'b111111;
12'd3942 : mem_out_dec = 6'b111111;
12'd3943 : mem_out_dec = 6'b111111;
12'd3944 : mem_out_dec = 6'b111111;
12'd3945 : mem_out_dec = 6'b111111;
12'd3946 : mem_out_dec = 6'b111111;
12'd3947 : mem_out_dec = 6'b111111;
12'd3948 : mem_out_dec = 6'b111111;
12'd3949 : mem_out_dec = 6'b111111;
12'd3950 : mem_out_dec = 6'b111111;
12'd3951 : mem_out_dec = 6'b111111;
12'd3952 : mem_out_dec = 6'b111111;
12'd3953 : mem_out_dec = 6'b111111;
12'd3954 : mem_out_dec = 6'b111111;
12'd3955 : mem_out_dec = 6'b111111;
12'd3956 : mem_out_dec = 6'b111111;
12'd3957 : mem_out_dec = 6'b111111;
12'd3958 : mem_out_dec = 6'b111111;
12'd3959 : mem_out_dec = 6'b111111;
12'd3960 : mem_out_dec = 6'b111111;
12'd3961 : mem_out_dec = 6'b111111;
12'd3962 : mem_out_dec = 6'b111111;
12'd3963 : mem_out_dec = 6'b111111;
12'd3964 : mem_out_dec = 6'b111111;
12'd3965 : mem_out_dec = 6'b111111;
12'd3966 : mem_out_dec = 6'b111111;
12'd3967 : mem_out_dec = 6'b111111;
12'd3968 : mem_out_dec = 6'b111111;
12'd3969 : mem_out_dec = 6'b111111;
12'd3970 : mem_out_dec = 6'b111111;
12'd3971 : mem_out_dec = 6'b111111;
12'd3972 : mem_out_dec = 6'b111111;
12'd3973 : mem_out_dec = 6'b111111;
12'd3974 : mem_out_dec = 6'b111111;
12'd3975 : mem_out_dec = 6'b111111;
12'd3976 : mem_out_dec = 6'b111111;
12'd3977 : mem_out_dec = 6'b111111;
12'd3978 : mem_out_dec = 6'b111111;
12'd3979 : mem_out_dec = 6'b111111;
12'd3980 : mem_out_dec = 6'b111111;
12'd3981 : mem_out_dec = 6'b111111;
12'd3982 : mem_out_dec = 6'b111111;
12'd3983 : mem_out_dec = 6'b111111;
12'd3984 : mem_out_dec = 6'b111111;
12'd3985 : mem_out_dec = 6'b111111;
12'd3986 : mem_out_dec = 6'b111111;
12'd3987 : mem_out_dec = 6'b111111;
12'd3988 : mem_out_dec = 6'b111111;
12'd3989 : mem_out_dec = 6'b111111;
12'd3990 : mem_out_dec = 6'b111111;
12'd3991 : mem_out_dec = 6'b111111;
12'd3992 : mem_out_dec = 6'b111111;
12'd3993 : mem_out_dec = 6'b111111;
12'd3994 : mem_out_dec = 6'b111111;
12'd3995 : mem_out_dec = 6'b111111;
12'd3996 : mem_out_dec = 6'b111111;
12'd3997 : mem_out_dec = 6'b111111;
12'd3998 : mem_out_dec = 6'b111111;
12'd3999 : mem_out_dec = 6'b111111;
12'd4000 : mem_out_dec = 6'b111111;
12'd4001 : mem_out_dec = 6'b111111;
12'd4002 : mem_out_dec = 6'b111111;
12'd4003 : mem_out_dec = 6'b111111;
12'd4004 : mem_out_dec = 6'b111111;
12'd4005 : mem_out_dec = 6'b111111;
12'd4006 : mem_out_dec = 6'b111111;
12'd4007 : mem_out_dec = 6'b111111;
12'd4008 : mem_out_dec = 6'b111111;
12'd4009 : mem_out_dec = 6'b111111;
12'd4010 : mem_out_dec = 6'b111111;
12'd4011 : mem_out_dec = 6'b111111;
12'd4012 : mem_out_dec = 6'b111111;
12'd4013 : mem_out_dec = 6'b111111;
12'd4014 : mem_out_dec = 6'b111111;
12'd4015 : mem_out_dec = 6'b111111;
12'd4016 : mem_out_dec = 6'b111111;
12'd4017 : mem_out_dec = 6'b111111;
12'd4018 : mem_out_dec = 6'b111111;
12'd4019 : mem_out_dec = 6'b111111;
12'd4020 : mem_out_dec = 6'b111111;
12'd4021 : mem_out_dec = 6'b111111;
12'd4022 : mem_out_dec = 6'b111111;
12'd4023 : mem_out_dec = 6'b111111;
12'd4024 : mem_out_dec = 6'b111111;
12'd4025 : mem_out_dec = 6'b111111;
12'd4026 : mem_out_dec = 6'b111111;
12'd4027 : mem_out_dec = 6'b111111;
12'd4028 : mem_out_dec = 6'b111111;
12'd4029 : mem_out_dec = 6'b111111;
12'd4030 : mem_out_dec = 6'b111111;
12'd4031 : mem_out_dec = 6'b111111;
12'd4032 : mem_out_dec = 6'b111111;
12'd4033 : mem_out_dec = 6'b111111;
12'd4034 : mem_out_dec = 6'b111111;
12'd4035 : mem_out_dec = 6'b111111;
12'd4036 : mem_out_dec = 6'b111111;
12'd4037 : mem_out_dec = 6'b111111;
12'd4038 : mem_out_dec = 6'b111111;
12'd4039 : mem_out_dec = 6'b111111;
12'd4040 : mem_out_dec = 6'b111111;
12'd4041 : mem_out_dec = 6'b111111;
12'd4042 : mem_out_dec = 6'b111111;
12'd4043 : mem_out_dec = 6'b111111;
12'd4044 : mem_out_dec = 6'b111111;
12'd4045 : mem_out_dec = 6'b111111;
12'd4046 : mem_out_dec = 6'b111111;
12'd4047 : mem_out_dec = 6'b111111;
12'd4048 : mem_out_dec = 6'b111111;
12'd4049 : mem_out_dec = 6'b111111;
12'd4050 : mem_out_dec = 6'b111111;
12'd4051 : mem_out_dec = 6'b111111;
12'd4052 : mem_out_dec = 6'b111111;
12'd4053 : mem_out_dec = 6'b111111;
12'd4054 : mem_out_dec = 6'b111111;
12'd4055 : mem_out_dec = 6'b111111;
12'd4056 : mem_out_dec = 6'b111111;
12'd4057 : mem_out_dec = 6'b111111;
12'd4058 : mem_out_dec = 6'b111111;
12'd4059 : mem_out_dec = 6'b111111;
12'd4060 : mem_out_dec = 6'b111111;
12'd4061 : mem_out_dec = 6'b111111;
12'd4062 : mem_out_dec = 6'b111111;
12'd4063 : mem_out_dec = 6'b111111;
12'd4064 : mem_out_dec = 6'b111111;
12'd4065 : mem_out_dec = 6'b111111;
12'd4066 : mem_out_dec = 6'b111111;
12'd4067 : mem_out_dec = 6'b111111;
12'd4068 : mem_out_dec = 6'b111111;
12'd4069 : mem_out_dec = 6'b111111;
12'd4070 : mem_out_dec = 6'b111111;
12'd4071 : mem_out_dec = 6'b111111;
12'd4072 : mem_out_dec = 6'b111111;
12'd4073 : mem_out_dec = 6'b111111;
12'd4074 : mem_out_dec = 6'b111111;
12'd4075 : mem_out_dec = 6'b111111;
12'd4076 : mem_out_dec = 6'b111111;
12'd4077 : mem_out_dec = 6'b111111;
12'd4078 : mem_out_dec = 6'b111111;
12'd4079 : mem_out_dec = 6'b111111;
12'd4080 : mem_out_dec = 6'b111111;
12'd4081 : mem_out_dec = 6'b111111;
12'd4082 : mem_out_dec = 6'b111111;
12'd4083 : mem_out_dec = 6'b111111;
12'd4084 : mem_out_dec = 6'b111111;
12'd4085 : mem_out_dec = 6'b111111;
12'd4086 : mem_out_dec = 6'b111111;
12'd4087 : mem_out_dec = 6'b111111;
12'd4088 : mem_out_dec = 6'b111111;
12'd4089 : mem_out_dec = 6'b111111;
12'd4090 : mem_out_dec = 6'b111111;
12'd4091 : mem_out_dec = 6'b111111;
12'd4092 : mem_out_dec = 6'b111111;
12'd4093 : mem_out_dec = 6'b111111;
12'd4094 : mem_out_dec = 6'b111111;
12'd4095 : mem_out_dec = 6'b111111;
endcase
end
always @ (posedge clk) begin
dec_cnt <= #TCQ mem_out_dec;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_rdlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling Stage1 calibration logic
// NOTES:
// 1. Window detection with PRBS pattern.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
(* use_dsp48 = "no" *)
module mig_7series_v4_2_ddr_phy_rdlvl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter RANKS = 1, // # of DRAM ranks
parameter PER_BIT_DESKEW = "ON", // Enable per-bit DQ deskew
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF", // Enable debug port
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter OCAL_EN = "ON",
parameter IDELAY_ADJ = "ON",
parameter PI_DIV2_INCDEC = "TRUE"
)
(
input clk,
input rst,
// Calibration status, control signals
input mpr_rdlvl_start,
output mpr_rdlvl_done,
output reg mpr_last_byte_done,
output mpr_rnk_done,
input rdlvl_stg1_start,
output rdlvl_stg1_done /* synthesis syn_maxfan = 30 */,
output rdlvl_stg1_rnk_done,
output reg rdlvl_stg1_err,
output mpr_rdlvl_err,
output rdlvl_err,
output reg rdlvl_prech_req,
output rdlvl_last_byte_done,
output reg rdlvl_assrt_common,
input prech_done,
input phy_if_empty,
input [4:0] idelaye2_init_val,
// Captured data in fabric clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Decrement initial Phaser_IN Fine tap delay
input dqs_po_dec_done,
input [5:0] pi_counter_read_val,
// Stage 1 calibration outputs
output reg pi_fine_dly_dec_done,
output reg pi_en_stg2_f,
output reg pi_stg2_f_incdec,
output reg pi_stg2_load,
output reg [5:0] pi_stg2_reg_l,
output [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt,
// To DQ IDELAY required to find left edge of
// valid window
output idelay_ce,
output idelay_inc,
input idelay_ld,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
// Only output if Per-bit de-skew enabled
output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
//output to prevent read during PI movement
output reg rdlvl_pi_incdec,
// Debug Port
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl
);
// minimum time (in IDELAY taps) for which capture data must be stable for
// algorithm to consider a valid data eye to be found. The read leveling
// logic will ignore any window found smaller than this value. Limitations
// on how small this number can be is determined by: (1) the algorithmic
// limitation of how many taps wide the data eye can be (3 taps), and (2)
// how wide regions of "instability" that occur around the edges of the
// read valid window can be (i.e. need to be able to filter out "false"
// windows that occur for a short # of taps around the edges of the true
// data window, although with multi-sampling during read leveling, this is
// not as much a concern) - the larger the value, the more protection
// against "false" windows
localparam MIN_EYE_SIZE = 16;
// Length of calibration sequence (in # of words)
localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK);
// # of cycles required to perform read data shift register compare
// This is defined as from the cycle the new data is loaded until
// signal found_edge_r is valid
localparam RD_SHIFT_COMP_DELAY = 5;
// worst-case # of cycles to wait to ensure that both the SR and
// PREV_SR shift registers have valid data, and that the comparison
// of the two shift register values is valid. The "+1" at the end of
// this equation is a fudge factor, I freely admit that
localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1;
// # of clock cycles to wait after changing tap value or read data MUX
// to allow: (1) tap chain to settle, (2) for delayed input to propagate
// thru ISERDES, (3) for the read data comparison logic to have time to
// output the comparison of two consecutive samples of the settled read data
// The minimum delay is 16 cycles, which should be good enough to handle all
// three of the above conditions for the simulation-only case with a short
// training pattern. For H/W (or for simulation with longer training
// pattern), it will take longer to store and compare two consecutive
// samples, and the value of this parameter will reflect that
// put the maximum number for 2:1 mode
localparam PIPE_WAIT_CNT = (nCK_PER_CLK == 2) ? 31 : (SR_VALID_DELAY < 8) ? 16
: (SR_VALID_DELAY + 8);
// # of read data samples to examine when detecting whether an edge has
// occured during stage 1 calibration. Width of local param must be
// changed as appropriate. Note that there are two counters used, each
// counter can be changed independently of the other - they are used in
// cascade to create a larger counter
localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF;
localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001; // 12'h1FF Must be > 0
localparam [5:0] CAL1_IDLE = 6'h00;
localparam [5:0] CAL1_NEW_DQS_WAIT = 6'h01;
localparam [5:0] CAL1_STORE_FIRST_WAIT = 6'h02;
localparam [5:0] CAL1_PAT_DETECT = 6'h03;
localparam [5:0] CAL1_DQ_IDEL_TAP_INC = 6'h04;
localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05;
localparam [5:0] CAL1_DQ_IDEL_TAP_DEC = 6'h06;
localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07;
localparam [5:0] CAL1_DETECT_EDGE = 6'h08;
localparam [5:0] CAL1_IDEL_INC_CPT = 6'h09;
localparam [5:0] CAL1_IDEL_INC_CPT_WAIT = 6'h0A;
localparam [5:0] CAL1_CALC_IDEL = 6'h0B;
localparam [5:0] CAL1_IDEL_DEC_CPT = 6'h0C;
localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT = 6'h0D;
localparam [5:0] CAL1_NEXT_DQS = 6'h0E;
localparam [5:0] CAL1_DONE = 6'h0F;
localparam [5:0] CAL1_PB_STORE_FIRST_WAIT = 6'h10;
localparam [5:0] CAL1_PB_DETECT_EDGE = 6'h11;
localparam [5:0] CAL1_PB_INC_CPT = 6'h12;
localparam [5:0] CAL1_PB_INC_CPT_WAIT = 6'h13;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT = 6'h14;
localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15;
localparam [5:0] CAL1_PB_DETECT_EDGE_DQ = 6'h16;
localparam [5:0] CAL1_PB_INC_DQ = 6'h17;
localparam [5:0] CAL1_PB_INC_DQ_WAIT = 6'h18;
localparam [5:0] CAL1_PB_DEC_CPT = 6'h19;
localparam [5:0] CAL1_PB_DEC_CPT_WAIT = 6'h1A;
localparam [5:0] CAL1_REGL_LOAD = 6'h1B;
localparam [5:0] CAL1_RDLVL_ERR = 6'h1C;
localparam [5:0] CAL1_MPR_NEW_DQS_WAIT = 6'h1D;
localparam [5:0] CAL1_VALID_WAIT = 6'h1E;
localparam [5:0] CAL1_MPR_PAT_DETECT = 6'h1F;
localparam [5:0] CAL1_NEW_DQS_PREWAIT = 6'h20;
localparam [5:0] CAL1_RD_STOP_FOR_PI_INC = 6'h21;
localparam [5:0] CAL1_CENTER_WAIT = 6'h22;
integer a;
integer b;
integer d;
integer e;
integer f;
integer h;
integer g;
integer i;
integer j;
integer k;
integer l;
integer m;
integer n;
integer r;
integer p;
integer q;
integer s;
integer t;
integer u;
integer w;
integer ce_i;
integer ce_rnk_i;
integer aa;
integer bb;
integer cc;
integer dd;
genvar x;
genvar z;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_r;
wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing;
reg [DQS_CNT_WIDTH:0] cal1_cnt_cpt_timing_r;
reg cal1_dq_idel_ce;
reg cal1_dq_idel_inc;
reg cal1_dlyce_cpt_r;
reg cal1_dlyinc_cpt_r;
reg cal1_dlyce_dq_r;
reg cal1_dlyinc_dq_r;
reg cal1_wait_cnt_en_r;
reg [4:0] cal1_wait_cnt_r;
reg cal1_wait_r;
reg [DQ_WIDTH-1:0] dlyce_dq_r;
reg dlyinc_dq_r;
reg [4:0] dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1];
reg cal1_prech_req_r;
reg [5:0] cal1_state_r;
reg [5:0] cal1_state_r1;
reg [5:0] cal1_state_r2;
reg [5:0] cal1_state_r3;
reg [5:0] cnt_idel_dec_cpt_r;
reg [3:0] cnt_shift_r;
reg detect_edge_done_r;
reg [5:0] right_edge_taps_r;
reg [5:0] first_edge_taps_r;
reg found_edge_r;
reg found_first_edge_r;
reg found_second_edge_r;
reg found_stable_eye_r;
reg found_stable_eye_last_r;
reg found_edge_all_r;
reg [5:0] tap_cnt_cpt_r;
reg tap_limit_cpt_r;
reg [4:0] idel_tap_cnt_dq_pb_r;
reg idel_tap_limit_dq_pb_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg mux_rd_valid_r;
reg new_cnt_cpt_r;
reg [RD_SHIFT_LEN-1:0] old_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] old_sr_rise3_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] old_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] old_sr_match_rise3_r;
reg [4:0] pb_cnt_eye_size_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] pb_detect_edge_done_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_last_r;
reg [DRAM_WIDTH-1:0] pb_found_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_first_edge_r;
reg [DRAM_WIDTH-1:0] pb_found_stable_eye_r;
reg [DRAM_WIDTH-1:0] pb_last_tap_jitter_r;
reg pi_en_stg2_f_timing;
reg pi_stg2_f_incdec_timing;
reg pi_stg2_load_timing;
reg [5:0] pi_stg2_reg_l_timing;
reg [DRAM_WIDTH-1:0] prev_sr_diff_r;
reg [RD_SHIFT_LEN-1:0] prev_sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] prev_sr_rise3_r [DRAM_WIDTH-1:0];
reg [DRAM_WIDTH-1:0] prev_sr_match_cyc2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise0_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise1_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_fall3_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise2_r;
reg [DRAM_WIDTH-1:0] prev_sr_match_rise3_r;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg samp_cnt_done_r;
reg samp_edge_cnt0_en_r;
reg [11:0] samp_edge_cnt0_r;
reg samp_edge_cnt1_en_r;
reg [11:0] samp_edge_cnt1_r;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg [5:0] second_edge_taps_r;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg store_sr_r;
reg store_sr_req_pulsed_r;
reg store_sr_req_r;
reg sr_valid_r;
reg sr_valid_r1;
reg sr_valid_r2;
reg [DRAM_WIDTH-1:0] old_sr_diff_r;
reg [DRAM_WIDTH-1:0] old_sr_match_cyc2_r;
reg pat0_data_match_r;
reg pat1_data_match_r;
wire pat_data_match_r;
wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0];
reg [DRAM_WIDTH-1:0] pat0_match_fall0_r;
reg pat0_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall1_r;
reg pat0_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall2_r;
reg pat0_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_fall3_r;
reg pat0_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise0_r;
reg pat0_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise1_r;
reg pat0_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise2_r;
reg pat0_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat0_match_rise3_r;
reg pat0_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg pat1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg pat1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall2_r;
reg pat1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall3_r;
reg pat1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg pat1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg pat1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise2_r;
reg pat1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise3_r;
reg pat1_match_rise3_and_r;
reg [4:0] idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w;
reg [4:0] idelay_tap_cnt_slice_r;
reg idelay_tap_limit_r;
wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0];
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise0_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall0_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise1_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall1_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise2_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall2_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_rise3_r;
reg [DRAM_WIDTH-1:0] idel_pat0_match_fall3_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise2_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall2_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_rise3_r;
reg [DRAM_WIDTH-1:0] idel_pat1_match_fall3_r;
reg idel_pat0_match_rise0_and_r;
reg idel_pat0_match_fall0_and_r;
reg idel_pat0_match_rise1_and_r;
reg idel_pat0_match_fall1_and_r;
reg idel_pat0_match_rise2_and_r;
reg idel_pat0_match_fall2_and_r;
reg idel_pat0_match_rise3_and_r;
reg idel_pat0_match_fall3_and_r;
reg idel_pat1_match_rise0_and_r;
reg idel_pat1_match_fall0_and_r;
reg idel_pat1_match_rise1_and_r;
reg idel_pat1_match_fall1_and_r;
reg idel_pat1_match_rise2_and_r;
reg idel_pat1_match_fall2_and_r;
reg idel_pat1_match_rise3_and_r;
reg idel_pat1_match_fall3_and_r;
reg idel_pat0_data_match_r;
reg idel_pat1_data_match_r;
reg idel_pat_data_match;
reg idel_pat_data_match_r;
reg [4:0] idel_dec_cnt;
reg [5:0] rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
reg [1:0] rnk_cnt_r;
reg rdlvl_rank_done_r;
reg [3:0] done_cnt;
reg [1:0] regl_rank_cnt;
reg [DQS_CNT_WIDTH:0] regl_dqs_cnt;
reg [DQS_CNT_WIDTH:0] regl_dqs_cnt_r;
wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing;
reg regl_rank_done_r;
reg rdlvl_stg1_start_r;
reg dqs_po_dec_done_r1;
reg dqs_po_dec_done_r2;
reg fine_dly_dec_done_r1;
reg fine_dly_dec_done_r2;
reg fine_dly_dec_done_r3;
reg fine_dly_dec_done_r4;
reg [3:0] wait_cnt_r;
reg [5:0] pi_rdval_cnt;
reg pi_cnt_dec;
reg mpr_valid_r;
reg mpr_valid_r1;
reg mpr_valid_r2;
reg mpr_rd_rise0_prev_r;
reg mpr_rd_fall0_prev_r;
reg mpr_rd_rise1_prev_r;
reg mpr_rd_fall1_prev_r;
reg mpr_rd_rise2_prev_r;
reg mpr_rd_fall2_prev_r;
reg mpr_rd_rise3_prev_r;
reg mpr_rd_fall3_prev_r;
reg mpr_rdlvl_done_r;
reg mpr_rdlvl_done_r1;
reg mpr_rdlvl_done_r2;
reg mpr_rdlvl_start_r;
reg mpr_rank_done_r;
reg [2:0] stable_idel_cnt;
reg inhibit_edge_detect_r;
reg idel_pat_detect_valid_r;
reg idel_mpr_pat_detect_r;
reg mpr_pat_detect_r;
reg mpr_dec_cpt_r;
reg idel_adj_inc; //IDELAY adjustment
wire [1:0] idelay_adj;
wire pb_detect_edge_setup;
wire pb_detect_edge;
// Debug
reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps;
reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps;
reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w;
reg rdlvl_stg1_done_int;
reg rdlvl_stg1_done_int_r1, rdlvl_stg1_done_int_r2, rdlvl_stg1_done_int_r3;
reg rdlvl_last_byte_done_int;
reg rdlvl_last_byte_done_int_r1, rdlvl_last_byte_done_int_r2, rdlvl_last_byte_done_int_r3;
//IDELAY adjustment setting for -1
//2'b10 : IDELAY - 1
//2'b01 : IDELAY + 1
//2'b00 : No IDELAY adjustment
assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < RANKS; d = d + 1) begin
for (e = 0; e < DQS_WIDTH; e = e + 1) begin
idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e];
dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e];
end
end
end
assign mpr_rdlvl_err = rdlvl_stg1_err & (!mpr_rdlvl_done);
assign rdlvl_err = rdlvl_stg1_err & (mpr_rdlvl_done);
assign dbg_phy_rdlvl[0] = rdlvl_stg1_start;
assign dbg_phy_rdlvl[1] = pat_data_match_r;
assign dbg_phy_rdlvl[2] = mux_rd_valid_r;
assign dbg_phy_rdlvl[3] = idelay_tap_limit_r;
assign dbg_phy_rdlvl[8:4] = 'b0;
assign dbg_phy_rdlvl[14:9] = cal1_state_r[5:0];
assign dbg_phy_rdlvl[20:15] = cnt_idel_dec_cpt_r;
assign dbg_phy_rdlvl[21] = found_first_edge_r;
assign dbg_phy_rdlvl[22] = found_second_edge_r;
assign dbg_phy_rdlvl[23] = found_edge_r;
assign dbg_phy_rdlvl[24] = store_sr_r;
// [40:25] previously used for sr, old_sr shift registers. If connecting
// these signals again, don't forget to parameterize based on RD_SHIFT_LEN
assign dbg_phy_rdlvl[40:25] = 'b0;
assign dbg_phy_rdlvl[41] = sr_valid_r;
assign dbg_phy_rdlvl[42] = found_stable_eye_r;
assign dbg_phy_rdlvl[48:43] = tap_cnt_cpt_r;
assign dbg_phy_rdlvl[54:49] = first_edge_taps_r;
assign dbg_phy_rdlvl[60:55] = second_edge_taps_r;
assign dbg_phy_rdlvl[64:61] = cal1_cnt_cpt_timing_r;
assign dbg_phy_rdlvl[65] = cal1_dlyce_cpt_r;
assign dbg_phy_rdlvl[66] = cal1_dlyinc_cpt_r;
assign dbg_phy_rdlvl[67] = found_edge_r;
assign dbg_phy_rdlvl[68] = found_first_edge_r;
assign dbg_phy_rdlvl[73:69] = 'b0;
assign dbg_phy_rdlvl[74] = idel_pat_data_match;
assign dbg_phy_rdlvl[75] = idel_pat0_data_match_r;
assign dbg_phy_rdlvl[76] = idel_pat1_data_match_r;
assign dbg_phy_rdlvl[77] = pat0_data_match_r;
assign dbg_phy_rdlvl[78] = pat1_data_match_r;
assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w;
assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r;
assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r;
assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r;
assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r;
assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r;
assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r;
assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r;
assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r;
//***************************************************************************
// Debug output
//***************************************************************************
// CPT taps
assign dbg_cpt_first_edge_cnt = dbg_cpt_first_edge_taps;
assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps;
assign dbg_cpt_tap_cnt = dbg_cpt_tap_cnt_w;
assign dbg_dq_idelay_tap_cnt = idelay_tap_cnt_w;
// Record first and second edges found during CPT calibration
generate
always @(posedge clk)
if (rst || (rdlvl_stg1_start && ~rdlvl_stg1_start_r)) begin
dbg_cpt_first_edge_taps <= #TCQ 'b0;
dbg_cpt_second_edge_taps <= #TCQ 'b0;
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin
//for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk
for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge
if (found_first_edge_r)
dbg_cpt_first_edge_taps[(6*ce_i)+:6]
<= #TCQ first_edge_taps_r;
if (found_second_edge_r)
dbg_cpt_second_edge_taps[(6*ce_i)+:6]
<= #TCQ second_edge_taps_r;
end
//end
end else if (cal1_state_r == CAL1_CALC_IDEL) begin
// Record tap counts of first and second edge edges during
// CPT calibration for each DQS group. If neither edge has
// been found, then those taps will remain 0
if (found_first_edge_r)
dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]
<= #TCQ first_edge_taps_r;
if (found_second_edge_r)
dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]
<= #TCQ second_edge_taps_r;
end
endgenerate
assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r;
assign mpr_rnk_done = mpr_rank_done_r;
assign mpr_rdlvl_done = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE")
mpr_rdlvl_done_r : 1'b1;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
assign pi_stg2_rdlvl_cnt = (((PI_DIV2_INCDEC == "TRUE") && (cal1_state_r3 == CAL1_REGL_LOAD)) || ((PI_DIV2_INCDEC == "FALSE") && (cal1_state_r == CAL1_REGL_LOAD))) ? regl_dqs_cnt_r : cal1_cnt_cpt_r;
assign rdlvl_stg1_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_stg1_done_int_r3 : rdlvl_stg1_done_int;
assign rdlvl_last_byte_done = (PI_DIV2_INCDEC == "TRUE") ? rdlvl_last_byte_done_int_r3 : rdlvl_last_byte_done_int;
always @ (posedge clk) begin
rdlvl_stg1_done_int_r1 <= #TCQ rdlvl_stg1_done_int;
rdlvl_stg1_done_int_r2 <= #TCQ rdlvl_stg1_done_int_r1;
rdlvl_stg1_done_int_r3 <= #TCQ rdlvl_stg1_done_int_r2;
rdlvl_last_byte_done_int_r1 <= #TCQ rdlvl_last_byte_done_int;
rdlvl_last_byte_done_int_r2 <= #TCQ rdlvl_last_byte_done_int_r1;
rdlvl_last_byte_done_int_r3 <= #TCQ rdlvl_last_byte_done_int_r2;
end
assign idelay_ce = cal1_dq_idel_ce;
assign idelay_inc = cal1_dq_idel_inc;
//***************************************************************************
// Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all
// DQs simultaneously
//***************************************************************************
always @(posedge clk) begin
if (rst)
rdlvl_assrt_common <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start &
!rdlvl_stg1_start_r)
rdlvl_assrt_common <= #TCQ 1'b1;
else if (!idel_pat_data_match_r & idel_pat_data_match)
rdlvl_assrt_common <= #TCQ 1'b0;
end
//***************************************************************************
// Data mux to route appropriate bit to calibration logic - i.e. calibration
// is done sequentially, one bit (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else begin: rd_data_div2_logic_clk
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r +
mux_i];
end
end
endgenerate
//***************************************************************************
// MPR Read Leveling
//***************************************************************************
// storing the previous read data for checking later. Only bit 0 is used
// since MPR contents (01010101) are available generally on DQ[0] per
// JEDEC spec.
always @(posedge clk)begin
if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin
mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0];
mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0];
mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0];
mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0];
mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0];
mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0];
mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0];
mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0];
end
end
generate
if (nCK_PER_CLK == 4) begin: mpr_4to1
// changed stable count of 2 IDELAY taps at 78 ps resolution
always @(posedge clk) begin
if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) |
//(cal1_state_r == CAL1_DETECT_EDGE) |
(mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) |
(mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) |
(mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) |
(mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) |
(mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))
stable_idel_cnt <= #TCQ 3'd0;
else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) &
((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idel_pat_detect_valid_r))) begin
if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
(mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
(mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
(mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
(mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) &
(mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) &
(mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) &
(mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) &
(stable_idel_cnt < 3'd2))
stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
end
end
always @(posedge clk) begin
if (rst |
(mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r))
inhibit_edge_detect_r <= 1'b1;
// Wait for settling time after idelay tap increment before
// de-asserting inhibit_edge_detect_r
else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
(~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r))
inhibit_edge_detect_r <= 1'b0;
end
//checking for transition from 01010101 to 10101010
always @(posedge clk)begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
inhibit_edge_detect_r)
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 10101010 is not the correct pattern
else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) ||
((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
&& (idel_pat_detect_valid_r)))
//|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 01010101 to 10101010 is the correct transition
else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) &
(stable_idel_cnt == 3'd2) &
((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) ||
(mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) ||
(mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) ||
(mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) ||
(mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])))
idel_mpr_pat_detect_r <= #TCQ 1'b1;
end
end else if (nCK_PER_CLK == 2) begin: mpr_2to1
// changed stable count of 2 IDELAY taps at 78 ps resolution
always @(posedge clk) begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
(mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))
stable_idel_cnt <= #TCQ 3'd0;
else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) &
((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idel_pat_detect_valid_r))) begin
if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
(mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
(mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
(mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
(stable_idel_cnt < 3'd2))
stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
end
end
always @(posedge clk) begin
if (rst |
(mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r))
inhibit_edge_detect_r <= 1'b1;
else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
(~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r))
inhibit_edge_detect_r <= 1'b0;
end
//checking for transition from 01010101 to 10101010
always @(posedge clk)begin
if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
inhibit_edge_detect_r)
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 1010 is not the correct pattern
else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) ||
((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
& (idel_pat_detect_valid_r)))
// ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
idel_mpr_pat_detect_r <= #TCQ 1'b0;
// 0101 to 1010 is the correct transition
else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) &
(stable_idel_cnt == 3'd2) &
((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
(mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
(mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
(mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])))
idel_mpr_pat_detect_r <= #TCQ 1'b1;
end
end
endgenerate
// Registered signal indicates when mux_rd_rise/fall_r is valid
always @(posedge clk)
mux_rd_valid_r <= #TCQ ~phy_if_empty;
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// read calibration
//***************************************************************************
always @(posedge clk) begin
dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done;
dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;
fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;
fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2;
fine_dly_dec_done_r4 <= #TCQ fine_dly_dec_done_r3;
if (PI_DIV2_INCDEC == "TRUE")
pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r4;
else
pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2;
end
always @(posedge clk) begin
if (rst || pi_cnt_dec)
wait_cnt_r <= #TCQ 'd8;
else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0))
wait_cnt_r <= #TCQ wait_cnt_r - 1;
end
always @(posedge clk) begin
if (rst) begin
pi_rdval_cnt <= #TCQ 'd0;
end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin
pi_rdval_cnt <= #TCQ pi_counter_read_val;
end else if (pi_rdval_cnt > 'd0) begin
if (pi_cnt_dec)
pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1;
else
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end else if (pi_rdval_cnt == 'd0) begin
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (pi_rdval_cnt == 'd0))
pi_cnt_dec <= #TCQ 1'b0;
else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)
&& (wait_cnt_r == 'd1))
pi_cnt_dec <= #TCQ 1'b1;
else
pi_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst) begin
fine_dly_dec_done_r1 <= #TCQ 1'b0;
end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||
(dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin
fine_dly_dec_done_r1 <= #TCQ 1'b1;
end
end
//***************************************************************************
// Demultiplexor to control Phaser_IN delay values
//***************************************************************************
// Read DQS
always @(posedge clk) begin
if (rst) begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (pi_cnt_dec) begin
pi_en_stg2_f_timing <= #TCQ 'b1;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end else if (cal1_dlyce_cpt_r) begin
if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
// Change only specified DQS
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
// if simulating, and "shortcuts" for calibration enabled, apply
// results to all DQSs (i.e. assume same delay on all
// DQSs).
pi_en_stg2_f_timing <= #TCQ 1'b1;
pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
end
end else begin
pi_en_stg2_f_timing <= #TCQ 'b0;
pi_stg2_f_incdec_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_en_stg2_f <= #TCQ pi_en_stg2_f_timing;
pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
end
// This counter used to implement settling time between
// Phaser_IN rank register loads to different DQSs
always @(posedge clk) begin
if (rst)
done_cnt <= #TCQ 'b0;
else if (((cal1_state_r == CAL1_REGL_LOAD) &&
(cal1_state_r1 == CAL1_NEXT_DQS)) ||
((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE)))
done_cnt <= #TCQ 4'b1010;
else if (done_cnt > 'b0)
done_cnt <= #TCQ done_cnt - 1;
end
// During rank register loading the rank count must be sent to
// Phaser_IN via the phy_ctl_wd?? If so phy_init will have to
// issue NOPs during rank register loading with the appropriate
// rank count
always @(posedge clk) begin
if (rst || (regl_rank_done_r == 1'b1))
regl_rank_done_r <= #TCQ 1'b0;
else if ((regl_dqs_cnt == DQS_WIDTH-1) &&
(regl_rank_cnt != RANKS-1) &&
(done_cnt == 4'd1))
regl_rank_done_r <= #TCQ 1'b1;
end
// Temp wire for timing.
// The following in the always block below causes timing issues
// due to DSP block inference
// 6*regl_dqs_cnt.
// replacing this with two left shifts + 1 left shift to avoid
// DSP multiplier.
assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt};
// Load Phaser_OUT rank register with rdlvl delay value
// for each DQS per rank.
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0)) begin
pi_stg2_load_timing <= #TCQ 'b0;
pi_stg2_reg_l_timing <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
pi_stg2_load_timing <= #TCQ 'b1;
pi_stg2_reg_l_timing <= #TCQ
rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt];
end else begin
pi_stg2_load_timing <= #TCQ 'b0;
pi_stg2_reg_l_timing <= #TCQ 'b0;
end
end
// registered for timing
always @(posedge clk) begin
pi_stg2_load <= #TCQ pi_stg2_load_timing;
pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing;
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
regl_rank_cnt <= #TCQ 2'b00;
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_rank_cnt <= #TCQ regl_rank_cnt;
else
regl_rank_cnt <= #TCQ regl_rank_cnt + 1;
end
end
always @(posedge clk) begin
if (rst || (done_cnt == 4'd0) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
regl_dqs_cnt <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
else if ((cal1_state_r == CAL1_REGL_LOAD) &&
(regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
if (regl_rank_cnt == RANKS-1)
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
else
regl_dqs_cnt <= #TCQ 'b0;
end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1)
&& (done_cnt == 4'd1))
regl_dqs_cnt <= #TCQ regl_dqs_cnt + 1;
else
regl_dqs_cnt <= #TCQ regl_dqs_cnt;
end
always @(posedge clk)
regl_dqs_cnt_r <= #TCQ regl_dqs_cnt;
//*****************************************************************
// DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC:
// The actual IDELAY elements for each of the DQ bits is set via the
// DLYVAL parallel load port. However, the stage 1 calibration
// algorithm (well most of it) only needs to increment or decrement the DQ
// IDELAY value by 1 at any one time.
//*****************************************************************
// Chip-select generation for each of the individual counters tracking
// IDELAY tap values for each DQ
generate
for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq
always @(posedge clk)
if (rst)
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skipping calibration altogether (only for simulation), no
// need to set DQ IODELAY values - they are hardcoded
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
else if (SIM_CAL_OPTION == "FAST_CAL") begin
// If fast calibration option (simulation only) selected, DQ
// IODELAYs across all bytes are updated simultaneously
// (although per-bit deskew within DQS[0] is still supported)
for (h = 0; h < DRAM_WIDTH; h = h + 1) begin
dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r;
end
end else if ((SIM_CAL_OPTION == "NONE") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
if (cal1_cnt_cpt_r == z) begin
for (g = 0; g < DRAM_WIDTH; g = g + 1) begin
dlyce_dq_r[DRAM_WIDTH*z + g]
<= #TCQ cal1_dlyce_dq_r;
end
end else
dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
end
end
endgenerate
// Also delay increment/decrement control to match delay on DLYCE
always @(posedge clk)
if (rst)
dlyinc_dq_r <= #TCQ 1'b0;
else
dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r;
// Each DQ has a counter associated with it to record current read-leveling
// delay value
always @(posedge clk)
// Reset or skipping calibration all together
if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin
for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r
for (bb = 0; bb < DQ_WIDTH; bb = bb + 1)
dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0;
end
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk
for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg
if (dlyce_dq_r[r]) begin
if (dlyinc_dq_r)
dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01;
else
dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01;
end
end
end
end else begin
if (dlyce_dq_r[cal1_cnt_cpt_r]) begin
if (dlyinc_dq_r)
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01;
else
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01;
end
end
// Register for timing (help with logic placement)
always @(posedge clk) begin
for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn
for (dd = 0; dd < DQ_WIDTH; dd = dd + 1)
dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd];
end
end
//***************************************************************************
// Generate signal used to delay calibration state machine - used when:
// (1) IDELAY value changed
// (2) RD_MUX_SEL value changed
// Use when a delay is necessary to give the change time to propagate
// through the data pipeline (through IDELAY and ISERDES, and fabric
// pipeline stages)
//***************************************************************************
// List all the stage 1 calibration wait states here.
// verilint STARC-2.7.3.3b off
always @(posedge clk)
if ((cal1_state_r == CAL1_NEW_DQS_WAIT) ||
(cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
(cal1_state_r == CAL1_NEW_DQS_PREWAIT) ||
(cal1_state_r == CAL1_VALID_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_INC_CPT_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||
(cal1_state_r == CAL1_PB_INC_DQ_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_WAIT) ||
(cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) ||
(cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) ||
(cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) ||
(cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT) ||
(cal1_state_r == CAL1_CENTER_WAIT) ||
(cal1_state_r == CAL1_RD_STOP_FOR_PI_INC))
cal1_wait_cnt_en_r <= #TCQ 1'b1;
else
cal1_wait_cnt_en_r <= #TCQ 1'b0;
// verilint STARC-2.7.3.3b on
always @(posedge clk)
if (!cal1_wait_cnt_en_r) begin
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b1;
end else begin
if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin
cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1;
cal1_wait_r <= #TCQ 1'b1;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
cal1_wait_cnt_r <= #TCQ 5'b00000;
cal1_wait_r <= #TCQ 1'b0;
end
end
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
rdlvl_prech_req <= #TCQ 1'b0;
else
rdlvl_prech_req <= #TCQ cal1_prech_req_r;
//***************************************************************************
// Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of
// data from ISERDES. The value of this register is also stored, so that
// previous and current values of the ISERDES data can be compared while
// varying the IODELAY taps to see if an "edge" of the data valid window
// has been encountered since the last IODELAY tap adjustment
//***************************************************************************
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end
end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall1_r[rd_i]};
sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise2_r[rd_i]};
sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall2_r[rd_i]};
sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise3_r[rd_i]};
sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall3_r[rd_i]};
end
end
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]};
end
end
end
end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
if (mux_rd_valid_r) begin
sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise0_r[rd_i]};
sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall0_r[rd_i]};
sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_rise1_r[rd_i]};
sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
mux_rd_fall1_r[rd_i]};
end
end
end
end
end
endgenerate
//***************************************************************************
// Conversion to pattern calibration
//***************************************************************************
// Pattern for DQ IDELAY calibration
//*****************************************************************
// Expected data pattern when DQ shifted to the right such that
// DQS before the left edge of the DVW:
// Based on pattern of ({rise,fall}) =
// 0x1, 0xB, 0x4, 0x4, 0xB, 0x9
// Each nibble will look like:
// bit3: 0, 1, 0, 0, 1, 1
// bit2: 0, 0, 1, 1, 0, 0
// bit1: 0, 1, 0, 0, 1, 0
// bit0: 1, 1, 0, 0, 1, 1
// Or if the write is early it could look like:
// 0x4, 0x4, 0xB, 0x9, 0x6, 0xE
// bit3: 0, 0, 1, 1, 0, 1
// bit2: 1, 1, 0, 0, 1, 1
// bit1: 0, 0, 1, 0, 1, 1
// bit0: 0, 0, 1, 1, 0, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// Pattern for DQ IDELAY increment
// Target pattern for "early write"
assign {idel_pat0_rise0[3], idel_pat0_rise0[2],
idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1;
assign {idel_pat0_fall0[3], idel_pat0_fall0[2],
idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7;
assign {idel_pat0_rise1[3], idel_pat0_rise1[2],
idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE;
assign {idel_pat0_fall1[3], idel_pat0_fall1[2],
idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC;
assign {idel_pat0_rise2[3], idel_pat0_rise2[2],
idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9;
assign {idel_pat0_fall2[3], idel_pat0_fall2[2],
idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2;
assign {idel_pat0_rise3[3], idel_pat0_rise3[2],
idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4;
assign {idel_pat0_fall3[3], idel_pat0_fall3[2],
idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB;
// Target pattern for "on-time write"
assign {idel_pat1_rise0[3], idel_pat1_rise0[2],
idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4;
assign {idel_pat1_fall0[3], idel_pat1_fall0[2],
idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9;
assign {idel_pat1_rise1[3], idel_pat1_rise1[2],
idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3;
assign {idel_pat1_fall1[3], idel_pat1_fall1[2],
idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7;
assign {idel_pat1_rise2[3], idel_pat1_rise2[2],
idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE;
assign {idel_pat1_fall2[3], idel_pat1_fall2[2],
idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC;
assign {idel_pat1_rise3[3], idel_pat1_rise3[2],
idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9;
assign {idel_pat1_fall3[3], idel_pat1_fall3[2],
idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2;
// Correct data valid window for "early write"
assign {pat0_rise0[3], pat0_rise0[2],
pat0_rise0[1], pat0_rise0[0]} = 4'h7;
assign {pat0_fall0[3], pat0_fall0[2],
pat0_fall0[1], pat0_fall0[0]} = 4'hE;
assign {pat0_rise1[3], pat0_rise1[2],
pat0_rise1[1], pat0_rise1[0]} = 4'hC;
assign {pat0_fall1[3], pat0_fall1[2],
pat0_fall1[1], pat0_fall1[0]} = 4'h9;
assign {pat0_rise2[3], pat0_rise2[2],
pat0_rise2[1], pat0_rise2[0]} = 4'h2;
assign {pat0_fall2[3], pat0_fall2[2],
pat0_fall2[1], pat0_fall2[0]} = 4'h4;
assign {pat0_rise3[3], pat0_rise3[2],
pat0_rise3[1], pat0_rise3[0]} = 4'hB;
assign {pat0_fall3[3], pat0_fall3[2],
pat0_fall3[1], pat0_fall3[0]} = 4'h1;
// Correct data valid window for "on-time write"
assign {pat1_rise0[3], pat1_rise0[2],
pat1_rise0[1], pat1_rise0[0]} = 4'h9;
assign {pat1_fall0[3], pat1_fall0[2],
pat1_fall0[1], pat1_fall0[0]} = 4'h3;
assign {pat1_rise1[3], pat1_rise1[2],
pat1_rise1[1], pat1_rise1[0]} = 4'h7;
assign {pat1_fall1[3], pat1_fall1[2],
pat1_fall1[1], pat1_fall1[0]} = 4'hE;
assign {pat1_rise2[3], pat1_rise2[2],
pat1_rise2[1], pat1_rise2[0]} = 4'hC;
assign {pat1_fall2[3], pat1_fall2[2],
pat1_fall2[1], pat1_fall2[0]} = 4'h9;
assign {pat1_rise3[3], pat1_rise3[2],
pat1_rise3[1], pat1_rise3[0]} = 4'h2;
assign {pat1_fall3[3], pat1_fall3[2],
pat1_fall3[1], pat1_fall3[0]} = 4'h4;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// Pattern for DQ IDELAY increment
// Target pattern for "early write"
assign idel_pat0_rise0[3] = 2'b01;
assign idel_pat0_fall0[3] = 2'b00;
assign idel_pat0_rise1[3] = 2'b10;
assign idel_pat0_fall1[3] = 2'b11;
assign idel_pat0_rise0[2] = 2'b00;
assign idel_pat0_fall0[2] = 2'b10;
assign idel_pat0_rise1[2] = 2'b11;
assign idel_pat0_fall1[2] = 2'b10;
assign idel_pat0_rise0[1] = 2'b00;
assign idel_pat0_fall0[1] = 2'b11;
assign idel_pat0_rise1[1] = 2'b10;
assign idel_pat0_fall1[1] = 2'b01;
assign idel_pat0_rise0[0] = 2'b11;
assign idel_pat0_fall0[0] = 2'b10;
assign idel_pat0_rise1[0] = 2'b00;
assign idel_pat0_fall1[0] = 2'b01;
// Target pattern for "on-time write"
assign idel_pat1_rise0[3] = 2'b01;
assign idel_pat1_fall0[3] = 2'b11;
assign idel_pat1_rise1[3] = 2'b01;
assign idel_pat1_fall1[3] = 2'b00;
assign idel_pat1_rise0[2] = 2'b11;
assign idel_pat1_fall0[2] = 2'b01;
assign idel_pat1_rise1[2] = 2'b00;
assign idel_pat1_fall1[2] = 2'b10;
assign idel_pat1_rise0[1] = 2'b01;
assign idel_pat1_fall0[1] = 2'b00;
assign idel_pat1_rise1[1] = 2'b10;
assign idel_pat1_fall1[1] = 2'b11;
assign idel_pat1_rise0[0] = 2'b00;
assign idel_pat1_fall0[0] = 2'b10;
assign idel_pat1_rise1[0] = 2'b11;
assign idel_pat1_fall1[0] = 2'b10;
// Correct data valid window for "early write"
assign pat0_rise0[3] = 2'b00;
assign pat0_fall0[3] = 2'b10;
assign pat0_rise1[3] = 2'b11;
assign pat0_fall1[3] = 2'b10;
assign pat0_rise0[2] = 2'b10;
assign pat0_fall0[2] = 2'b11;
assign pat0_rise1[2] = 2'b10;
assign pat0_fall1[2] = 2'b00;
assign pat0_rise0[1] = 2'b11;
assign pat0_fall0[1] = 2'b10;
assign pat0_rise1[1] = 2'b01;
assign pat0_fall1[1] = 2'b00;
assign pat0_rise0[0] = 2'b10;
assign pat0_fall0[0] = 2'b00;
assign pat0_rise1[0] = 2'b01;
assign pat0_fall1[0] = 2'b11;
// Correct data valid window for "on-time write"
assign pat1_rise0[3] = 2'b11;
assign pat1_fall0[3] = 2'b01;
assign pat1_rise1[3] = 2'b00;
assign pat1_fall1[3] = 2'b10;
assign pat1_rise0[2] = 2'b01;
assign pat1_fall0[2] = 2'b00;
assign pat1_rise1[2] = 2'b10;
assign pat1_fall1[2] = 2'b11;
assign pat1_rise0[1] = 2'b00;
assign pat1_fall0[1] = 2'b10;
assign pat1_rise1[1] = 2'b11;
assign pat1_fall1[1] = 2'b10;
assign pat1_rise0[0] = 2'b10;
assign pat1_fall0[0] = 2'b11;
assign pat1_rise1[0] = 2'b10;
assign pat1_fall1[0] = 2'b00;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
// DQ IDELAY pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4])
idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4])
idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4])
idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4])
idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4])
idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4])
idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4])
idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4])
idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
// DQS DVW pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4])
pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4])
pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4])
pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4])
pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4])
pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4])
pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4])
pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4])
pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
// Combine pattern match "subterms" for DQ-IDELAY stage
always @(posedge clk) begin
idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r;
idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r;
idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r;
idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r;
idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
idel_pat0_match_fall0_and_r &&
idel_pat0_match_rise1_and_r &&
idel_pat0_match_fall1_and_r &&
idel_pat0_match_rise2_and_r &&
idel_pat0_match_fall2_and_r &&
idel_pat0_match_rise3_and_r &&
idel_pat0_match_fall3_and_r);
end
always @(posedge clk) begin
idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r;
idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r;
idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r;
idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r;
idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
idel_pat1_match_fall0_and_r &&
idel_pat1_match_rise1_and_r &&
idel_pat1_match_fall1_and_r &&
idel_pat1_match_rise2_and_r &&
idel_pat1_match_fall2_and_r &&
idel_pat1_match_rise3_and_r &&
idel_pat1_match_fall3_and_r);
end
always @(*)
idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
idel_pat1_data_match_r;
always @(posedge clk)
idel_pat_data_match_r <= #TCQ idel_pat_data_match;
// Combine pattern match "subterms" for DQS-PHASER_IN stage
always @(posedge clk) begin
pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r;
pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r;
pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r;
pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r;
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r &&
pat0_match_rise2_and_r &&
pat0_match_fall2_and_r &&
pat0_match_rise3_and_r &&
pat0_match_fall3_and_r);
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r;
pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r;
pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r;
pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r &&
pat1_match_rise2_and_r &&
pat1_match_fall2_and_r &&
pat1_match_rise3_and_r &&
pat1_match_fall3_and_r);
end
assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
// DQ IDELAY pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// DQS DVW pattern detection
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
// Combine pattern match "subterms" for DQ-IDELAY stage
always @(posedge clk) begin
idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
idel_pat0_match_fall0_and_r &&
idel_pat0_match_rise1_and_r &&
idel_pat0_match_fall1_and_r);
end
always @(posedge clk) begin
idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
idel_pat1_match_fall0_and_r &&
idel_pat1_match_rise1_and_r &&
idel_pat1_match_fall1_and_r);
end
always @(posedge clk) begin
if (sr_valid_r2)
idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
idel_pat1_data_match_r;
end
//assign idel_pat_data_match = idel_pat0_data_match_r |
// idel_pat1_data_match_r;
always @(posedge clk)
idel_pat_data_match_r <= #TCQ idel_pat_data_match;
// Combine pattern match "subterms" for DQS-PHASER_IN stage
always @(posedge clk) begin
pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
pat0_match_fall0_and_r &&
pat0_match_rise1_and_r &&
pat0_match_fall1_and_r);
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
end
assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
end
endgenerate
always @(posedge clk) begin
rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start;
mpr_rdlvl_done_r1 <= #TCQ mpr_rdlvl_done_r;
mpr_rdlvl_done_r2 <= #TCQ mpr_rdlvl_done_r1;
mpr_rdlvl_start_r <= #TCQ mpr_rdlvl_start;
end
//***************************************************************************
// First stage calibration: Capture clock
//***************************************************************************
//*****************************************************************
// Keep track of how many samples have been written to shift registers
// Every time RD_SHIFT_LEN samples have been written, then we have a
// full read training pattern loaded into the sr_* registers. Then assert
// sr_valid_r to indicate that: (1) comparison between the sr_* and
// old_sr_* and prev_sr_* registers can take place, (2) transfer of
// the contents of sr_* to old_sr_* and prev_sr_* registers can also
// take place
//*****************************************************************
// verilint STARC-2.2.3.3 off
always @(posedge clk)
if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin
cnt_shift_r <= #TCQ 'b1;
sr_valid_r <= #TCQ 1'b0;
mpr_valid_r <= #TCQ 1'b0;
end else begin
if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin
if (cnt_shift_r == 'b0)
mpr_valid_r <= #TCQ 1'b1;
else begin
mpr_valid_r <= #TCQ 1'b0;
cnt_shift_r <= #TCQ cnt_shift_r + 1;
end
end else
mpr_valid_r <= #TCQ 1'b0;
if (mux_rd_valid_r && rdlvl_stg1_start) begin
if (cnt_shift_r == RD_SHIFT_LEN-1) begin
sr_valid_r <= #TCQ 1'b1;
cnt_shift_r <= #TCQ 'b0;
end else begin
sr_valid_r <= #TCQ 1'b0;
cnt_shift_r <= #TCQ cnt_shift_r + 1;
end
end else
// When the current mux_rd_* contents are not valid, then
// retain the current value of cnt_shift_r, and make sure
// that sr_valid_r = 0 to prevent any downstream loads or
// comparisons
sr_valid_r <= #TCQ 1'b0;
end
// verilint STARC-2.2.3.3 on
//*****************************************************************
// Logic to determine when either edge of the data eye encountered
// Pre- and post-IDELAY update data pattern is compared, if they
// differ, than an edge has been encountered. Currently no attempt
// made to determine if the data pattern itself is "correct", only
// whether it changes after incrementing the IDELAY (possible
// future enhancement)
//*****************************************************************
// One-way control for ensuring that state machine request to store
// current read data into OLD SR shift register only occurs on a
// valid clock cycle. The FSM provides a one-cycle request pulse.
// It is the responsibility of the FSM to wait the worst-case time
// before relying on any downstream results of this load.
always @(posedge clk)
if (rst)
store_sr_r <= #TCQ 1'b0;
else begin
if (store_sr_req_r)
store_sr_r <= #TCQ 1'b1;
else if ((sr_valid_r || mpr_valid_r) && store_sr_r)
store_sr_r <= #TCQ 1'b0;
end
// Transfer current data to old data, prior to incrementing delay
// Also store data from current sampling window - so that we can detect
// if the current delay tap yields data that is "jittery"
generate
if (nCK_PER_CLK == 4) begin: gen_old_sr_div4
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
always @(posedge clk) begin
if (sr_valid_r || mpr_valid_r) begin
// Load last sample (i.e. from current sampling interval)
prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
end
end
end
end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
always @(posedge clk) begin
if (sr_valid_r || mpr_valid_r) begin
prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
end
if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
end
end
end
end
endgenerate
//*******************************************************
// Match determination occurs over 3 cycles - pipelined for better timing
//*******************************************************
// Match valid with # of cycles of pipelining in match determination
always @(posedge clk) begin
sr_valid_r1 <= #TCQ sr_valid_r;
sr_valid_r2 <= #TCQ sr_valid_r1;
mpr_valid_r1 <= #TCQ mpr_valid_r;
mpr_valid_r2 <= #TCQ mpr_valid_r1;
end
generate
if (nCK_PER_CLK == 4) begin: gen_sr_match_div4
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
always @(posedge clk) begin
// CYCLE1: Compare all bits in DQS grp, generate separate term for
// each bit over four bit times. For example, if there are 8-bits
// per DQS group, 32 terms are generated on cycle 1
// NOTE: Structure HDL such that X on data bus will result in a
// mismatch. This is required for memory models that can drive the
// bus with X's to model uncertainty regions (e.g. Denali)
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
old_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
else
old_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
old_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
else
old_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
old_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
else
old_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
old_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
else
old_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z]))
old_sr_match_rise2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z];
else
old_sr_match_rise2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z]))
old_sr_match_fall2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z];
else
old_sr_match_fall2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z]))
old_sr_match_rise3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z];
else
old_sr_match_rise3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z]))
old_sr_match_fall3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z];
else
old_sr_match_fall3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
else
prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
else
prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
else
prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
else
prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z]))
prev_sr_match_rise2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z];
else
prev_sr_match_rise2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z]))
prev_sr_match_fall2_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z];
else
prev_sr_match_fall2_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z]))
prev_sr_match_rise3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z];
else
prev_sr_match_rise3_r[z] <= #TCQ 1'b0;
if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z]))
prev_sr_match_fall3_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z];
else
prev_sr_match_fall3_r[z] <= #TCQ 1'b0;
// CYCLE2: Combine all the comparisons for every 8 words (rise0,
// fall0,rise1, fall1) in the calibration sequence. Now we're down
// to DRAM_WIDTH terms
old_sr_match_cyc2_r[z] <= #TCQ
old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_fall1_r[z] &
old_sr_match_rise2_r[z] &
old_sr_match_fall2_r[z] &
old_sr_match_rise3_r[z] &
old_sr_match_fall3_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ
prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_fall1_r[z] &
prev_sr_match_rise2_r[z] &
prev_sr_match_fall2_r[z] &
prev_sr_match_rise3_r[z] &
prev_sr_match_fall3_r[z];
// CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
// and qualify with pipelined valid signal) - probably don't need
// a cycle just do do this....
if (sr_valid_r2 || mpr_valid_r2) begin
old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];
prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
end else begin
old_sr_diff_r[z] <= #TCQ 'b0;
prev_sr_diff_r[z] <= #TCQ 'b0;
end
end
end
end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
always @(posedge clk) begin
if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
old_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
else
old_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
old_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
else
old_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
old_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
else
old_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
old_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
else
old_sr_match_fall1_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
else
prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
else
prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
else
prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
if ((sr_valid_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
else
prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
old_sr_match_cyc2_r[z] <= #TCQ
old_sr_match_rise0_r[z] &
old_sr_match_fall0_r[z] &
old_sr_match_rise1_r[z] &
old_sr_match_fall1_r[z];
prev_sr_match_cyc2_r[z] <= #TCQ
prev_sr_match_rise0_r[z] &
prev_sr_match_fall0_r[z] &
prev_sr_match_rise1_r[z] &
prev_sr_match_fall1_r[z];
// CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
// and qualify with pipelined valid signal) - probably don't need
// a cycle just do do this....
if (sr_valid_r2 || mpr_valid_r2) begin
old_sr_diff_r[z] <= #TCQ ~old_sr_match_cyc2_r[z];
prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
end else begin
old_sr_diff_r[z] <= #TCQ 'b0;
prev_sr_diff_r[z] <= #TCQ 'b0;
end
end
end
end
endgenerate
//***************************************************************************
// First stage calibration: DQS Capture
//***************************************************************************
//*******************************************************
// Counters for tracking # of samples compared
// For each comparision point (i.e. to determine if an edge has
// occurred after each IODELAY increment when read leveling),
// multiple samples are compared in order to average out the effects
// of jitter. If any one of these samples is different than the "old"
// sample corresponding to the previous IODELAY value, then an edge
// is declared to be detected.
//*******************************************************
// Two cascaded counters are used to keep track of # of samples compared,
// in order to make it easier to meeting timing on these paths. Once
// optimal sampling interval is determined, it may be possible to remove
// the second counter
always @(posedge clk)
samp_edge_cnt0_en_r <= #TCQ
(cal1_state_r == CAL1_PAT_DETECT) ||
(cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
// First counter counts # of samples compared
always @(posedge clk)
if (rst)
samp_edge_cnt0_r <= #TCQ 'b0;
else begin
if (!samp_edge_cnt0_en_r)
// Reset sample counter when not in any of the "sampling" states
samp_edge_cnt0_r <= #TCQ 'b0;
else if (sr_valid_r2 || mpr_valid_r2)
// Otherwise, count # of samples compared
samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1;
end
// Counter #2 enable generation
always @(posedge clk)
if (rst)
samp_edge_cnt1_en_r <= #TCQ 1'b0;
else begin
// Assert pulse when correct number of samples compared
if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) &&
(sr_valid_r2 || mpr_valid_r2))
samp_edge_cnt1_en_r <= #TCQ 1'b1;
else
samp_edge_cnt1_en_r <= #TCQ 1'b0;
end
// Counter #2
always @(posedge clk)
if (rst)
samp_edge_cnt1_r <= #TCQ 'b0;
else
if (!samp_edge_cnt0_en_r)
samp_edge_cnt1_r <= #TCQ 'b0;
else if (samp_edge_cnt1_en_r)
samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1;
always @(posedge clk)
if (rst)
samp_cnt_done_r <= #TCQ 1'b0;
else begin
if (!samp_edge_cnt0_en_r)
samp_cnt_done_r <= #TCQ 'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") ||
(SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
if (samp_edge_cnt0_r == SR_VALID_DELAY-1)
// For simulation only, stay in edge detection mode a minimum
// amount of time - just enough for two data compares to finish
samp_cnt_done_r <= #TCQ 1'b1;
end else begin
if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1)
samp_cnt_done_r <= #TCQ 1'b1;
end
end
//*****************************************************************
// Logic to keep track of (on per-bit basis):
// 1. When a region of stability preceded by a known edge occurs
// 2. If for the current tap, the read data jitters
// 3. If an edge occured between the current and previous tap
// 4. When the current edge detection/sampling interval can end
// Essentially, these are a series of status bits - the stage 1
// calibration FSM monitors these to determine when an edge is
// found. Additional information is provided to help the FSM
// determine if a left or right edge has been found.
//****************************************************************
assign pb_detect_edge_setup
= (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
(cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT);
assign pb_detect_edge
= (cal1_state_r == CAL1_PAT_DETECT) ||
(cal1_state_r == CAL1_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE) ||
(cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
generate
for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge
always @(posedge clk) begin
if (pb_detect_edge_setup) begin
// Reset eye size, stable eye marker, and jitter marker before
// starting new edge detection iteration
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_found_edge_last_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_found_first_edge_r[z] <= #TCQ 1'b0;
end else if (pb_detect_edge) begin
// Save information on which DQ bits are already out of the
// data valid window - those DQ bits will later not have their
// IDELAY tap value incremented
pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z];
if (!pb_detect_edge_done_r[z]) begin
if (samp_cnt_done_r) begin
// If we've reached end of sampling interval, no jitter on
// current tap has been found (although an edge could have
// been found between the current and previous taps), and
// the sampling interval is complete. Increment the stable
// eye counter if no edge found, and always clear the jitter
// flag in preparation for the next tap.
pb_last_tap_jitter_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin
// If the data was completely stable during this tap and
// no edge was found between this and the previous tap
// then increment the stable eye counter "as appropriate"
if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1)
pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1;
else //if (pb_found_first_edge_r[z])
// We've reached minimum stable eye width
pb_found_stable_eye_r[z] <= #TCQ 1'b1;
end else begin
// Otherwise, an edge was found, either because of a
// difference between this and the previous tap's read
// data, and/or because the previous tap's data jittered
// (but not the current tap's data), then just set the
// edge found flag, and enable the stable eye counter
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end
end else if (prev_sr_diff_r[z]) begin
// If we find that the current tap read data jitters, then
// set edge and jitter found flags, "enable" the eye size
// counter, and stop sampling interval for this bit
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_last_tap_jitter_r[z] <= #TCQ 1'b1;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
pb_detect_edge_done_r[z] <= #TCQ 1'b1;
end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin
// If either an edge was found (i.e. difference between
// current tap and previous tap read data), or the previous
// tap exhibited jitter (which means by definition that the
// current tap cannot match the previous tap because the
// previous tap gave unstable data), then set the edge found
// flag, and "enable" eye size counter. But do not stop
// sampling interval - we still need to check if the current
// tap exhibits jitter
pb_cnt_eye_size_r[z] <= #TCQ 5'd0;
pb_found_stable_eye_r[z] <= #TCQ 1'b0;
pb_found_edge_r[z] <= #TCQ 1'b1;
pb_found_first_edge_r[z] <= #TCQ 1'b1;
end
end
end else begin
// Before every edge detection interval, reset "intra-tap" flags
pb_found_edge_r[z] <= #TCQ 1'b0;
pb_detect_edge_done_r[z] <= #TCQ 1'b0;
end
end
end
endgenerate
// Combine the above per-bit status flags into combined terms when
// performing deskew on the aggregate data window
always @(posedge clk) begin
detect_edge_done_r <= #TCQ &pb_detect_edge_done_r;
found_edge_r <= #TCQ |pb_found_edge_r;
found_edge_all_r <= #TCQ &pb_found_edge_r;
found_stable_eye_r <= #TCQ &pb_found_stable_eye_r;
end
// last IODELAY "stable eye" indicator is updated only after
// detect_edge_done_r is asserted - so that when we do find the "right edge"
// of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1
// when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates
// immediately, then it never possible to have found_stable_eye_r = 1
// when we detect an edge - and we'll never know whether we've found
// a "right edge")
always @(posedge clk)
if (pb_detect_edge_setup)
found_stable_eye_last_r <= #TCQ 1'b0;
else if (detect_edge_done_r)
found_stable_eye_last_r <= #TCQ found_stable_eye_r;
//*****************************************************************
// Keep track of DQ IDELAYE2 taps used
//*****************************************************************
// Added additional register stage to improve timing
always @(posedge clk)
if (rst)
idelay_tap_cnt_slice_r <= 5'h0;
else
idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
always @(posedge clk)
if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r
for (s = 0; s < RANKS; s = s + 1) begin
for (t = 0; t < DQS_WIDTH; t = t + 1) begin
idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val;
end
end
end else if (SIM_CAL_OPTION == "FAST_CAL") begin
for (u = 0; u < RANKS; u = u + 1) begin
for (w = 0; w < DQS_WIDTH; w = w + 1) begin
if (cal1_dq_idel_ce) begin
if (cal1_dq_idel_inc)
idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1;
else
idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1;
end
end
end
end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) &&
rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin
for (f = 0; f < DQS_WIDTH; f = f + 1) begin
idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f];
end
end else if (cal1_dq_idel_ce) begin
if (cal1_dq_idel_inc)
idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1;
else
idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1;
end else if (idelay_ld)
idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000;
always @(posedge clk)
if (rst || new_cnt_cpt_r)
idelay_tap_limit_r <= #TCQ 1'b0;
else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31)
idelay_tap_limit_r <= #TCQ 1'b1;
//*****************************************************************
// keep track of edge tap counts found, and current capture clock
// tap count
//*****************************************************************
always @(posedge clk)
if (rst || new_cnt_cpt_r ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
tap_cnt_cpt_r <= #TCQ 'b0;
else if (cal1_dlyce_cpt_r) begin
if (cal1_dlyinc_cpt_r)
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1;
else if (tap_cnt_cpt_r != 'd0)
tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1;
end
always @(posedge clk)
if (rst || new_cnt_cpt_r ||
(cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) ||
(mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
tap_limit_cpt_r <= #TCQ 1'b0;
else if (tap_cnt_cpt_r == 6'd63)
tap_limit_cpt_r <= #TCQ 1'b1;
always @(posedge clk)
cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r;
assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r};
// Storing DQS tap values at the end of each DQS read leveling
always @(posedge clk) begin
if (rst) begin
for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop
for (b = 0; b < DQS_WIDTH; b = b + 1)
rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0;
end
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin
for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r;
end
end
end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt
for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31;
end
end
end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin
rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r;
end
end
// Counter to track maximum DQ IODELAY tap usage during the per-bit
// deskew portion of stage 1 calibration
always @(posedge clk)
if (rst) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else
if (new_cnt_cpt_r) begin
idel_tap_cnt_dq_pb_r <= #TCQ 'b0;
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end else if (|cal1_dlyce_dq_r) begin
if (cal1_dlyinc_dq_r)
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1;
else
idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1;
if (idel_tap_cnt_dq_pb_r == 31)
idel_tap_limit_dq_pb_r <= #TCQ 1'b1;
else
idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
end
//*****************************************************************
always @(posedge clk) begin
cal1_state_r1 <= #TCQ cal1_state_r;
cal1_state_r2 <= #TCQ cal1_state_r1;
cal1_state_r3 <= #TCQ cal1_state_r2;
end
always @(posedge clk)
if (rst) begin
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
cnt_idel_dec_cpt_r <= #TCQ 6'bxxxxxx;
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
right_edge_taps_r <= #TCQ 6'b000000;
first_edge_taps_r <= #TCQ 6'bxxxxxx;
new_cnt_cpt_r <= #TCQ 1'b0;
rdlvl_stg1_done_int <= #TCQ 1'b0;
rdlvl_stg1_err <= #TCQ 1'b0;
second_edge_taps_r <= #TCQ 6'bxxxxxx;
store_sr_req_pulsed_r <= #TCQ 1'b0;
store_sr_req_r <= #TCQ 1'b0;
rnk_cnt_r <= #TCQ 2'b00;
rdlvl_rank_done_r <= #TCQ 1'b0;
idel_dec_cnt <= #TCQ 'd0;
rdlvl_last_byte_done_int <= #TCQ 1'b0;
idel_pat_detect_valid_r <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
idel_adj_inc <= #TCQ 1'b0;
if (OCAL_EN == "ON")
mpr_rdlvl_done_r <= #TCQ 1'b0;
else
mpr_rdlvl_done_r <= #TCQ 1'b1;
mpr_dec_cpt_r <= #TCQ 1'b0;
rdlvl_pi_incdec <= #TCQ 1'b0;
end else begin
// default (inactive) states for all "pulse" outputs
// verilint STARC-2.2.3.3 off
cal1_prech_req_r <= #TCQ 1'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
new_cnt_cpt_r <= #TCQ 1'b0;
store_sr_req_pulsed_r <= #TCQ 1'b0;
store_sr_req_r <= #TCQ 1'b0;
case (cal1_state_r)
CAL1_IDLE: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
rdlvl_last_byte_done_int <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin
rdlvl_pi_incdec <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
end else begin
rdlvl_pi_incdec <= #TCQ 1'b1;
if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin
if (SIM_CAL_OPTION == "SKIP_CAL")
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
else if (SIM_CAL_OPTION == "FAST_CAL")
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
else begin
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
end
end
CAL1_MPR_NEW_DQS_WAIT: begin
cal1_prech_req_r <= #TCQ 1'b0;
if (!cal1_wait_r && mpr_valid_r)
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
end
// Wait for the new DQS group to change
// also gives time for the read data IN_FIFO to
// output the updated data for the new DQS group
CAL1_NEW_DQS_WAIT: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
rdlvl_last_byte_done_int <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
if (|pi_counter_read_val) begin //VK_REVIEW
mpr_dec_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val;
rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed
end else if (!cal1_wait_r) begin
rdlvl_pi_incdec <= #TCQ 1'b0;
// Store "previous tap" read data. Technically there is no
// "previous" read data, since we are starting a new DQS
// group, so we'll never find an edge at tap 0 unless the
// data is fluctuating/jittering
store_sr_req_r <= #TCQ 1'b1;
// If per-bit deskew is disabled, then skip the first
// portion of stage 1 calibration
if (PER_BIT_DESKEW == "OFF")
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
else if (PER_BIT_DESKEW == "ON")
cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT;
end else
rdlvl_pi_incdec <= #TCQ 1'b1; //every byte dec first so no read needed
end
//*****************************************************************
// Per-bit deskew states
//*****************************************************************
// Wait state following storage of initial read data
CAL1_PB_STORE_FIRST_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
// Look for an edge on all DQ bits in current DQS group
CAL1_PB_DETECT_EDGE:
if (detect_edge_done_r) begin
if (found_stable_eye_r) begin
// If we've found the left edge for all bits (or more precisely,
// we've found the left edge, and then part of the stable
// window thereafter), then proceed to positioning the CPT clock
// right before the left margin
cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT;
end else begin
// If we've reached the end of the sampling time, and haven't
// yet found the left margin of all the DQ bits, then:
if (!tap_limit_cpt_r) begin
// If we still have taps left to use, then store current value
// of read data, increment the capture clock, and continue to
// look for (left) edges
store_sr_req_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_CPT;
end else begin
// If we ran out of taps moving the capture clock, and we
// haven't finished edge detection, then reset the capture
// clock taps to 0 (gradually, one tap at a time...
// then exit the per-bit portion of the algorithm -
// i.e. proceed to adjust the capture clock and DQ IODELAYs as
cnt_idel_dec_cpt_r <= #TCQ 6'd63;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end
end
end
// Increment delay for DQS
CAL1_PB_INC_CPT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_CPT_WAIT;
end
// Wait for IODELAY for both capture and internal nodes within
// ISERDES to settle, before checking again for an edge
CAL1_PB_INC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r) begin
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
end
end
// We've found the left edges of the windows for all DQ bits
// (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture
// clock IDELAY to position just outside left edge of data window
CAL1_PB_DEC_CPT_LEFT:
if (cnt_idel_dec_cpt_r == 6'b000000)
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT;
else begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
end
CAL1_PB_DEC_CPT_LEFT_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
// If there is skew between individual DQ bits, then after we've
// positioned the CPT clock, we will be "in the window" for some
// DQ bits ("early" DQ bits), and "out of the window" for others
// ("late" DQ bits). Increase DQ taps until we are out of the
// window for all DQ bits
CAL1_PB_DETECT_EDGE_DQ:
if (detect_edge_done_r)
if (found_edge_all_r) begin
// We're out of the window for all DQ bits in this DQS group
// We're done with per-bit deskew for this group - now decr
// capture clock IODELAY tap count back to 0, and proceed
// with the rest of stage 1 calibration for this DQS group
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end else
if (!idel_tap_limit_dq_pb_r)
// If we still have DQ taps available for deskew, keep
// incrementing IODELAY tap count for the appropriate DQ bits
cal1_state_r <= #TCQ CAL1_PB_INC_DQ;
else begin
// Otherwise, stop immediately (we've done the best we can)
// and proceed with rest of stage 1 calibration
cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
end
CAL1_PB_INC_DQ: begin
// Increment only those DQ for which an edge hasn't been found yet
cal1_dlyce_dq_r <= #TCQ ~pb_found_edge_last_r;
cal1_dlyinc_dq_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_PB_INC_DQ_WAIT;
end
CAL1_PB_INC_DQ_WAIT:
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
// Decrement capture clock taps back to initial value
CAL1_PB_DEC_CPT:
if (cnt_idel_dec_cpt_r == 6'b000000)
cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT;
else begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
end
// Wait for capture clock to settle, then proceed to rest of
// state 1 calibration for this DQS group
CAL1_PB_DEC_CPT_WAIT:
if (!cal1_wait_r) begin
store_sr_req_r <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
end
// When first starting calibration for a DQS group, save the
// current value of the read data shift register, and use this
// as a reference. Note that for the first iteration of the
// edge detection loop, we will in effect be checking for an edge
// at IODELAY taps = 0 - normally, we are comparing the read data
// for IODELAY taps = N, with the read data for IODELAY taps = N-1
// An edge can only be found at IODELAY taps = 0 if the read data
// is changing during this time (possible due to jitter)
CAL1_STORE_FIRST_WAIT: begin
mpr_dec_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_PAT_DETECT;
end
CAL1_VALID_WAIT: begin
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
end
CAL1_MPR_PAT_DETECT: begin
rdlvl_pi_incdec <= #TCQ 1'b0;
// MPR read leveling for centering DQS in valid window before
// OCLKDELAYED calibration begins in order to eliminate read issues
if (idel_pat_detect_valid_r == 1'b0) begin
cal1_state_r <= #TCQ CAL1_VALID_WAIT;
idel_pat_detect_valid_r <= #TCQ 1'b1;
end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
idel_dec_cnt <= #TCQ 'd0;
end else if (!idelay_tap_limit_r)
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;
else
cal1_state_r <= #TCQ CAL1_RDLVL_ERR;
end
CAL1_PAT_DETECT: begin
// All DQ bits associated with a DQS are pushed to the right one IDELAY
// tap at a time until first rising DQS is in the tri-state region
// before first rising edge window.
// The detect_edge_done_r condition included to support averaging
// during IDELAY tap increments
rdlvl_pi_incdec <= #TCQ 1'b0;
if (detect_edge_done_r) begin
if (idel_pat_data_match) begin
case (idelay_adj)
2'b01: begin
cal1_state_r <= CAL1_DQ_IDEL_TAP_INC;
idel_dec_cnt <= #TCQ 5'd0;
idel_adj_inc <= #TCQ 1'b1;
end
2'b10: begin //DEC by 1
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC ;
idel_dec_cnt <= #TCQ 5'd1;
idel_adj_inc <= #TCQ 1'b0;
end
default: begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
idel_dec_cnt <= #TCQ 5'd0;
idel_adj_inc <= #TCQ 1'b0;
end
endcase
end else if (!idelay_tap_limit_r) begin
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC;
end else begin
cal1_state_r <= #TCQ CAL1_RDLVL_ERR;
end
end
end
// Increment IDELAY tap by 1 for DQ bits in the byte being calibrated
// until left edge of valid window detected
CAL1_DQ_IDEL_TAP_INC: begin
cal1_dq_idel_ce <= #TCQ 1'b1;
cal1_dq_idel_inc <= #TCQ 1'b1;
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT;
idel_pat_detect_valid_r <= #TCQ 1'b0;
end
CAL1_DQ_IDEL_TAP_INC_WAIT: begin
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
if (!cal1_wait_r) begin
idel_adj_inc <= #TCQ 1'b0;
if (idel_adj_inc)
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
else if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
else
cal1_state_r <= #TCQ CAL1_PAT_DETECT;
end
end
// Decrement by 2 IDELAY taps once idel_pat_data_match detected
CAL1_DQ_IDEL_TAP_DEC: begin
cal1_dq_idel_inc <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT;
if (idel_dec_cnt >= 'd0)
cal1_dq_idel_ce <= #TCQ 1'b1;
else
cal1_dq_idel_ce <= #TCQ 1'b0;
if (idel_dec_cnt > 'd0)
idel_dec_cnt <= #TCQ idel_dec_cnt - 1;
else
idel_dec_cnt <= #TCQ idel_dec_cnt;
end
CAL1_DQ_IDEL_TAP_DEC_WAIT: begin
cal1_dq_idel_ce <= #TCQ 1'b0;
cal1_dq_idel_inc <= #TCQ 1'b0;
if (!cal1_wait_r) begin
if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0))
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
else if (mpr_dec_cpt_r)
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
else
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
end
end
// Check for presence of data eye edge. During this state, we
// sample the read data multiple times, and look for changes
// in the read data, specifically:
// 1. A change in the read data compared with the value of
// read data from the previous delay tap. This indicates
// that the most recent tap delay increment has moved us
// into either a new window, or moved/kept us in the
// transition/jitter region between windows. Note that this
// condition only needs to be checked for once, and for
// logistical purposes, we check this soon after entering
// this state (see comment in CAL1_DETECT_EDGE below for
// why this is done)
// 2. A change in the read data while we are in this state
// (i.e. in the absence of a tap delay increment). This
// indicates that we're close enough to a window edge that
// jitter will cause the read data to change even in the
// absence of a tap delay change
CAL1_DETECT_EDGE: begin
// Essentially wait for the first comparision to finish, then
// store current data into "old" data register. This store
// happens now, rather than later (e.g. when we've have already
// left this state) in order to avoid the situation the data that
// is stored as "old" data has not been used in an "active
// comparison" - i.e. data is stored after the last comparison
// of this state. In this case, we can miss an edge if the
// following sequence occurs:
// 1. Comparison completes in this state - no edge found
// 2. "Momentary jitter" occurs which "pushes" the data out the
// equivalent of one delay tap
// 3. We store this jittered data as the "old" data
// 4. "Jitter" no longer present
// 5. We increment the delay tap by one
// 6. Now we compare the current with the "old" data - they're
// the same, and no edge is detected
// NOTE: Given the large # of comparisons done in this state, it's
// highly unlikely the above sequence will occur in actual H/W
// Wait for the first load of read data into the comparison
// shift register to finish, then load the current read data
// into the "old" data register. This allows us to do one
// initial comparision between the current read data, and
// stored data corresponding to the previous delay tap
idel_pat_detect_valid_r <= #TCQ 1'b0;
if (!store_sr_req_pulsed_r) begin
// Pulse store_sr_req_r only once in this state
store_sr_req_r <= #TCQ 1'b1;
store_sr_req_pulsed_r <= #TCQ 1'b1;
end else begin
store_sr_req_r <= #TCQ 1'b0;
store_sr_req_pulsed_r <= #TCQ 1'b1;
end
// Continue to sample read data and look for edges until the
// appropriate time interval (shorter for simulation-only,
// much, much longer for actual h/w) has elapsed
if (detect_edge_done_r) begin
if (tap_limit_cpt_r)
// Only one edge detected and ran out of taps since only one
// bit time worth of taps available for window detection. This
// can happen if at tap 0 DQS is in previous window which results
// in only left edge being detected. Or at tap 0 DQS is in the
// current window resulting in only right edge being detected.
// Depending on the frequency this case can also happen if at
// tap 0 DQS is in the left noise region resulting in only left
// edge being detected.
cal1_state_r <= #TCQ CAL1_CALC_IDEL;
else if (found_edge_r) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
found_first_edge_r <= #TCQ 1'b1;
// Only the right edge of the data valid window is found
// Record the inner right edge tap value
if (!found_first_edge_r && found_stable_eye_last_r) begin
if (tap_cnt_cpt_r == 'd0)
right_edge_taps_r <= #TCQ 'd0;
else
right_edge_taps_r <= #TCQ tap_cnt_cpt_r;
end
// Both edges of data valid window found:
// If we've found a second edge after a region of stability
// then we must have just passed the second ("right" edge of
// the window. Record this second_edge_taps = current tap-1,
// because we're one past the actual second edge tap, where
// the edge taps represent the extremes of the data valid
// window (i.e. smallest & largest taps where data still valid
if (found_first_edge_r && found_stable_eye_last_r) begin
found_second_edge_r <= #TCQ 1'b1;
second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1;
cal1_state_r <= #TCQ CAL1_CALC_IDEL;
end else begin
// Otherwise, an edge was found (just not the "second" edge)
// Assuming DQS is in the correct window at tap 0 of Phaser IN
// fine tap. The first edge found is the right edge of the valid
// window and is the beginning of the jitter region hence done!
first_edge_taps_r <= #TCQ tap_cnt_cpt_r;
//wait for read stop before PI increament
cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC;
end
end else
// Otherwise, if we haven't found an edge....
// If we still have taps left to use, then keep incrementing
//wait for read stop before PI increament
cal1_state_r <= #TCQ CAL1_RD_STOP_FOR_PI_INC;
end
end
//before increment PI, read command sending should be stopped.
//Also need to wait existing read is finished
CAL1_RD_STOP_FOR_PI_INC: begin
rdlvl_pi_incdec <= #TCQ 1'b1;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;
end
// Increment Phaser_IN delay for DQS
CAL1_IDEL_INC_CPT: begin
cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT_WAIT;
if (~tap_limit_cpt_r) begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b1;
end else begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
end
end
// Wait for Phaser_In to settle, before checking again for an edge
CAL1_IDEL_INC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r) begin
cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
rdlvl_pi_incdec <= #TCQ 1'b0; //return to normal read
end
end
// Calculate final value of Phaser_IN taps. At this point, one or both
// edges of data eye have been found, and/or all taps have been
// exhausted looking for the edges
// NOTE: We're calculating the amount to decrement by, not the
// absolute setting for DQS.
CAL1_CALC_IDEL: begin
// CASE1: If 2 edges found.
if (found_second_edge_r)
cnt_idel_dec_cpt_r
<= #TCQ ((second_edge_taps_r -
first_edge_taps_r)>>1) + 1;
else if (right_edge_taps_r > 6'd0)
// Only right edge detected
// right_edge_taps_r is the inner right edge tap value
// hence used for calculation
cnt_idel_dec_cpt_r
<= #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1));
else if (found_first_edge_r)
// Only left edge detected
cnt_idel_dec_cpt_r
<= #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1);
else
cnt_idel_dec_cpt_r
<= #TCQ (tap_cnt_cpt_r>>1);
// Now use the value we just calculated to decrement CPT taps
// to the desired calibration point
//cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
cal1_state_r <= #TCQ CAL1_CENTER_WAIT;
rdlvl_pi_incdec <= #TCQ 1'b1;
end
CAL1_CENTER_WAIT: begin
if(!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end
// decrement capture clock for final adjustment - center
// capture clock in middle of data eye. This adjustment will occur
// only when both the edges are found usign CPT taps. Must do this
// incrementally to avoid clock glitching (since CPT drives clock
// divider within each ISERDES)
CAL1_IDEL_DEC_CPT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b1;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// once adjustment is complete, we're done with calibration for
// this DQS, repeat for next DQS
cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
if (cnt_idel_dec_cpt_r == 6'b000001) begin
if (mpr_dec_cpt_r) begin
if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin
idel_dec_cnt <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
end else
cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
end else
cal1_state_r <= #TCQ CAL1_NEXT_DQS;
end else
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;
end
CAL1_IDEL_DEC_CPT_WAIT: begin
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
if (!cal1_wait_r)
cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
end
// Determine whether we're done, or have more DQS's to calibrate
// Also request precharge after every byte, as appropriate
CAL1_NEXT_DQS: begin
//if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2"))
cal1_prech_req_r <= #TCQ 1'b1;
//else
// cal1_prech_req_r <= #TCQ 1'b0;
cal1_dlyce_cpt_r <= #TCQ 1'b0;
cal1_dlyinc_cpt_r <= #TCQ 1'b0;
// Prepare for another iteration with next DQS group
found_first_edge_r <= #TCQ 1'b0;
found_second_edge_r <= #TCQ 1'b0;
first_edge_taps_r <= #TCQ 'd0;
second_edge_taps_r <= #TCQ 'd0;
right_edge_taps_r <= #TCQ 'd0;
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin
if (mpr_rdlvl_done_r) begin
rdlvl_last_byte_done_int <= #TCQ 1'b1;
mpr_last_byte_done <= #TCQ 1'b0;
end else begin
rdlvl_last_byte_done_int <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b1;
end
end
// Wait until precharge that occurs in between calibration of
// DQS groups is finished
if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
//rdlvl_rank_done_r <= #TCQ 1'b1;
rdlvl_last_byte_done_int <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD;
end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin
if (~mpr_rdlvl_done_r) begin
mpr_rank_done_r <= #TCQ 1'b1;
// if (rnk_cnt_r == RANKS-1) begin
// All DQS groups in all ranks done
cal1_state_r <= #TCQ CAL1_DONE;
cal1_cnt_cpt_r <= #TCQ 'b0;
// end else begin
// // Process DQS groups in next rank
// rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
// new_cnt_cpt_r <= #TCQ 1'b1;
// cal1_cnt_cpt_r <= #TCQ 'b0;
// cal1_state_r <= #TCQ CAL1_IDLE;
// end
end else begin
// All DQS groups in a rank done
rdlvl_rank_done_r <= #TCQ 1'b1;
if (rnk_cnt_r == RANKS-1) begin
// All DQS groups in all ranks done
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end else begin
// Process DQS groups in next rank
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_cnt_cpt_r <= #TCQ 'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
end
end
end else begin
// Process next DQS group
new_cnt_cpt_r <= #TCQ 1'b1;
cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1;
cal1_state_r <= #TCQ CAL1_NEW_DQS_PREWAIT;
end
end
end
CAL1_NEW_DQS_PREWAIT: begin
if (!cal1_wait_r) begin
rdlvl_pi_incdec <= #TCQ 1'b0;
if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
cal1_state_r <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
else
cal1_state_r <= #TCQ CAL1_NEW_DQS_WAIT;
end
end
// Load rank registers in Phaser_IN
CAL1_REGL_LOAD: begin
rdlvl_rank_done_r <= #TCQ 1'b0;
mpr_rank_done_r <= #TCQ 1'b0;
cal1_prech_req_r <= #TCQ 1'b0;
cal1_cnt_cpt_r <= #TCQ 'b0;
rnk_cnt_r <= #TCQ 2'b00;
if ((regl_rank_cnt == RANKS-1) &&
((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin
cal1_state_r <= #TCQ CAL1_DONE;
rdlvl_last_byte_done_int <= #TCQ 1'b0;
mpr_last_byte_done <= #TCQ 1'b0;
end else
cal1_state_r <= #TCQ CAL1_REGL_LOAD;
end
CAL1_RDLVL_ERR: begin
rdlvl_stg1_err <= #TCQ 1'b1;
end
// Done with this stage of calibration
// if used, allow DEBUG_PORT to control taps
CAL1_DONE: begin
mpr_rdlvl_done_r <= #TCQ 1'b1;
cal1_prech_req_r <= #TCQ 1'b0;
if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin
rdlvl_stg1_done_int <= #TCQ 1'b0;
cal1_state_r <= #TCQ CAL1_IDLE;
end else
rdlvl_stg1_done_int <= #TCQ 1'b1;
end
endcase
end
// verilint STARC-2.2.3.3 on
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v4_2_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Dec 20 2013
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ddr_phy_tempmon #
(
parameter SKIP_CALIB = "FALSE",
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
parameter TEMP_HYST = 1,
parameter TEMP_MIN_LIMIT = 12'h8ac,
parameter TEMP_MAX_LIMIT = 12'hca4
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
input [11:0] calib_device_temp, // Calibration device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec, // Assume control of PHASER_IN taps
output tempmon_done_skip
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
// Temperature sampler FSM encoding
localparam IDLE = 11'b000_0000_0001;
localparam INIT = 11'b000_0000_0010;
localparam FOUR_INC = 11'b000_0000_0100;
localparam THREE_INC = 11'b000_0000_1000;
localparam TWO_INC = 11'b000_0001_0000;
localparam ONE_INC = 11'b000_0010_0000;
localparam NEUTRAL = 11'b000_0100_0000;
localparam ONE_DEC = 11'b000_1000_0000;
localparam TWO_DEC = 11'b001_0000_0000;
localparam THREE_DEC = 11'b010_0000_0000;
localparam FOUR_DEC = 11'b100_0000_0000;
//===========================================================================
// Reg declarations
//===========================================================================
// Output port flops. Inc and dec are mutex.
reg pi_f_dec; // Flop output
reg pi_f_inc; // Flop output
reg pi_f_dec_nxt; // FSM output
reg pi_f_inc_nxt; // FSM output
// FSM state
reg [10:0] tempmon_state;
reg [10:0] tempmon_state_nxt;
// FSM output used to capture the initial device termperature
reg tempmon_state_init;
// Flag to indicate the initial device temperature is captured and normal operation can begin
reg tempmon_init_complete;
// Temperature band/state boundaries
reg [11:0] four_inc_max_limit;
reg [11:0] three_inc_max_limit;
reg [11:0] two_inc_max_limit;
reg [11:0] one_inc_max_limit;
reg [11:0] neutral_max_limit;
reg [11:0] one_dec_max_limit;
reg [11:0] two_dec_max_limit;
reg [11:0] three_dec_max_limit;
reg [11:0] three_inc_min_limit;
reg [11:0] two_inc_min_limit;
reg [11:0] one_inc_min_limit;
reg [11:0] neutral_min_limit;
reg [11:0] one_dec_min_limit;
reg [11:0] two_dec_min_limit;
reg [11:0] three_dec_min_limit;
reg [11:0] four_dec_min_limit;
reg [11:0] device_temp_init;
// Flops for capturing and storing the current device temperature
reg tempmon_sample_en_101;
reg tempmon_sample_en_102;
reg [11:0] device_temp_101;
reg [11:0] device_temp_capture_102;
reg update_temp_102;
// Flops for comparing temperature to max limits
reg temp_cmp_four_inc_max_102;
reg temp_cmp_three_inc_max_102;
reg temp_cmp_two_inc_max_102;
reg temp_cmp_one_inc_max_102;
reg temp_cmp_neutral_max_102;
reg temp_cmp_one_dec_max_102;
reg temp_cmp_two_dec_max_102;
reg temp_cmp_three_dec_max_102;
// Flops for comparing temperature to min limits
reg temp_cmp_three_inc_min_102;
reg temp_cmp_two_inc_min_102;
reg temp_cmp_one_inc_min_102;
reg temp_cmp_neutral_min_102;
reg temp_cmp_one_dec_min_102;
reg temp_cmp_two_dec_min_102;
reg temp_cmp_three_dec_min_102;
reg temp_cmp_four_dec_min_102;
reg calib_complete_r;
reg tempmon_done;
reg [2:0] sample_en_cnt;
always @ (posedge clk)
calib_complete_r <= #TCQ calib_complete;
wire [11:0] device_temp_in = ((tempmon_state_init | ~calib_complete_r) & (SKIP_CALIB == "TRUE")) ? calib_device_temp : device_temp;
always @ (posedge clk) begin
if (rst)
sample_en_cnt <= #TCQ 'd0;
else if ((tempmon_sample_en & ~tempmon_sample_en_101) & ((SKIP_CALIB == "TRUE")) & (sample_en_cnt < 'd5))
sample_en_cnt <= #TCQ sample_en_cnt + 1;
end
always @ (posedge clk) begin
if (rst)
tempmon_done <= #TCQ 1'b0;
else if ((sample_en_cnt == 'd5) & ((SKIP_CALIB == "TRUE")))
tempmon_done <= #TCQ 1'b1;
end
assign tempmon_done_skip = tempmon_done;
//===========================================================================
// Overview and temperature band limits
//===========================================================================
// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
// 125C will never be entered.
// Temperature lowest highest
// <------------------------------------------------------------------------------------------------------------------------------------------------>
//
// Temp four three two one neutral one two three four
// band/state inc inc inc inc dec dec dec dec
//
// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
// | | | | | | |
// | | | | | | |
// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
// | device_temp_init |
// four_inc_max_limit three_dec_max_limit
// Boundaries for moving from lower temp bands to higher temp bands.
// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
// Boundaries for moving from higher temp bands to lower temp bands
wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
//===========================================================================
// Capture device temperature
//===========================================================================
// There is a three stage pipeline used to capture temperature, calculate the next state
// of the FSM, and update the tempmon outputs.
//
// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
// Input device_temp is compared to ADC codes for 0C and 125C and limited
// at the flop input if needed.
//
// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
// to determine if a state change is needed. State changes are only enabled on the
// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
// increment or decrement signal is generated and flopped.
//
// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
wire device_temp_high = device_temp_in > TEMP_MAX_LIMIT;
wire device_temp_low = device_temp_in < TEMP_MIN_LIMIT;
wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp_in );
// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
// to enable normal sample operation.
wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
//===========================================================================
// Generate FSM arc signals
//===========================================================================
// Temperature comparisons for increasing temperature.
wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
// Temperature comparisons for decreasing temperature.
wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
// FSM arcs for increasing temperature.
wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
// FSM arcs for decreasing temperature.
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
//===========================================================================
// Implement FSM
//===========================================================================
// In addition to the nine temperature states, there are also IDLE and INIT states.
// The INIT state triggers the calculation of the temperature boundaries between the
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
// no timing restriction required between calib_complete and tempmon_sample_en.
always @(*) begin
tempmon_state_nxt = tempmon_state;
tempmon_state_init = 1'b0;
pi_f_inc_nxt = 1'b0;
pi_f_dec_nxt = 1'b0;
casez (tempmon_state)
IDLE: begin
if (calib_complete) tempmon_state_nxt = INIT;
end
INIT: begin
tempmon_state_nxt = NEUTRAL;
tempmon_state_init = 1'b1;
end
FOUR_INC: begin
if (temp_gte_four_inc_max) begin
tempmon_state_nxt = THREE_INC;
pi_f_dec_nxt = 1'b1;
end
end
THREE_INC: begin
if (temp_gte_three_inc_max) begin
tempmon_state_nxt = TWO_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_inc_min) begin
tempmon_state_nxt = FOUR_INC;
pi_f_inc_nxt = 1'b1;
end
end
TWO_INC: begin
if (temp_gte_two_inc_max) begin
tempmon_state_nxt = ONE_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_inc_min) begin
tempmon_state_nxt = THREE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_INC: begin
if (temp_gte_one_inc_max) begin
tempmon_state_nxt = NEUTRAL;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_inc_min) begin
tempmon_state_nxt = TWO_INC;
pi_f_inc_nxt = 1'b1;
end
end
NEUTRAL: begin
if (temp_gte_neutral_max) begin
tempmon_state_nxt = ONE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_neutral_min) begin
tempmon_state_nxt = ONE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_DEC: begin
if (temp_gte_one_dec_max) begin
tempmon_state_nxt = TWO_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_dec_min) begin
tempmon_state_nxt = NEUTRAL;
pi_f_inc_nxt = 1'b1;
end
end
TWO_DEC: begin
if (temp_gte_two_dec_max) begin
tempmon_state_nxt = THREE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_dec_min) begin
tempmon_state_nxt = ONE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
THREE_DEC: begin
if (temp_gte_three_dec_max) begin
tempmon_state_nxt = FOUR_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_dec_min) begin
tempmon_state_nxt = TWO_DEC;
pi_f_inc_nxt = 1'b1;
end
end
FOUR_DEC: begin
if (temp_lte_four_dec_min) begin
tempmon_state_nxt = THREE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
default: begin
tempmon_state_nxt = IDLE;
end
endcase
end //always
//synopsys translate_off
reg [71:0] tempmon_state_name;
always @(*) casez (tempmon_state)
IDLE : tempmon_state_name = "IDLE";
INIT : tempmon_state_name = "INIT";
FOUR_INC : tempmon_state_name = "FOUR_INC";
THREE_INC : tempmon_state_name = "THREE_INC";
TWO_INC : tempmon_state_name = "TWO_INC";
ONE_INC : tempmon_state_name = "ONE_INC";
NEUTRAL : tempmon_state_name = "NEUTRAL";
ONE_DEC : tempmon_state_name = "ONE_DEC";
TWO_DEC : tempmon_state_name = "TWO_DEC";
THREE_DEC : tempmon_state_name = "THREE_DEC";
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
default : tempmon_state_name = "BAD_STATE";
endcase
//synopsys translate_on
//===========================================================================
// Generate final output and implement flops
//===========================================================================
// Generate output
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
// Implement reset flops
always @(posedge clk) begin
if(rst) begin
tempmon_state <= #TCQ 11'b000_0000_0001;
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
four_inc_max_limit <= #TCQ 12'b0;
three_inc_max_limit <= #TCQ 12'b0;
two_inc_max_limit <= #TCQ 12'b0;
one_inc_max_limit <= #TCQ 12'b0;
neutral_max_limit <= #TCQ 12'b0;
one_dec_max_limit <= #TCQ 12'b0;
two_dec_max_limit <= #TCQ 12'b0;
three_dec_max_limit <= #TCQ 12'b0;
three_inc_min_limit <= #TCQ 12'b0;
two_inc_min_limit <= #TCQ 12'b0;
one_inc_min_limit <= #TCQ 12'b0;
neutral_min_limit <= #TCQ 12'b0;
one_dec_min_limit <= #TCQ 12'b0;
two_dec_min_limit <= #TCQ 12'b0;
three_dec_min_limit <= #TCQ 12'b0;
four_dec_min_limit <= #TCQ 12'b0;
device_temp_init <= #TCQ 12'b0;
tempmon_init_complete <= #TCQ 1'b0;
tempmon_sample_en_101 <= #TCQ 1'b0;
tempmon_sample_en_102 <= #TCQ 1'b0;
device_temp_101 <= #TCQ 12'b0;
device_temp_capture_102 <= #TCQ 12'b0;
end
else begin
tempmon_state <= #TCQ tempmon_state_nxt;
pi_f_inc <= #TCQ pi_f_inc_nxt;
pi_f_dec <= #TCQ pi_f_dec_nxt;
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
device_temp_init <= #TCQ device_temp_init_nxt;
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
device_temp_101 <= #TCQ device_temp_100;
device_temp_capture_102 <= #TCQ device_temp_capture_101;
end
end
// Implement non-reset flops
always @(posedge clk) begin
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
update_temp_102 <= #TCQ update_temp_101;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.2
// \ \ Application : MIG
// / / Filename : ddr_phy_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ddr_phy_top #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter DDR3_VDD_OP_VOLT = 135, // Voltage mode used for DDR3
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// This parameter must be set based on memory clock frequency
// It must be set to 4 for frequencies above 533 MHz?? (undecided)
// and set to 2 for 533 MHz and below
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter OUTPUT_DRV = "HIGH", // to calib_top
parameter REG_CTRL = "OFF", // to calib_top
parameter RTT_NOM = "60", // to calib_top
parameter RTT_WR = "120", // to calib_top
parameter tCK = 2500, // pS
parameter tRFC = 110000, // pS
parameter tREFI = 7800000, // pS
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter WRLVL = "OFF", // to calib_top
parameter DEBUG_PORT = "OFF", // to calib_top
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "OFF",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
//parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps
//parameter SIM_CAL_OPTION = "NONE", // Skip various calib steps
parameter REFCLK_FREQ = 200.0, // IODELAY ref clock freq (MHz)
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter RD_PATH_REG = 0, // optional registers in the read path
// to MC for timing improvement.
// =1 enabled, = 0 disabled
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter TAPSPERKCLK = 56,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SKIP_CALIB = "FALSE",
parameter FPGA_VOLT_TYPE = "N"
)
(
input clk, // Fabric logic clock
// To MC, calib_top, hard PHY
input clk_div2, // mem_refclk divided by 2 for PI incdec
input rst_div2, // reset in clk_div2 domain
input clk_ref, // Idelay_ctrl reference clock
// To hard PHY (external source)
input freq_refclk, // To hard PHY for Phasers
input mem_refclk, // Memory clock to hard PHY
input pll_lock, // System PLL lock signal
input sync_pulse, // 1/N sync pulse used to synchronize all PHASERS
input mmcm_ps_clk, // Phase shift clock for oclk stg3 centering
input poc_sample_pd, // Tell POC how to avoid metastability.
input error, // Support for TG error detect
output rst_tg_mc, // Support for TG error detect
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input rst,
input iddr_rst,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// From MC
input [nCK_PER_CLK-1:0] mc_ras_n,
input [nCK_PER_CLK-1:0] mc_cas_n,
input [nCK_PER_CLK-1:0] mc_we_n,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
input mc_reset_n,
input [1:0] mc_odt,
input [nCK_PER_CLK-1:0] mc_cke,
// AUX - For ODT and CKE assertion during reads and writes
input [3:0] mc_aux_out0,
input [3:0] mc_aux_out1,
input mc_cmd_wren,
input mc_ctl_wren,
input [2:0] mc_cmd,
input [1:0] mc_cas_slot,
input [5:0] mc_data_offset,
input [5:0] mc_data_offset_1,
input [5:0] mc_data_offset_2,
input [1:0] mc_rank_cnt,
// Write
input mc_wrdata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,
input idle,
// DDR bus signals
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
// Ports to be used when SKIP_CALIB="TRUE"
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// Debug Port Outputs
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output dbg_rddata_valid,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [1023:0] dbg_poc,
// FIFO status flags
output phy_mc_ctl_full,
output phy_mc_cmd_full,
output phy_mc_data_full,
// Calibration status and resultant outputs
output init_calib_complete,
output init_wrcal_complete,
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
output ref_dll_lock,
input rst_phaser_ref,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Parameter used to force skipping or abbreviation of initialization
// and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
// disables various other blocks depending on the option selected
// This option should only be used during simulation. In the case of
// the "SKIP" option, the testbench used should also not be modeling
// propagation delays.
// Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
// "NONE" = options determined by the individual parameter settings
// "SIM_FULL" = skip power-up delay. FULL calibration performed without
// averaging algorithm turned ON during window detection.
// "SKIP" = skip power-up delay. Skip calibration not yet supported.
// "FAST" = skip power-up delay, and calibrate (read leveling, write
// leveling, and phase detector) only using one DQS group, and
// apply the results to all other DQS groups.
localparam SIM_INIT_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" :
((SIM_BYPASS_INIT_CAL == "FAST") ||
(SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" :
"NONE");
localparam SIM_CAL_OPTION
= ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
(SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" :
((SIM_BYPASS_INIT_CAL == "SIM_FULL") ||
(SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" :
"NONE");
localparam WRLVL_W
= (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :
(BYTE_LANES_B2 != 0 ? 3 :
(BYTE_LANES_B1 != 0 ? 2 : 1))));
localparam HIGHEST_LANE_B0 = BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :
BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :
0;
localparam HIGHEST_LANE_B1 = BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :
BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :
0;
localparam HIGHEST_LANE_B2 = BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :
BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :
0;
localparam HIGHEST_LANE_B3 = BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :
BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :
0;
localparam HIGHEST_LANE_B4 = BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :
BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :
0;
localparam HIGHEST_LANE =
(HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :
((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :
((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) :
((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :
HIGHEST_LANE_B0)));
localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +
(0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +
(0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +
(0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +
((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +
(0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +
(0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +
(0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +
((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +
(0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +
(0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +
(0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +
((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +
(0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +
(0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +
(0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +
((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +
(0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +
(0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +
(0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));
// Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
// This should be the case since the PLL should be placed adjacent
// to the same IO Bank as Ck/Addr/Cmd and Control
localparam [2:0] CTL_BANK = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |
((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?
3'b000 :
(((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?
3'b001 :
(((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?
3'b010 :
(((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?
3'b011 :
(((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |
((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?
3'b100 : 3'b000;
localparam [7:0] CTL_BYTE_LANE = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_10_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_01_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_00 :
((N_CTL_LANES == 3) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_11_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?
8'b00_00_01_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_00 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_10 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
8'b00_00_11_01 :
((N_CTL_LANES == 2) &
(((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
8'b00_00_10_00 : 8'b11_10_01_00;
localparam PI_DIV2_INCDEC = (DRAM_TYPE == "DDR2") ? "FALSE" : (((FPGA_VOLT_TYPE == "L") && (nCK_PER_CLK == 4)) ? "TRUE" : "FALSE");
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire [(HIGHEST_LANE*12)-1:0] ddr_cmd_ctl_data;
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out;
wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;
wire phy_mc_go;
wire phy_ctl_full;
wire phy_cmd_full;
wire phy_data_full;
wire phy_pre_data_a_full;
wire if_empty /* synthesis syn_maxfan = 3 */;
wire phy_write_calib;
wire phy_read_calib;
wire [HIGHEST_BANK-1:0] rst_stg1_cal;
wire [5:0] calib_sel;
wire calib_in_common /* synthesis syn_maxfan = 10 */;
wire [HIGHEST_BANK-1:0] calib_zero_inputs;
wire [HIGHEST_BANK-1:0] calib_zero_ctrl;
wire pi_phase_locked;
wire pi_phase_locked_all;
wire pi_found_dqs;
wire pi_dqs_found_all;
wire pi_dqs_out_of_range;
wire pi_enstg2_f;
wire pi_stg2_fincdec;
wire pi_stg2_load;
wire [5:0] pi_stg2_reg_l;
wire idelay_ce;
wire idelay_inc;
wire idelay_ld;
wire [2:0] po_sel_stg2stg3;
wire [2:0] po_stg2_cincdec;
wire [2:0] po_enstg2_c;
wire [2:0] po_stg2_fincdec;
wire [2:0] po_enstg2_f;
wire [8:0] po_counter_read_val;
wire [5:0] pi_counter_read_val;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata;
reg [nCK_PER_CLK-1:0] parity;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] phy_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;
wire [nCK_PER_CLK-1:0] phy_ras_n;
wire [nCK_PER_CLK-1:0] phy_cas_n;
wire [nCK_PER_CLK-1:0] phy_we_n;
wire phy_reset_n;
wire [3:0] calib_aux_out;
wire [nCK_PER_CLK-1:0] calib_cke;
wire [1:0] calib_odt;
wire calib_ctl_wren;
wire calib_cmd_wren;
wire calib_wrdata_en;
wire [2:0] calib_cmd;
wire [1:0] calib_seq;
wire [5:0] calib_data_offset_0;
wire [5:0] calib_data_offset_1;
wire [5:0] calib_data_offset_2;
wire [1:0] calib_rank_cnt;
wire [1:0] calib_cas_slot;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address;
wire [3:0] mux_aux_out;
wire [3:0] aux_out_map;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank;
wire [2:0] mux_cmd;
wire mux_cmd_wren;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;
wire mux_ctl_wren;
wire [1:0] mux_cas_slot;
wire [5:0] mux_data_offset;
wire [5:0] mux_data_offset_1;
wire [5:0] mux_data_offset_2;
wire [nCK_PER_CLK-1:0] mux_ras_n;
wire [nCK_PER_CLK-1:0] mux_cas_n;
wire [1:0] mux_rank_cnt;
wire mux_reset_n;
wire [nCK_PER_CLK-1:0] mux_we_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata;
wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;
wire mux_wrdata_en;
wire [nCK_PER_CLK-1:0] mux_cke ;
wire [1:0] mux_odt ;
wire phy_if_empty_def;
wire phy_if_reset;
wire phy_init_data_sel;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_map;
wire phy_rddata_valid_w;
reg rddata_valid_reg;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data_reg;
wire [4:0] idelaye2_init_val;
wire [5:0] oclkdelay_init_val;
wire po_counter_load_en;
wire [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [DRAM_WIDTH-1:0] fine_delay_incdec_pb;
wire fine_delay_sel;
wire pd_out;
//***************************************************************************
assign dbg_rddata_valid = rddata_valid_reg;
assign dbg_rddata = rd_data_reg;
assign dbg_rd_data_offset = calib_rd_data_offset_0;
assign dbg_pi_phaselocked_done = pi_phase_locked_all;
assign dbg_po_counter_read_val = po_counter_read_val;
assign dbg_pi_counter_read_val = pi_counter_read_val;
//***************************************************************************
//***************************************************************************
// Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec
//***************************************************************************
//localparam PI_DIV2_INCDEC = "TRUE";
wire pi_fine_enable;
wire pi_fine_inc;
wire pi_counter_load_en;
wire [5:0] pi_counter_load_val;
wire [HIGHEST_BANK-1:0] pi_rst_dqs_find;
generate
if (PI_DIV2_INCDEC == "TRUE") begin: div2_incdec
// 3-stage synchronizer registers
(* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r1;
(* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r2;
(* ASYNC_REG = "TRUE" *) reg pi_enstg2_f_div2r3;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r1;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r2;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_fincdec_div2r3;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r1;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r2;
(* ASYNC_REG = "TRUE" *) reg pi_stg2_load_div2r3;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] rst_stg1_cal_div2r2;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r1;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r2;
(* ASYNC_REG = "TRUE" *) reg [5:0] pi_stg2_reg_l_div2r3;
reg pi_stg2_fine_enable, pi_stg2_fine_enable_r1;
reg pi_stg2_fine_inc, pi_stg2_fine_inc_r1;
reg pi_stg2_load_en, pi_stg2_load_en_r1;
reg [5:0] pi_stg2_load_val;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_BANK-1:0] pi_dqs_find_rst;
// 3-stage synchronizer
always @(posedge clk_div2) begin
//Phaser_In fine enable
pi_enstg2_f_div2r1 <= #TCQ pi_enstg2_f;
pi_enstg2_f_div2r2 <= #TCQ pi_enstg2_f_div2r1;
pi_enstg2_f_div2r3 <= #TCQ pi_enstg2_f_div2r2;
//Phaser_In fine incdec
pi_stg2_fincdec_div2r1 <= #TCQ pi_stg2_fincdec;
pi_stg2_fincdec_div2r2 <= #TCQ pi_stg2_fincdec_div2r1;
pi_stg2_fincdec_div2r3 <= #TCQ pi_stg2_fincdec_div2r2;
//Phaser_In stage2 load
pi_stg2_load_div2r1 <= #TCQ pi_stg2_load;
pi_stg2_load_div2r2 <= #TCQ pi_stg2_load_div2r1;
pi_stg2_load_div2r3 <= #TCQ pi_stg2_load_div2r2;
//Phaser_In stage2 load value
pi_stg2_reg_l_div2r1 <= #TCQ pi_stg2_reg_l;
pi_stg2_reg_l_div2r2 <= #TCQ pi_stg2_reg_l_div2r1;
pi_stg2_reg_l_div2r3 <= #TCQ pi_stg2_reg_l_div2r2;
//Phaser_In reset DQSFOUND
rst_stg1_cal_div2r1 <= #TCQ rst_stg1_cal;
rst_stg1_cal_div2r2 <= #TCQ rst_stg1_cal_div2r1;
pi_dqs_find_rst <= #TCQ rst_stg1_cal_div2r2;
end
always @(posedge clk_div2) begin
pi_stg2_fine_enable_r1 <= #TCQ pi_stg2_fine_enable;
pi_stg2_fine_inc_r1 <= #TCQ pi_stg2_fine_inc;
pi_stg2_load_en_r1 <= #TCQ pi_stg2_load_en;
end
always @(posedge clk_div2) begin
if (rst_div2 || pi_stg2_fine_enable || pi_stg2_fine_enable_r1)
pi_stg2_fine_enable <= #TCQ 1'b0;
else if (pi_enstg2_f_div2r3)
pi_stg2_fine_enable <= #TCQ 1'b1;
end
always @(posedge clk_div2) begin
if (rst_div2 || pi_stg2_fine_inc || pi_stg2_fine_inc_r1)
pi_stg2_fine_inc <= #TCQ 1'b0;
else if (pi_stg2_fincdec_div2r3)
pi_stg2_fine_inc <= #TCQ 1'b1;
end
always @(posedge clk_div2) begin
if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1)
pi_stg2_load_en <= #TCQ 1'b0;
else if (pi_stg2_load_div2r3)
pi_stg2_load_en <= #TCQ 1'b1;
end
always @(posedge clk_div2) begin
if (rst_div2 || pi_stg2_load_en || pi_stg2_load_en_r1)
pi_stg2_load_val <= #TCQ 6'd0;
else if (pi_stg2_load_div2r3)
pi_stg2_load_val <= #TCQ pi_stg2_reg_l_div2r3;
end
assign pi_fine_enable = pi_stg2_fine_enable;
assign pi_fine_inc = pi_stg2_fine_inc;
assign pi_counter_load_en = pi_stg2_load_en;
assign pi_counter_load_val = pi_stg2_load_val;
assign pi_rst_dqs_find = pi_dqs_find_rst;
end else begin: div4_incdec
assign pi_fine_enable = pi_enstg2_f;
assign pi_fine_inc = pi_stg2_fincdec;
assign pi_counter_load_en = pi_stg2_load;
assign pi_counter_load_val = pi_stg2_reg_l;
assign pi_rst_dqs_find = rst_stg1_cal;
end
endgenerate
genvar i;
generate
for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen
assign ddr_ck[i] = ddr_clk[LP_DDR_CK_WIDTH * i];
assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];
end
endgenerate
//***************************************************************************
// During memory initialization and calibration the calibration logic drives
// the memory signals. After calibration is complete the memory controller
// drives the memory signals.
// Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
//***************************************************************************
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;
genvar v ;
generate
if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm
for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin
if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin
assign mc_cs_n_temp[v] = mc_cs_n[v] ;
end else begin
assign mc_cs_n_temp[v] = 'b1 ;
end
end
end else begin
assign mc_cs_n_temp = mc_cs_n ;
end
endgenerate
assign mux_wrdata = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;
assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;
assign mux_address = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;
assign mux_bank = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;
assign mux_cs_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;
assign mux_ras_n = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;
assign mux_cas_n = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;
assign mux_we_n = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;
assign mux_reset_n = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;
assign mux_aux_out = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;
assign mux_odt = (phy_init_data_sel | init_wrcal_complete) ? mc_odt : calib_odt ;
assign mux_cke = (phy_init_data_sel | init_wrcal_complete) ? mc_cke : calib_cke ;
assign mux_cmd_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :
calib_cmd_wren;
assign mux_ctl_wren = (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :
calib_ctl_wren;
assign mux_wrdata_en = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :
calib_wrdata_en;
assign mux_cmd = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;
assign mux_cas_slot = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;
assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :
calib_data_offset_0;
assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :
calib_data_offset_1;
assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :
calib_data_offset_2;
// Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
assign mux_rank_cnt = 2'b00;
// Assigning cke & odt for DDR2 & DDR3
// No changes for DDR3 & DDR2 dual rank
// DDR2 single rank systems might potentially need 3 odt signals.
// Aux_out[2] will have the odt toggled by phy and controller
// wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
// all of the three odt bits or some of them might be used.
// mapping done in mc_phy_wrapper module
generate
if(CKE_ODT_AUX == "TRUE") begin
assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ?
{mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :
mux_aux_out;
end else begin
assign aux_out_map = 4'b0000 ;
end
endgenerate
assign init_calib_complete = phy_init_data_sel;
assign phy_mc_ctl_full = phy_ctl_full;
assign phy_mc_cmd_full = phy_cmd_full;
assign phy_mc_data_full = phy_pre_data_a_full;
//***************************************************************************
// Generate parity for DDR3 RDIMM.
//***************************************************************************
generate
if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],
mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],
mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});
parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],
mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],
mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
end
always @(*) begin
parity[1] = (^{mux_address[ROW_WIDTH-1:0],
mux_bank[BANK_WIDTH-1:0],
mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});
end
end
end else begin: gen_ddr3_noparity
if (nCK_PER_CLK == 4) begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
parity[2] <= #TCQ 1'b0;
parity[3] <= #TCQ 1'b0;
end
end else begin
always @(posedge clk) begin
parity[0] <= #TCQ 1'b0;
parity[1] <= #TCQ 1'b0;
end
end
end
endgenerate
//***************************************************************************
// Code for optional register stage in read path to MC for timing
//***************************************************************************
generate
if(RD_PATH_REG == 1)begin:RD_REG_TIMING
always @(posedge clk)begin
rddata_valid_reg <= #TCQ phy_rddata_valid_w;
rd_data_reg <= #TCQ rd_data_map;
end // always @ (posedge clk)
end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING
always @(phy_rddata_valid_w or rd_data_map)begin
rddata_valid_reg = phy_rddata_valid_w;
rd_data_reg = rd_data_map;
end
end
endgenerate
assign phy_rddata_valid = rddata_valid_reg;
assign phy_rd_data = rd_data_reg;
//***************************************************************************
// Hard PHY and accompanying bit mapping logic
//***************************************************************************
mig_7series_v4_2_ddr_mc_phy_wrapper #
(
.TCQ (TCQ),
.tCK (tCK),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CK_WIDTH (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.CWL (CWL),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.HIGHEST_BANK (HIGHEST_BANK),
.HIGHEST_LANE (HIGHEST_LANE),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DRAM_WIDTH (DRAM_WIDTH),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_mc_phy_wrapper
(
.rst (rst),
.iddr_rst (iddr_rst),
.clk (clk),
.clk_div2 (clk_div2),
// For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
// For memory frequencies below 400 MHz mem_refclk = mem_refclk and
// freq_refclk = 2x or 4x mem_refclk such that it remains in the
// 400~1066 MHz range
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.mmcm_ps_clk (mmcm_ps_clk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.idelayctrl_refclk (clk_ref),
.phy_cmd_wr_en (mux_cmd_wren),
.phy_data_wr_en (mux_wrdata_en),
// phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
// DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
// AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
// The fields ACTPRE, and BankCount are only used
// when the hard PHY counters are used by the MC.
.phy_ctl_wd ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,
mux_rank_cnt, 3'd0, aux_out_map,
5'd0, mux_cmd}),
.phy_ctl_wr (mux_ctl_wren),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
.data_offset_1 (mux_data_offset_1),
.data_offset_2 (mux_data_offset_2),
.aux_in_1 (aux_out_map),
.aux_in_2 (aux_out_map),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
.if_empty (if_empty),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.phy_pre_data_a_full (phy_pre_data_a_full),
.ddr_clk (ddr_clk),
.phy_mc_go (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.po_fine_enable (po_enstg2_f),
.po_coarse_enable (po_enstg2_c),
.po_fine_inc (po_stg2_fincdec),
.po_coarse_inc (po_stg2_cincdec),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_en (1'b1),
.po_sel_fine_oclk_delay (po_sel_stg2stg3),
.po_counter_load_val (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_counter_read_val (pi_counter_read_val),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
// Currently not being used. May be used in future if periodic reads
// become a requirement. This output could also be used to signal a
// catastrophic failure in read capture and the need for re-cal
.pi_dqs_out_of_range (pi_dqs_out_of_range),
.phy_init_data_sel (phy_init_data_sel),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.mux_address (mux_address),
.mux_bank (mux_bank),
.mux_cs_n (mux_cs_n),
.mux_ras_n (mux_ras_n),
.mux_cas_n (mux_cas_n),
.mux_we_n (mux_we_n),
.mux_reset_n (mux_reset_n),
.parity_in (parity),
.mux_wrdata (mux_wrdata),
.mux_wrdata_mask (mux_wrdata_mask),
.mux_odt (mux_odt),
.mux_cke (mux_cke),
.idle (idle),
.rd_data (rd_data_map),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_parity (ddr_parity),
.ddr_ras_n (ddr_ras_n),
.ddr_we_n (ddr_we_n),
.ddr_dq (ddr_dq),
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_reset_n (ddr_reset_n),
.dbg_pi_counter_read_en (1'b1),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.byte_sel_cnt (byte_sel_cnt),
.pd_out (pd_out),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
//***************************************************************************
// Soft memory initialization and calibration logic
//***************************************************************************
mig_7series_v4_2_ddr_calib_top #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.tCK (tCK),
.CLK_PERIOD (CLK_PERIOD),
.N_CTL_LANES (N_CTL_LANES),
.CTL_BYTE_LANE (CTL_BYTE_LANE),
.CTL_BANK (CTL_BANK),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (8),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.HIGHEST_BANK (HIGHEST_BANK),
.BANK_TYPE (BANK_TYPE),
.HIGHEST_LANE (HIGHEST_LANE),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.CS_WIDTH (CS_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.PER_BIT_DESKEW ("OFF"),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (CL),
.nCWL (CWL),
.tRFC (tRFC),
.tREFI (tREFI),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL_W),
.USE_ODT_PORT (USE_ODT_PORT),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SKIP_CALIB (SKIP_CALIB),
.PI_DIV2_INCDEC (PI_DIV2_INCDEC)
)
u_ddr_calib_top
(
.clk (clk),
.rst (rst),
.tg_err (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
// PHY Control Block and IN_FIFO status
.phy_ctl_ready (phy_mc_go),
.phy_ctl_full (1'b0),
.phy_cmd_full (1'b0),
.phy_data_full (1'b0),
.phy_if_empty (if_empty),
.idelaye2_init_val (idelaye2_init_val),
.oclkdelay_init_val (oclkdelay_init_val),
// From calib logic To data IN_FIFO
// DQ IDELAY tap value from Calib logic
// port to be added to mc_phy by Gary
.dlyval_dq (),
// hard PHY calibration modes
.write_calib (phy_write_calib),
.read_calib (phy_read_calib),
// DQS count and ck/addr/cmd to be mapped to calib_sel
// based on parameter that defines placement of ctl lanes
// and DQS byte groups in each bank. When phy_write_calib
// is de-asserted calib_sel should select CK/addr/cmd/ctl.
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.phy_if_empty_def (phy_if_empty_def),
.phy_if_reset (phy_if_reset),
// Signals from calib logic to be MUXED with MC
// signals before sending to hard PHY
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_odt (calib_odt),
.calib_cke (calib_cke),
.calib_cmd (calib_cmd),
.calib_wrdata_en (calib_wrdata_en),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.phy_reset_n (phy_reset_n),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_cas_n (phy_cas_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
// DQS Phaser_IN calibration/status signals
.pi_phaselocked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_found_dqs (pi_found_dqs),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.pi_rst_stg1_cal (rst_stg1_cal),
.pi_en_stg2_f (pi_enstg2_f),
.pi_stg2_f_incdec (pi_stg2_fincdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.pi_counter_read_val (pi_counter_read_val),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en),
// IDELAY tap enable and inc signals
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.idelay_ld (idelay_ld),
// DQS Phaser_OUT calibration/status signals
.po_sel_stg2stg3 (po_sel_stg2stg3),
.po_stg2_c_incdec (po_stg2_cincdec),
.po_en_stg2_c (po_enstg2_c),
.po_stg2_f_incdec (po_stg2_fincdec),
.po_en_stg2_f (po_enstg2_f),
.po_counter_load_en (po_counter_load_en),
.po_counter_read_val (po_counter_read_val),
// From data IN_FIFO To Calib logic and MC/UI
.phy_rddata (rd_data_map),
// From calib logic To MC
.phy_rddata_valid (phy_rddata_valid_w),
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.calib_writes (),
// Mem Init and Calibration status To MC
.init_calib_complete (phy_init_data_sel),
.init_wrcal_complete (init_wrcal_complete),
// Debug Error signals
.pi_phase_locked_err (dbg_pi_phaselock_err),
.pi_dqsfound_err (dbg_pi_dqsfound_err),
.wrcal_err (dbg_wrcal_err),
//used for oclk stg3 centering
.pd_out (pd_out),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.poc_sample_pd (poc_sample_pd),
.calib_tap_req (calib_tap_req),
.calib_tap_addr (calib_tap_addr),
.calib_tap_load (calib_tap_load),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
// Debug Signals
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_calib_top (dbg_calib_top),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.dbg_poc (dbg_poc[1023:0]),
.prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.byte_sel_cnt (byte_sel_cnt),
.fine_delay_incdec_pb (fine_delay_incdec_pb),
.fine_delay_sel (fine_delay_sel)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] = po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
generate
if (nCK_PER_CLK == 4) begin: match_data_4
assign dbg_phy_wrcal[0] = pat_data_match_r;
end else begin:match_data_2
assign dbg_phy_wrcal[0] = 1'b0;
end
endgenerate
assign dbg_phy_wrcal[4:1] = cal2_state_r1[3:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[22] = early1_data;
assign dbg_phy_wrcal[23] = early2_data;
assign dbg_phy_wrcal[24+:8] = mux_rd_rise0_r;
assign dbg_phy_wrcal[32+:8] = mux_rd_fall0_r;
assign dbg_phy_wrcal[40+:8] = mux_rd_rise1_r;
assign dbg_phy_wrcal[48+:8] = mux_rd_fall1_r;
generate
if (nCK_PER_CLK == 4) begin: mux_data_4
assign dbg_phy_wrcal[56+:8] = mux_rd_rise2_r;
assign dbg_phy_wrcal[64+:8] = mux_rd_fall2_r;
assign dbg_phy_wrcal[72+:8] = mux_rd_rise3_r;
assign dbg_phy_wrcal[80+:8] = mux_rd_fall3_r;
end else begin: mux_data_2
assign dbg_phy_wrcal[56+:8] = {8{1'b0}};
assign dbg_phy_wrcal[64+:8] = {8{1'b0}};
assign dbg_phy_wrcal[72+:8] = {8{1'b0}};
assign dbg_phy_wrcal[80+:8] = {8{1'b0}};
end
endgenerate
assign dbg_phy_wrcal[88] = early1_data_match_r;
assign dbg_phy_wrcal[89] = early2_data_match_r;
assign dbg_phy_wrcal[90] = wrcal_sanity_chk_r & pat_data_match_valid_r;
assign dbg_phy_wrcal[91] = wrcal_sanity_chk_r;
assign dbg_phy_wrcal[92] = wrcal_sanity_chk_done;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
//verilint STARC-2.2.3.3 off
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
//verilint STARC-2.2.3.3 on
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_wrlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
// 3. ODT not supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_phy_wrlvl #
(
parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 2,
parameter DRAM_WIDTH = 8,
parameter RANKS = 1,
parameter nCK_PER_CLK = 4,
parameter CLK_PERIOD = 4,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
input phy_ctl_ready,
input wr_level_start,
input wl_sm_start,
input wrlvl_final,
input wrlvl_byte_redo,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
input early1_data,
input early2_data,
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
input oclkdelay_calib_done,
input [(DQ_WIDTH)-1:0] rd_data_rise0,
output reg wrlvl_byte_done,
output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,
output phy_ctl_rdy_dly,
output reg wr_level_done /* synthesis syn_maxfan = 2 */,
// to phy_init for cs logic
output wrlvl_rank_done,
output done_dqs_tap_inc,
output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,
// Fine delay line used only during write leveling
// Inc/dec Phaser_Out fine delay line
output reg dqs_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_po_en_stg2_f,
// Coarse delay line used during write leveling
// only if 64 taps of fine delay line were not
// sufficient to detect a 0->1 transition
// Inc Phaser_Out coarse delay line
output reg dqs_wl_po_stg2_c_incdec,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_wl_po_en_stg2_c,
// Read Phaser_Out delay value
input [8:0] po_counter_read_val,
// output reg dqs_wl_po_stg2_load,
// output reg [8:0] dqs_wl_po_stg2_reg_l,
// CK edge undetected
output reg wrlvl_err,
output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
// Debug ports
output [5:0] dbg_wl_tap_cnt,
output dbg_wl_edge_detect_valid,
output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,
output [DQS_CNT_WIDTH:0] dbg_dqs_count,
output [4:0] dbg_wl_state,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl
);
localparam WL_IDLE = 5'h0;
localparam WL_INIT = 5'h1;
localparam WL_INIT_FINE_INC = 5'h2;
localparam WL_INIT_FINE_INC_WAIT1= 5'h3;
localparam WL_INIT_FINE_INC_WAIT = 5'h4;
localparam WL_INIT_FINE_DEC = 5'h5;
localparam WL_INIT_FINE_DEC_WAIT = 5'h6;
localparam WL_FINE_INC = 5'h7;
localparam WL_WAIT = 5'h8;
localparam WL_EDGE_CHECK = 5'h9;
localparam WL_DQS_CHECK = 5'hA;
localparam WL_DQS_CNT = 5'hB;
localparam WL_2RANK_TAP_DEC = 5'hC;
localparam WL_2RANK_DQS_CNT = 5'hD;
localparam WL_FINE_DEC = 5'hE;
localparam WL_FINE_DEC_WAIT = 5'hF;
localparam WL_CORSE_INC = 5'h10;
localparam WL_CORSE_INC_WAIT = 5'h11;
localparam WL_CORSE_INC_WAIT1 = 5'h12;
localparam WL_CORSE_INC_WAIT2 = 5'h13;
localparam WL_CORSE_DEC = 5'h14;
localparam WL_CORSE_DEC_WAIT = 5'h15;
localparam WL_CORSE_DEC_WAIT1 = 5'h16;
localparam WL_FINE_INC_WAIT = 5'h17;
localparam WL_2RANK_FINAL_TAP = 5'h18;
localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;
localparam WL_FINE_DEC_WAIT1 = 5'h1A;
localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;
localparam COARSE_TAPS = 7;
localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;
localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;
localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;
integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;
reg phy_ctl_ready_r1;
reg phy_ctl_ready_r2;
reg phy_ctl_ready_r3;
reg phy_ctl_ready_r4;
reg phy_ctl_ready_r5;
reg phy_ctl_ready_r6;
(* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;
reg [1:0] rank_cnt_r;
reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;
reg [DQS_WIDTH-1:0] rd_data_previous_r;
reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;
reg wr_level_done_r;
reg wrlvl_rank_done_r;
reg wr_level_start_r;
reg [4:0] wl_state_r, wl_state_r1;
reg inhibit_edge_detect_r;
reg wl_edge_detect_valid_r;
reg [5:0] wl_tap_count_r;
reg [5:0] fine_dec_cnt;
reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each
reg [2:0] corse_dec[0:DQS_WIDTH-1];
reg [2:0] corse_inc[0:DQS_WIDTH-1];
reg dq_cnt_inc;
reg [3:0] stable_cnt;
reg flag_ck_negedge;
//reg past_negedge;
reg flag_init;
reg [2:0] corse_cnt[0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;
reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];
//reg [3*DQS_WIDTH-1:0] coarse_tap_inc;
reg [2:0] final_coarse_tap[0:DQS_WIDTH-1];
reg [5:0] add_smallest[0:DQS_WIDTH-1];
reg [5:0] add_largest[0:DQS_WIDTH-1];
//reg [6*DQS_WIDTH-1:0] fine_tap_inc;
//reg [6*DQS_WIDTH-1:0] fine_tap_dec;
reg wr_level_done_r1;
reg wr_level_done_r2;
reg wr_level_done_r3;
reg wr_level_done_r4;
reg wr_level_done_r5;
reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];
reg [5:0] smallest[0:DQS_WIDTH-1];
reg [5:0] largest[0:DQS_WIDTH-1];
reg [5:0] final_val[0:DQS_WIDTH-1];
reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];
reg done_dqs_dec;
reg [8:0] po_rdval_cnt;
reg po_cnt_dec;
reg po_dec_done;
reg dual_rnk_dec;
wire [DQS_CNT_WIDTH+2:0] dqs_count_w;
reg [5:0] fast_cal_fine_cnt;
reg [2:0] fast_cal_coarse_cnt;
reg wrlvl_byte_redo_r;
reg [2:0] wrlvl_redo_corse_inc;
reg wrlvl_final_r;
reg final_corse_dec;
wire [DQS_CNT_WIDTH+2:0] oclk_count_w;
reg wrlvl_tap_done_r ;
reg [3:0] wait_cnt;
reg [3:0] incdec_wait_cnt;
// Debug ports
assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;
assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;
assign dbg_wl_tap_cnt = wl_tap_count_r;
assign dbg_dqs_count = dqs_count_r;
assign dbg_wl_state = wl_state_r;
assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt;
assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;
always @(*) begin
for (v = 0; v < DQS_WIDTH; v = v + 1)
corse_cnt_dbg[3*v+:3] = corse_cnt[v];
end
assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg;
assign dbg_phy_wrlvl[27+:5] = wl_state_r;
assign dbg_phy_wrlvl[32+:4] = dqs_count_r;
assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;
assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;
assign dbg_phy_wrlvl[54+:4] = stable_cnt;
assign dbg_phy_wrlvl[58] = 'd0;
assign dbg_phy_wrlvl[59] = flag_ck_negedge;
assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;
//**************************************************************************
// DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay
//**************************************************************************
assign po_stg2_wl_cnt = dqs_count_r;
assign wrlvl_rank_done = wrlvl_rank_done_r;
assign done_dqs_tap_inc = done_dqs_dec;
assign phy_ctl_rdy_dly = phy_ctl_ready_r6;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;
wrlvl_final_r <= #TCQ wrlvl_final;
if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
wr_level_done <= #TCQ 1'b0;
else
wr_level_done <= #TCQ done_dqs_dec;
end
// Status signal that will be asserted once the first
// pass of write leveling is done.
always @(posedge clk) begin
if(rst) begin
wrlvl_tap_done_r <= #TCQ 1'b0 ;
end else begin
if(wrlvl_tap_done_r == 1'b0) begin
if(oclkdelay_calib_done) begin
wrlvl_tap_done_r <= #TCQ 1'b1 ;
end
end
end
end
always @(posedge clk) begin
if (rst || po_cnt_dec)
wait_cnt <= #TCQ 'd8;
else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (po_rdval_cnt == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
po_dec_done <= #TCQ 1'b0;
else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
po_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
dqs_po_dec_done <= #TCQ po_dec_done;
wr_level_done_r1 <= #TCQ wr_level_done_r;
wr_level_done_r2 <= #TCQ wr_level_done_r1;
wr_level_done_r3 <= #TCQ wr_level_done_r2;
wr_level_done_r4 <= #TCQ wr_level_done_r3;
wr_level_done_r5 <= #TCQ wr_level_done_r4;
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];
if ((RANKS == 1) || ~oclkdelay_calib_done)
wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];
else
wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];
end
end
generate
if (RANKS == 2) begin: dual_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))
done_dqs_dec <= #TCQ 1'b1;
end
end else begin: single_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if (~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r3 && ~wr_level_done_r4)
done_dqs_dec <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk)
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))
wrlvl_byte_done <= #TCQ 1'b0;
else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)
wrlvl_byte_done <= #TCQ 1'b1;
// Storing DQS tap values at the end of each DQS write leveling
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop
for (n = 0; n < DQS_WIDTH; n = n + 1) begin
wl_corse_cnt[k][n] <= #TCQ 'b0;
wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;
end
end
end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |
(wl_state_r == WL_FINE_DEC_WAIT1) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;
wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r];
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin
for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt
wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;
wl_corse_cnt[p][q] <= #TCQ corse_cnt[0];
end
end
end
end
// Convert coarse delay to fine taps in case of unequal number of coarse
// taps between ranks. Assuming a difference of 1 coarse tap counts
// between ranks. A common fine and coarse tap value must be used for both ranks
// because Phaser_Out has only one rank register.
// Coarse tap1 = period(ps)*93/360 = 34 fine taps
// Other coarse taps = period(ps)*103/360 = 38 fine taps
generate
genvar cnt;
if (RANKS == 2) begin // Dual rank
for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt
always @(posedge clk) begin
if (rst) begin
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ 'd0;
end else if (wr_level_done_r1 & ~wr_level_done_r2) begin
if (~oclkdelay_calib_done) begin
for(y = 0 ; y < DQS_WIDTH; y = y+1) begin
final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y];
add_smallest[y] <= #TCQ 'd0;
add_largest[y] <= #TCQ 'd0;
end
end else
if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin
// Both ranks have use the same number of coarse delay taps.
// No conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin
// Rank 0 uses fewer coarse delay taps than rank1.
// conversion of coarse tap to fine taps required for rank1.
// The final coarse count will the smaller value.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1;
if (|wl_corse_cnt[0][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd34;
end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin
// This may be an unlikely scenario in a real system.
// Rank 0 uses more coarse delay taps than rank1.
// conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
if (|wl_corse_cnt[1][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'smallest' value in final_val
// computation
add_smallest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'smallest' value in
// final_val computation
add_smallest[cnt] <= #TCQ 'd34;
end
end
end
end
end else begin
// Single rank
always @(posedge clk) begin
//coarse_tap_inc <= #TCQ 'd0;
for(w = 0; w < DQS_WIDTH; w = w + 1) begin
final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];
add_smallest[w] <= #TCQ 'd0;
add_largest[w] <= #TCQ 'd0;
end
end
end
endgenerate
// Determine delay value for DQS in multirank system
// Assuming delay value is the smallest for rank 0 DQS
// and largest delay value for rank 4 DQS
// Set to smallest + ((largest-smallest)/2)
always @(posedge clk) begin
if (rst) begin
for(x = 0; x < DQS_WIDTH; x = x +1) begin
smallest[x] <= #TCQ 'b0;
largest[x] <= #TCQ 'b0;
end
end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
end else if ((wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];
end else if (((SIM_CAL_OPTION == "FAST_CAL") |
(~oclkdelay_calib_done & ~wrlvl_byte_redo)) &
wr_level_done_r1 & ~wr_level_done_r2) begin
for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs
smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
largest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
end
end
end
// final_val to be used for all DQSs in all ranks
genvar wr_i;
generate
for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap
always @(posedge clk) begin
if (rst)
final_val[wr_i] <= #TCQ 'b0;
else if (wr_level_done_r2 && ~wr_level_done_r3) begin
if (~oclkdelay_calib_done)
final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]);
else if ((smallest[wr_i] + add_smallest[wr_i]) <
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +
(((largest[wr_i] + add_largest[wr_i]) -
(smallest[wr_i] + add_smallest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) >
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +
(((smallest[wr_i] + add_smallest[wr_i]) -
(largest[wr_i] + add_largest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) ==
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);
end
end
end
endgenerate
// // fine tap inc/dec value for all DQSs in all ranks
// genvar dqs_i;
// generate
// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap
// always @(posedge clk) begin
// if (rst)
// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// else if (wr_level_done_r3 && ~wr_level_done_r4) begin
// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// end
// end
// endgenerate
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
// Fine delay line used only during write leveling
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
// Dec Phaser_Out fine delay (1)before write leveling,
// (2)if no 0 to 1 transition detected with 63 fine delay taps, or
// (3)dual rank case where fine taps for the first rank need to be 0
end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||
(wl_state_r == WL_FINE_DEC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b1;
// Inc Phaser_Out fine delay during write leveling
end else if ((wl_state_r == WL_INIT_FINE_INC) ||
(wl_state_r == WL_FINE_INC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b1;
dqs_po_en_stg2_f <= #TCQ 1'b1;
end else begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
end
end
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write leveling
// only if no 0->1 transition undetected with 64
// fine delay line taps
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end else if (wl_state_r == WL_CORSE_INC) begin
// Inc Phaser_Out coarse delay during write leveling
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end
end
// only storing the rise data for checking. The data comming back during
// write leveling will be a static value. Just checking for rise data is
// enough.
genvar rd_i;
generate
for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd
always @(posedge clk)
rd_data_rise_wl_r[rd_i] <=
#TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];
end
endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||
//(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))
rd_data_previous_r <= #TCQ rd_data_rise_wl_r;
end
// changed stable count from 3 to 7 because of fine tap resolution
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC) |
(wl_state_r == WL_FINE_DEC) |
(rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |
(wl_state_r1 == WL_INIT_FINE_DEC))
stable_cnt <= #TCQ 'd0;
else if ((wl_tap_count_r > 6'd0) &
(((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 'd14))
stable_cnt <= #TCQ stable_cnt + 1;
end
end
// Signal to ensure that flag_ck_negedge does not incorrectly assert
// when DQS is very close to CK rising edge
//always @(posedge clk) begin
// if (rst | (wl_state_r == WL_DQS_CNT) |
// (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
// past_negedge <= #TCQ 1'b0;
// else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
// (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
// (wl_state_r == WL_CORSE_INC_WAIT2)))
// past_negedge <= #TCQ 1'b1;
//end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r |
(wl_state_r1 == WL_INIT_FINE_DEC))
flag_ck_negedge <= #TCQ 1'd0;
else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |
(wl_state_r == WL_CORSE_INC))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
// Flag to inhibit rd_data_edge_detect_r before stable DQ
always @(posedge clk) begin
if (rst)
flag_init <= #TCQ 1'b1;
else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) ||
(wl_state_r1 == WL_INIT_FINE_DEC_WAIT)))
flag_init <= #TCQ 1'b0;
end
//checking for transition from 0 to 1
always @(posedge clk)begin
if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) |
inhibit_edge_detect_r)
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin
if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);
end
// registring the write level start signal
always@(posedge clk) begin
wr_level_start_r <= #TCQ wr_level_start;
end
// Assign dqs_count_r to dqs_count_w to perform the shift operation
// instead of multiply operation
assign dqs_count_w = {2'b00, dqs_count_r};
assign oclk_count_w = {2'b00, oclkdelay_calib_cnt};
always @(posedge clk) begin
if (rst)
incdec_wait_cnt <= #TCQ 'd0;
else if ((wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_INIT_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC_WAIT_TMP))
incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1;
else
incdec_wait_cnt <= #TCQ 'd0;
end
// state machine to initiate the write leveling sequence
// The state machine operates on one byte at a time.
// It will increment the delays to the DQS OSERDES
// and sample the DQ from the memory. When it detects
// a transition from 1 to 0 then the write leveling is considered
// done.
always @(posedge clk) begin
if(rst)begin
wrlvl_err <= #TCQ 1'b0;
wr_level_done_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
dq_cnt_inc <= #TCQ 1'b1;
rank_cnt_r <= #TCQ 2'b00;
wl_state_r <= #TCQ WL_IDLE;
wl_state_r1 <= #TCQ WL_IDLE;
inhibit_edge_detect_r <= #TCQ 1'b1;
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 6'd0;
fine_dec_cnt <= #TCQ 6'd0;
for (r = 0; r < DQS_WIDTH; r = r + 1) begin
fine_inc[r] <= #TCQ 6'b0;
corse_dec[r] <= #TCQ 3'b0;
corse_inc[r] <= #TCQ 3'b0;
corse_cnt[r] <= #TCQ 3'b0;
end
dual_rnk_dec <= #TCQ 1'b0;
fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE;
fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE;
final_corse_dec <= #TCQ 1'b0;
//zero_tran_r <= #TCQ 1'b0;
wrlvl_redo_corse_inc <= #TCQ 'd0;
end else begin
wl_state_r1 <= #TCQ wl_state_r;
case (wl_state_r)
WL_IDLE: begin
wrlvl_rank_done_r <= #TCQ 1'd0;
inhibit_edge_detect_r <= #TCQ 1'b1;
if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ wrcal_cnt;
corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt];
wl_tap_count_r <= #TCQ smallest[wrcal_cnt];
if (early1_data &&
(((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) ||
((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500))))
wrlvl_redo_corse_inc <= #TCQ REDO_COARSE;
else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2))
wrlvl_redo_corse_inc <= #TCQ 3'd6;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if (wrlvl_final && ~wrlvl_final_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ 'd0;
end
// verilint STARC-2.2.3.3 off
if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin
if (SIM_CAL_OPTION == "FAST_CAL")
wl_state_r <= #TCQ WL_FINE_INC;
else
wl_state_r <= #TCQ WL_INIT;
end
end
// verilint STARC-2.2.3.3 on
WL_INIT: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
inhibit_edge_detect_r <= #TCQ 1'b1;
wrlvl_rank_done_r <= #TCQ 1'd0;
//zero_tran_r <= #TCQ 1'b0;
if (wrlvl_final)
corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ];
if (wrlvl_byte_redo) begin
if (|wl_tap_count_r) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if(wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
end
// Initially Phaser_Out fine delay taps incremented
// until stable_cnt=14. A stable_cnt of 14 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 14 fine
// tap increments. This is done to inhibit false 0->1
// edge detection when DQS is initially aligned to the
// negedge of CK
WL_INIT_FINE_INC: begin
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
final_corse_dec <= #TCQ 1'b0;
end
WL_INIT_FINE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT;
end
// Case1: stable value of rd_data_previous_r=0 then
// proceed to 0->1 edge detection.
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_INC_WAIT: begin
if (wl_sm_start) begin
if (stable_cnt < 'd14)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
else if (~rd_data_previous_r[dqs_count_r]) begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end else begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end
end
end
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_DEC: begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_INIT_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT;
end
WL_INIT_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0) begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end
end
// Inc DQS Phaser_Out Stage2 Fine Delay line
WL_FINE_INC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL") begin
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (fast_cal_fine_cnt > 'd0)
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1;
else
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt;
end else if (wr_level_done_r5) begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (|fine_inc[dqs_count_w])
fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
end
end
WL_FINE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_fine_cnt > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
WL_FINE_DEC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_FINE_DEC_WAIT;
end
WL_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0)
wl_state_r <= #TCQ WL_FINE_DEC;
//else if (zero_tran_r)
// wl_state_r <= #TCQ WL_DQS_CNT;
else if (dual_rnk_dec) begin
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else
wl_state_r <= #TCQ WL_CORSE_INC;
end
WL_CORSE_DEC: begin
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;
dual_rnk_dec <= #TCQ 1'b0;
if (|corse_dec[dqs_count_r])
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1;
else
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r];
end
WL_CORSE_DEC_WAIT: begin
if (wl_sm_start) begin
//if (|corse_dec[dqs_count_r])
// wl_state_r <= #TCQ WL_CORSE_DEC;
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end
end
WL_CORSE_DEC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_DEC;
end
WL_CORSE_INC: begin
wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP;
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1;
else
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt;
end else if (wrlvl_byte_redo) begin
corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1;
if (|wrlvl_redo_corse_inc)
wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1;
end else if (~wr_level_done_r5)
corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1;
else if (|corse_inc[dqs_count_w])
corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1;
end
WL_CORSE_INC_WAIT_TMP: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT;
end
WL_CORSE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if (|wrlvl_redo_corse_inc)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_INIT_FINE_INC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end
end else if (~wr_level_done_r5 && wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;
else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
end
WL_CORSE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;
end
WL_CORSE_INC_WAIT2: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_WAIT;
end
WL_WAIT: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK;
end
WL_EDGE_CHECK: begin // Look for the edge
if (wl_edge_detect_valid_r == 1'b0) begin
wl_state_r <= #TCQ WL_WAIT;
wl_edge_detect_valid_r <= #TCQ 1'b1;
end
// 0->1 transition detected with DQS
else if(rd_data_edge_detect_r[dqs_count_r] &&
wl_edge_detect_valid_r)
begin
wl_tap_count_r <= #TCQ wl_tap_count_r;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) ||
~oclkdelay_calib_done)
wl_state_r <= #TCQ WL_DQS_CNT;
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// For initial writes check only upto 56 taps. Reserving the
// remaining taps for OCLK calibration.
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin
if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end else begin
if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal
wl_state_r <= #TCQ WL_FINE_INC;
else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end
end
WL_2RANK_TAP_DEC: begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
for (m = 0; m < DQS_WIDTH; m = m + 1)
corse_dec[m] <= #TCQ corse_cnt[m];
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b1;
end
WL_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1)) ||
wrlvl_byte_redo) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
end
WL_2RANK_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b0;
end
WL_DQS_CHECK: begin // check if all DQS have been calibrated
wl_tap_count_r <= #TCQ 'd0;
if (dq_cnt_inc == 1'b0)begin
wrlvl_rank_done_r <= #TCQ 1'd1;
for (t = 0; t < DQS_WIDTH; t = t + 1)
corse_cnt[t] <= #TCQ 3'b0;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin
wl_state_r <= #TCQ WL_IDLE;
if (wrlvl_byte_redo)
dqs_count_r <= #TCQ dqs_count_r;
else
dqs_count_r <= #TCQ 'd0;
end else if (rank_cnt_r == RANKS-1) begin
dqs_count_r <= #TCQ dqs_count_r;
if (RANKS > 1)
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
else
wl_state_r <= #TCQ WL_IDLE;
end else begin
wl_state_r <= #TCQ WL_INIT;
dqs_count_r <= #TCQ 'd0;
end
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(rank_cnt_r == RANKS-1)) begin
wr_level_done_r <= #TCQ 1'd1;
rank_cnt_r <= #TCQ 2'b00;
end else begin
wr_level_done_r <= #TCQ 1'd0;
rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;
end
end else
wl_state_r <= #TCQ WL_INIT;
end
WL_2RANK_FINAL_TAP: begin
if (wr_level_done_r4 && ~wr_level_done_r5) begin
for(u = 0; u < DQS_WIDTH; u = u + 1) begin
corse_inc[u] <= #TCQ final_coarse_tap[u];
fine_inc[u] <= #TCQ final_val[u];
end
dqs_count_r <= #TCQ 'd0;
end else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
end
end
endcase
end
end // always @ (posedge clk)
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64, // LFSR shift register length
parameter DQS_CNT_WIDTH = 5,
parameter DQ_WIDTH = 72,
parameter VCCO_PAT_EN = 1,
parameter VCCAUX_PAT_EN = 1,
parameter ISI_PAT_EN = 1,
parameter FIXED_VICTIM = "TRUE"
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
input prbs_rdlvl_done,
input complex_wr_done,
input [2:0] victim_sel,
input [DQS_CNT_WIDTH:0] byte_cnt,
//output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
output [8*DQ_WIDTH-1:0] prbs_o,
output [9:0] dbg_prbs_gen,
input reset_rd_addr,
output prbs_ignore_first_byte,
output prbs_ignore_last_bytes
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
//******************************************************************************
// Complex pattern BRAM
//******************************************************************************
localparam BRAM_ADDR_WIDTH = 8;
localparam BRAM_DATA_WIDTH = 18;
localparam BRAM_DEPTH = 256;
integer i,j;
(* RAM_STYLE = "distributed" *) reg [BRAM_ADDR_WIDTH - 1:0] rd_addr;
//reg [BRAM_DATA_WIDTH - 1:0] mem[0:BRAM_DEPTH - 1];
(* RAM_STYLE = "distributed" *) reg [BRAM_DATA_WIDTH - 1:0] mem_out;
reg [BRAM_DATA_WIDTH - 3:0] dout_o;
reg [DQ_WIDTH-1:0] sel;
reg [DQ_WIDTH-1:0] dout_rise0;
reg [DQ_WIDTH-1:0] dout_fall0;
reg [DQ_WIDTH-1:0] dout_rise1;
reg [DQ_WIDTH-1:0] dout_fall1;
reg [DQ_WIDTH-1:0] dout_rise2;
reg [DQ_WIDTH-1:0] dout_fall2;
reg [DQ_WIDTH-1:0] dout_rise3;
reg [DQ_WIDTH-1:0] dout_fall3;
// VCCO noise injection pattern with matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
always @ (rd_addr) begin
case (rd_addr)
8'd0 : mem_out = {2'b11, 8'b10101010,8'b10101010}; //1 read
8'd1 : mem_out = {2'b01, 8'b11001100,8'b11001100}; //2 reads
8'd2 : mem_out = {2'b10, 8'b11001100,8'b11001100}; //2 reads
8'd3 : mem_out = {2'b01, 8'b11100011,8'b11100011}; //3 reads
8'd4 : mem_out = {2'b00, 8'b10001110,8'b10001110}; //3 reads
8'd5 : mem_out = {2'b10, 8'b00111000,8'b00111000}; //3 reads
8'd6 : mem_out = {2'b01, 8'b11110000,8'b11110000}; //4 reads
8'd7 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd8 : mem_out = {2'b00, 8'b11110000,8'b11110000}; //4 reads
8'd9 : mem_out = {2'b10, 8'b11110000,8'b11110000}; //4 reads
8'd10 : mem_out = {2'b01, 8'b11111000,8'b11111000}; //5 reads
8'd11 : mem_out = {2'b00, 8'b00111110,8'b00111110}; //5 reads
8'd12 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //5 reads
8'd13 : mem_out = {2'b00, 8'b10000011,8'b10000011}; //5 reads
8'd14 : mem_out = {2'b10, 8'b11100000,8'b11100000}; //5 reads
8'd15 : mem_out = {2'b01, 8'b11111100,8'b11111100}; //6 reads
8'd16 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd17 : mem_out = {2'b00, 8'b11000000,8'b11000000}; //6 reads
8'd18 : mem_out = {2'b00, 8'b11111100,8'b11111100}; //6 reads
8'd19 : mem_out = {2'b00, 8'b00001111,8'b00001111}; //6 reads
8'd20 : mem_out = {2'b10, 8'b11000000,8'b11000000}; //6 reads
// VCCO noise injection pattern with non-matching victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd21 : mem_out = {2'b11, 8'b10101010,8'b01010101}; //1 read
8'd22 : mem_out = {2'b01, 8'b11001100,8'b00110011}; //2 reads
8'd23 : mem_out = {2'b10, 8'b11001100,8'b00110011}; //2 reads
8'd24 : mem_out = {2'b01, 8'b11100011,8'b00011100}; //3 reads
8'd25 : mem_out = {2'b00, 8'b10001110,8'b01110001}; //3 reads
8'd26 : mem_out = {2'b10, 8'b00111000,8'b11000111}; //3 reads
8'd27 : mem_out = {2'b01, 8'b11110000,8'b00001111}; //4 reads
8'd28 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd29 : mem_out = {2'b00, 8'b11110000,8'b00001111}; //4 reads
8'd30 : mem_out = {2'b10, 8'b11110000,8'b00001111}; //4 reads
8'd31 : mem_out = {2'b01, 8'b11111000,8'b00000111}; //5 reads
8'd32 : mem_out = {2'b00, 8'b00111110,8'b11000001}; //5 reads
8'd33 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //5 reads
8'd34 : mem_out = {2'b00, 8'b10000011,8'b01111100}; //5 reads
8'd35 : mem_out = {2'b10, 8'b11100000,8'b00011111}; //5 reads
8'd36 : mem_out = {2'b01, 8'b11111100,8'b00000011}; //6 reads
8'd37 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd38 : mem_out = {2'b00, 8'b11000000,8'b00111111}; //6 reads
8'd39 : mem_out = {2'b00, 8'b11111100,8'b00000011}; //6 reads
8'd40 : mem_out = {2'b00, 8'b00001111,8'b11110000}; //6 reads
8'd41 : mem_out = {2'b10, 8'b11000000,8'b00111111}; //6 reads
// VCCAUX noise injection pattern with ISI pattern on victim (reads with gaps)
// content format
// {aggressor pattern, victim pattern}
8'd42 : mem_out = {2'b01, 8'b10110100,8'b01010111}; //3 reads
8'd43 : mem_out = {2'b00, 8'b10110100,8'b01101111}; //3 reads
8'd44 : mem_out = {2'b10, 8'b10110100,8'b11000000}; //3 reads
8'd45 : mem_out = {2'b01, 8'b10100010,8'b10000100}; //4 reads
8'd46 : mem_out = {2'b00, 8'b10001010,8'b00110001}; //4 reads
8'd47 : mem_out = {2'b00, 8'b00101000,8'b01000111}; //4 reads
8'd48 : mem_out = {2'b10, 8'b10100010,8'b00100101}; //4 reads
8'd49 : mem_out = {2'b01, 8'b10101111,8'b10011010}; //5 reads
8'd50 : mem_out = {2'b00, 8'b01010000,8'b01111010}; //5 reads
8'd51 : mem_out = {2'b00, 8'b10101111,8'b10010101}; //5 reads
8'd52 : mem_out = {2'b00, 8'b01010000,8'b11011011}; //5 reads
8'd53 : mem_out = {2'b10, 8'b10101111,8'b11110000}; //5 reads
8'd54 : mem_out = {2'b01, 8'b10101000,8'b00100001}; //7 reads
8'd55 : mem_out = {2'b00, 8'b00101010,8'b10001010}; //7 reads
8'd56 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //7 reads
8'd57 : mem_out = {2'b00, 8'b10000010,8'b10011010}; //7 reads
8'd58 : mem_out = {2'b00, 8'b10100000,8'b01111010}; //7 reads
8'd59 : mem_out = {2'b00, 8'b10101000,8'b10111111}; //7 reads
8'd60 : mem_out = {2'b10, 8'b00101010,8'b01010111}; //7 reads
8'd61 : mem_out = {2'b01, 8'b10101011,8'b01101111}; //8 reads
8'd62 : mem_out = {2'b00, 8'b11110101,8'b11000000}; //8 reads
8'd63 : mem_out = {2'b00, 8'b01000000,8'b10000100}; //8 reads
8'd64 : mem_out = {2'b00, 8'b10101011,8'b00110001}; //8 reads
8'd65 : mem_out = {2'b00, 8'b11110101,8'b01000111}; //8 reads
8'd66 : mem_out = {2'b00, 8'b01000000,8'b00100101}; //8 reads
8'd67 : mem_out = {2'b00, 8'b10101011,8'b10011010}; //8 reads
8'd68 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //8 reads
8'd69 : mem_out = {2'b01, 8'b10101010,8'b10010101}; //9 reads
8'd70 : mem_out = {2'b00, 8'b00000010,8'b11011011}; //9 reads
8'd71 : mem_out = {2'b00, 8'b10101000,8'b11110000}; //9 reads
8'd72 : mem_out = {2'b00, 8'b00001010,8'b00100001}; //9 reads
8'd73 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //9 reads
8'd74 : mem_out = {2'b00, 8'b00101010,8'b00100101}; //9 reads
8'd75 : mem_out = {2'b00, 8'b10000000,8'b10011010}; //9 reads
8'd76 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //9 reads
8'd77 : mem_out = {2'b10, 8'b00000010,8'b10111111}; //9 reads
8'd78 : mem_out = {2'b01, 8'b10101010,8'b01010111}; //10 reads
8'd79 : mem_out = {2'b00, 8'b11111111,8'b01101111}; //10 reads
8'd80 : mem_out = {2'b00, 8'b01010101,8'b11000000}; //10 reads
8'd81 : mem_out = {2'b00, 8'b00000000,8'b10000100}; //10 reads
8'd82 : mem_out = {2'b00, 8'b10101010,8'b00110001}; //10 reads
8'd83 : mem_out = {2'b00, 8'b11111111,8'b01000111}; //10 reads
8'd84 : mem_out = {2'b00, 8'b01010101,8'b00100101}; //10 reads
8'd85 : mem_out = {2'b00, 8'b00000000,8'b10011010}; //10 reads
8'd86 : mem_out = {2'b00, 8'b10101010,8'b01111010}; //10 reads
8'd87 : mem_out = {2'b10, 8'b11111111,8'b10010101}; //10 reads
8'd88 : mem_out = {2'b01, 8'b10101010,8'b11011011}; //12 reads
8'd89 : mem_out = {2'b00, 8'b10000000,8'b11110000}; //12 reads
8'd90 : mem_out = {2'b00, 8'b00101010,8'b00100001}; //12 reads
8'd91 : mem_out = {2'b00, 8'b10100000,8'b10001010}; //12 reads
8'd92 : mem_out = {2'b00, 8'b00001010,8'b00100101}; //12 reads
8'd93 : mem_out = {2'b00, 8'b10101000,8'b10011010}; //12 reads
8'd94 : mem_out = {2'b00, 8'b00000010,8'b01111010}; //12 reads
8'd95 : mem_out = {2'b00, 8'b10101010,8'b10111111}; //12 reads
8'd96 : mem_out = {2'b00, 8'b00000000,8'b01010111}; //12 reads
8'd97 : mem_out = {2'b00, 8'b10101010,8'b01101111}; //12 reads
8'd98 : mem_out = {2'b00, 8'b10000000,8'b11000000}; //12 reads
8'd99 : mem_out = {2'b10, 8'b00101010,8'b10000100}; //12 reads
8'd100 : mem_out = {2'b01, 8'b10101010,8'b00110001}; //13 reads
8'd101 : mem_out = {2'b00, 8'b10111111,8'b01000111}; //13 reads
8'd102 : mem_out = {2'b00, 8'b11110101,8'b00100101}; //13 reads
8'd103 : mem_out = {2'b00, 8'b01010100,8'b10011010}; //13 reads
8'd104 : mem_out = {2'b00, 8'b00000000,8'b01111010}; //13 reads
8'd105 : mem_out = {2'b00, 8'b10101010,8'b10010101}; //13 reads
8'd106 : mem_out = {2'b00, 8'b10111111,8'b11011011}; //13 reads
8'd107 : mem_out = {2'b00, 8'b11110101,8'b11110000}; //13 reads
8'd108 : mem_out = {2'b00, 8'b01010100,8'b00100001}; //13 reads
8'd109 : mem_out = {2'b00, 8'b00000000,8'b10001010}; //13 reads
8'd110 : mem_out = {2'b00, 8'b10101010,8'b00100101}; //13 reads
8'd111 : mem_out = {2'b00, 8'b10111111,8'b10011010}; //13 reads
8'd112 : mem_out = {2'b10, 8'b11110101,8'b01111010}; //13 reads
8'd113 : mem_out = {2'b01, 8'b10101010,8'b10111111}; //14 reads
8'd114 : mem_out = {2'b00, 8'b10100000,8'b01010111}; //14 reads
8'd115 : mem_out = {2'b00, 8'b00000010,8'b01101111}; //14 reads
8'd116 : mem_out = {2'b00, 8'b10101010,8'b11000000}; //14 reads
8'd117 : mem_out = {2'b00, 8'b10000000,8'b10000100}; //14 reads
8'd118 : mem_out = {2'b00, 8'b00001010,8'b00110001}; //14 reads
8'd119 : mem_out = {2'b00, 8'b10101010,8'b01000111}; //14 reads
8'd120 : mem_out = {2'b00, 8'b00000000,8'b00100101}; //14 reads
8'd121 : mem_out = {2'b00, 8'b00101010,8'b10011010}; //14 reads
8'd122 : mem_out = {2'b00, 8'b10101000,8'b01111010}; //14 reads
8'd123 : mem_out = {2'b00, 8'b00000000,8'b10010101}; //14 reads
8'd124 : mem_out = {2'b00, 8'b10101010,8'b11011011}; //14 reads
8'd125 : mem_out = {2'b00, 8'b10100000,8'b11110000}; //14 reads
8'd126 : mem_out = {2'b10, 8'b00000010,8'b00100001}; //14 reads
// ISI pattern (Back-to-back reads)
// content format
// {aggressor pattern, victim pattern}
8'd127 : mem_out = {2'b01, 8'b01010111,8'b01010111};
8'd128 : mem_out = {2'b00, 8'b01101111,8'b01101111};
8'd129 : mem_out = {2'b00, 8'b11000000,8'b11000000};
8'd130 : mem_out = {2'b00, 8'b10000110,8'b10000100};
8'd131 : mem_out = {2'b00, 8'b00101000,8'b00110001};
8'd132 : mem_out = {2'b00, 8'b11100100,8'b01000111};
8'd133 : mem_out = {2'b00, 8'b10110011,8'b00100101};
8'd134 : mem_out = {2'b00, 8'b01001111,8'b10011011};
8'd135 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd136 : mem_out = {2'b00, 8'b10110101,8'b01010101};
8'd137 : mem_out = {2'b00, 8'b10000111,8'b10011000};
8'd138 : mem_out = {2'b00, 8'b11100011,8'b00011100};
8'd139 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd140 : mem_out = {2'b00, 8'b11010100,8'b00101011};
8'd141 : mem_out = {2'b00, 8'b01001000,8'b10110111};
8'd142 : mem_out = {2'b00, 8'b00011111,8'b11100000};
8'd143 : mem_out = {2'b00, 8'b10111100,8'b01000011};
8'd144 : mem_out = {2'b00, 8'b10001111,8'b00010100};
8'd145 : mem_out = {2'b00, 8'b10110100,8'b01001011};
8'd146 : mem_out = {2'b00, 8'b11001011,8'b00110100};
8'd147 : mem_out = {2'b00, 8'b00001010,8'b11110101};
8'd148 : mem_out = {2'b00, 8'b10000000,8'b00000000};
//Additional for ISI
8'd149 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd150 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd151 : mem_out = {2'b00, 8'b01010101,8'b01010101};
8'd152 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd153 : mem_out = {2'b00, 8'b00000000,8'b00000000};
8'd154 : mem_out = {2'b00, 8'b01010101,8'b00101010};
8'd155 : mem_out = {2'b00, 8'b01010101,8'b10101010};
8'd156 : mem_out = {2'b10, 8'b00000000,8'b10000000};
//Available
8'd157 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd158 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd159 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd160 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd161 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd162 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd163 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd164 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd165 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd166 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd167 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd168 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd169 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd170 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd171 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd172 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd173 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd174 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd175 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd176 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd177 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd178 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd179 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd180 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd181 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd182 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd183 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd184 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd185 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd186 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd187 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd188 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd189 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd190 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd191 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd192 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd193 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd194 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd195 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd196 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd197 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd198 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd199 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd200 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd201 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd202 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd203 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd204 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd205 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd206 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd207 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd208 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd209 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd210 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd211 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd212 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd213 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd214 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd215 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd216 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd217 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd218 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd219 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd220 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd221 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd222 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd223 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd224 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd225 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd226 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd227 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd228 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd229 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd230 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd231 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd232 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd233 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd234 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd235 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd236 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd237 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd238 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd239 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd240 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd241 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd242 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd243 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd244 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd245 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd246 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd247 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd248 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd249 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd250 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd251 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd252 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd253 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd254 : mem_out = {2'b00, 8'b00000001,8'b00000001};
8'd255 : mem_out = {2'b00, 8'b00000001,8'b00000001};
endcase
end
always @ (posedge clk_i) begin
if (rst_i | reset_rd_addr)
rd_addr <= #TCQ 'b0;
//rd_addr for complex oclkdelay calib
else if (clk_en_i && prbs_rdlvl_done && (~phy_if_empty_r || ~complex_wr_done)) begin
if (rd_addr == 'd156) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr + 1;
end
//rd_addr for complex rdlvl
else if (clk_en_i && (~phy_if_empty_r || (~prbs_rdlvl_start && ~complex_wr_done))) begin
if (rd_addr == 'd148) rd_addr <= #TCQ 'b0;
else rd_addr <= #TCQ rd_addr+1;
end
end
// Each pattern can be disabled independently
// When disabled zeros are written to and read from the DRAM
always @ (posedge clk_i) begin
if ((rd_addr < 42) && VCCO_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if ((rd_addr < 127) && VCCAUX_PAT_EN)
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else if (ISI_PAT_EN && (rd_addr > 126))
dout_o <= #TCQ mem_out[BRAM_DATA_WIDTH-3:0];
else
dout_o <= #TCQ 'd0;
end
reg prbs_ignore_first_byte_r;
always @(posedge clk_i) prbs_ignore_first_byte_r <= #TCQ mem_out[16];
assign prbs_ignore_first_byte = prbs_ignore_first_byte_r;
reg prbs_ignore_last_bytes_r;
always @(posedge clk_i) prbs_ignore_last_bytes_r <= #TCQ mem_out[17];
assign prbs_ignore_last_bytes = prbs_ignore_last_bytes_r;
generate
if (FIXED_VICTIM == "TRUE") begin: victim_sel_fixed
// Fixed victim bit 3
always @(posedge clk_i)
sel <= #TCQ {DQ_WIDTH/8{8'h08}};
end else begin: victim_sel_rotate
// One-hot victim select
always @(posedge clk_i)
if (rst_i)
sel <= #TCQ 'd0;
else begin
for (i = 0; i < DQ_WIDTH/8; i = i+1) begin
for (j=0; j <8 ; j = j+1) begin
if (j == victim_sel)
sel[i*8+j] <= #TCQ 1'b1;
else
sel[i*8+j] <= #TCQ 1'b0;
end
end
end
end
endgenerate
// construct 8 X DATA_WIDTH output bus
always @(*)
for (i = 0; i < DQ_WIDTH; i = i+1) begin
dout_rise0[i] = (dout_o[7]&&sel[i] || dout_o[15]&&~sel[i]);
dout_fall0[i] = (dout_o[6]&&sel[i] || dout_o[14]&&~sel[i]);
dout_rise1[i] = (dout_o[5]&&sel[i] || dout_o[13]&&~sel[i]);
dout_fall1[i] = (dout_o[4]&&sel[i] || dout_o[12]&&~sel[i]);
dout_rise2[i] = (dout_o[3]&&sel[i] || dout_o[11]&&~sel[i]);
dout_fall2[i] = (dout_o[2]&&sel[i] || dout_o[10]&&~sel[i]);
dout_rise3[i] = (dout_o[1]&&sel[i] || dout_o[9]&&~sel[i]);
dout_fall3[i] = (dout_o[0]&&sel[i] || dout_o[8]&&~sel[i]);
end
assign prbs_o = {dout_fall3, dout_rise3, dout_fall2, dout_rise2, dout_fall1, dout_rise1, dout_fall0, dout_rise0};
assign dbg_prbs_gen[9] = phy_if_empty_r;
assign dbg_prbs_gen[8] = clk_en_i;
assign dbg_prbs_gen[7:0] = rd_addr[7:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_skip_calib_tap.v
// /___/ /\ Date Last Modified: $Date: 2015/05/06 02:07:40 $
// \ \ / \ Date Created: May 06 2015
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Phaser_Out, Phaser_In, and IDELAY tap adjustments to match
// calibration values when SKIP_CALIB=="TRUE"
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_2_ddr_skip_calib_tap #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DQS_WIDTH = 8 // number of bytes
)
(
input clk,
input rst,
input phy_ctl_ready,
// Completed loading calib tap values into registers
input load_done,
// Tap adjustment status
input calib_tap_inc_start,
output calib_tap_inc_done,
// Calibration tap values
input [6*DQS_WIDTH-1:0] calib_po_stage2_tap_cnt,
input [6*DQS_WIDTH-1:0] calib_po_stage3_tap_cnt,
input [3*DQS_WIDTH-1:0] calib_po_coarse_tap_cnt,
input [6*DQS_WIDTH-1:0] calib_pi_stage2_tap_cnt,
input [5*DQS_WIDTH-1:0] calib_idelay_tap_cnt,
// Phaser_Out and Phaser_In tap count
input [8:0] po_counter_read_val,
input [5:0] pi_counter_read_val,
// Phaser_Out and Phaser_In tap inc/dec control signals
output [5:0] calib_tap_inc_byte_cnt,
output calib_po_f_en,
output calib_po_f_incdec,
output calib_po_sel_stg2stg3,
output calib_po_c_en,
output calib_po_c_inc,
output calib_pi_f_en,
output calib_pi_f_incdec,
output calib_idelay_ce,
output calib_idelay_inc,
output skip_cal_po_pi_dec_done,
output reg coarse_dec_err,
output [127:0] dbg_skip_cal
);
//***************************************************************************
// Decrement initial Phaser_OUT fine delay value before proceeding with
// calibration
//***************************************************************************
reg phy_ctl_ready_r1, phy_ctl_ready_r2, phy_ctl_ready_r3, phy_ctl_ready_r4, phy_ctl_ready_r5, phy_ctl_ready_r6;
reg po_cnt_dec;
reg [3:0] dec_wait_cnt;
reg [8:0] po_rdval_cnt;
reg po_dec_done;
reg dec_po_f_en_r;
reg dec_po_f_incdec_r;
reg dqs_po_dec_done_r1, dqs_po_dec_done_r2;
reg fine_dly_dec_done_r1, fine_dly_dec_done_r2, fine_dly_dec_done_r3;
reg [5:0] pi_rdval_cnt;
reg pi_cnt_dec;
reg dec_pi_f_en_r;
reg dec_pi_f_incdec_r;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
end
always @(posedge clk) begin
if (rst || po_cnt_dec || pi_cnt_dec)
dec_wait_cnt <= #TCQ 'd8;
else if (phy_ctl_ready_r6 && (dec_wait_cnt > 'd0))
dec_wait_cnt <= #TCQ dec_wait_cnt - 1;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (po_rdval_cnt == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (dec_wait_cnt == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
dec_po_f_incdec_r <= #TCQ 1'b0;
dec_po_f_en_r <= #TCQ 1'b0;
end else if (po_cnt_dec) begin
dec_po_f_incdec_r <= #TCQ 1'b0;
dec_po_f_en_r <= #TCQ 1'b1;
end else begin
dec_po_f_incdec_r <= #TCQ 1'b0;
dec_po_f_en_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst)
po_dec_done <= #TCQ 1'b0;
else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
po_dec_done <= #TCQ 1'b1;
end
end
//***************************************************************************
// Decrement initial Phaser_IN fine delay value before proceeding with
// calibration
//***************************************************************************
always @(posedge clk) begin
dqs_po_dec_done_r1 <= #TCQ po_dec_done;
dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;
fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;
fine_dly_dec_done_r3 <= #TCQ fine_dly_dec_done_r2;
end
always @(posedge clk) begin
if (rst) begin
pi_rdval_cnt <= #TCQ 'd0;
end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin
pi_rdval_cnt <= #TCQ pi_counter_read_val;
end else if (pi_rdval_cnt > 'd0) begin
if (pi_cnt_dec)
pi_rdval_cnt <= #TCQ pi_rdval_cnt - 1;
else
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end else if (pi_rdval_cnt == 'd0) begin
pi_rdval_cnt <= #TCQ pi_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (pi_rdval_cnt == 'd0))
pi_cnt_dec <= #TCQ 1'b0;
else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)
&& (dec_wait_cnt == 'd1))
pi_cnt_dec <= #TCQ 1'b1;
else
pi_cnt_dec <= #TCQ 1'b0;
end
// Inc/Dec Phaser_In stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
dec_pi_f_incdec_r <= #TCQ 1'b0;
dec_pi_f_en_r <= #TCQ 1'b0;
end else if (pi_cnt_dec) begin
dec_pi_f_incdec_r <= #TCQ 1'b0;
dec_pi_f_en_r <= #TCQ 1'b1;
end else begin
dec_pi_f_incdec_r <= #TCQ 1'b0;
dec_pi_f_en_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
fine_dly_dec_done_r1 <= #TCQ 1'b0;
end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||
(dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin
fine_dly_dec_done_r1 <= #TCQ 1'b1;
end
end
assign skip_cal_po_pi_dec_done = fine_dly_dec_done_r3;
//*************************end Phaser_Out and Phaser_In decrement to zero*******
localparam WAIT_CNT = 15;
// State Machine
localparam [4:0] IDLE = 5'h00;
localparam [4:0] READ_PO_PI_COUNTER_VAL = 5'h01;
localparam [4:0] CALC_INC_DEC_CNT_VAL = 5'h02;
localparam [4:0] WAIT_STG3_SEL = 5'h03;
localparam [4:0] PO_COARSE_CNT_CHECK = 5'h04;
localparam [4:0] PO_COARSE_INC = 5'h05;
localparam [4:0] PO_STG3_SEL = 5'h06;
localparam [4:0] PO_STG3_INC_CNT_CHECK = 5'h07;
localparam [4:0] PO_STG3_INC = 5'h08;
localparam [4:0] PO_STG3_DEC_CNT_CHECK = 5'h09;
localparam [4:0] PO_STG3_DEC = 5'h0A;
localparam [4:0] PO_STG2_INC_CNT_CHECK = 5'h0B;
localparam [4:0] PO_STG2_INC = 5'h0C;
localparam [4:0] PO_STG2_DEC_CNT_CHECK = 5'h0D;
localparam [4:0] PO_STG2_DEC = 5'h0E;
localparam [4:0] PI_STG2_INC_CNT_CHECK = 5'h0F;
localparam [4:0] PI_STG2_INC = 5'h10;
localparam [4:0] PI_STG2_DEC_CNT_CHECK = 5'h11;
localparam [4:0] PI_STG2_DEC = 5'h12;
localparam [4:0] IDELAY_CNT_CHECK = 5'h13;
localparam [4:0] IDELAY_TAP_INC = 5'h14;
localparam [4:0] WAIT_TAP_INC_DEC = 5'h15;
localparam [4:0] NEXT_BYTE = 5'h16;
localparam [4:0] WAIT_PO_PI_COUNTER_VAL = 5'h17;
localparam [4:0] PO_PI_TAP_ADJ_DONE = 5'h18;
reg calib_tap_inc_start_r;
reg [4:0] skip_state_r;
reg wait_cnt_en_r;
reg wait_cnt_done;
reg [3:0] wait_cnt_r;
reg po_sel_stg23_r;
reg po_f_en_r;
reg po_f_incdec_r;
reg po_c_en_r;
reg po_c_inc_r;
reg pi_f_en_r;
reg pi_f_incdec_r;
reg idelay_ce_r;
reg idelay_inc_r;
reg [2:0] po_c_inc_cnt;
reg [5:0] po_stg3_inc_cnt;
reg [5:0] po_stg3_dec_cnt;
reg [5:0] po_stg2_inc_cnt;
reg [5:0] po_stg2_dec_cnt;
reg [5:0] pi_stg2_inc_cnt;
reg [5:0] pi_stg2_dec_cnt;
reg [4:0] idelay_inc_cnt;
reg po_stg3_cnt_load_r;
reg po_c_inc_active_r;
reg po_stg3_inc_active_r;
reg po_stg3_dec_active_r;
reg po_stg2_inc_active_r;
reg po_stg2_dec_active_r;
reg pi_stg2_inc_active_r;
reg pi_stg2_dec_active_r;
reg idelay_inc_active_r;
reg [5:0] byte_cnt_r;
reg tap_adj_done_r;
reg [2:0] calib_byte_po_c_cnt;
reg [5:0] calib_byte_po_stg2_cnt;
reg [5:0] calib_byte_po_stg3_cnt;
reg [5:0] calib_byte_pi_stg2_cnt;
reg [4:0] calib_byte_idelay_cnt;
reg [4:0] skip_next_state;
reg [5:0] byte_cnt;
reg tap_adj_done;
reg po_sel_stg23;
reg po_f_en;
reg po_f_incdec;
reg po_c_en;
reg po_c_inc;
reg pi_f_en;
reg pi_f_incdec;
reg idelay_ce;
reg idelay_inc;
reg po_stg3_cnt_load;
reg po_c_inc_active;
reg po_stg3_inc_active;
reg po_stg3_dec_active;
reg po_stg2_inc_active;
reg po_stg2_dec_active;
reg pi_stg2_inc_active;
reg pi_stg2_dec_active;
reg idelay_inc_active;
// Output assignments
assign calib_tap_inc_byte_cnt = byte_cnt_r;
assign calib_po_f_en = fine_dly_dec_done_r3 ? po_f_en_r : dec_po_f_en_r;
assign calib_po_f_incdec = fine_dly_dec_done_r3 ? po_f_incdec_r : dec_po_f_incdec_r;
assign calib_po_sel_stg2stg3 = po_sel_stg23_r;
assign calib_po_c_en = po_c_en_r;
assign calib_po_c_inc = po_c_inc_r;
assign calib_pi_f_en = fine_dly_dec_done_r3 ? pi_f_en_r : dec_pi_f_en_r;
assign calib_pi_f_incdec = fine_dly_dec_done_r3 ? pi_f_incdec_r : dec_pi_f_incdec_r;
assign calib_idelay_ce = idelay_ce_r;
assign calib_idelay_inc = idelay_inc_r;
assign calib_tap_inc_done = tap_adj_done_r;
// Register input calib_tap_inc_start
always @(posedge clk)
calib_tap_inc_start_r <= #TCQ calib_tap_inc_start;
/**************************Wait Counter Start*********************************/
// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and
// WAIT_PO_PI_COUNTER_VAL
always @(posedge clk) begin
if ((skip_state_r == WAIT_STG3_SEL) ||
(skip_state_r == WAIT_TAP_INC_DEC) ||
(skip_state_r == WAIT_PO_PI_COUNTER_VAL))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
end
// Wait counter enable for wait states WAIT_STG3_SEL, WAIT_TAP_INC_DEC, and
// WAIT_PO_PI_COUNTER_VAL
always @(posedge clk) begin
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
wait_cnt_done <= #TCQ 1'b0;
end else begin
wait_cnt_r <= #TCQ 'b0;
wait_cnt_done <= #TCQ 1'b1;
end
end
end
/**************************Wait Counter End***********************************/
// Calibration tap values for current byte being adjusted
always @(posedge clk) begin
if (rst) begin
calib_byte_po_c_cnt <= #TCQ 'd0;
calib_byte_po_stg2_cnt <= #TCQ 'd0;
calib_byte_po_stg3_cnt <= #TCQ 'd0;
calib_byte_pi_stg2_cnt <= #TCQ 'd0;
calib_byte_idelay_cnt <= #TCQ 'd0;
end else begin
calib_byte_po_c_cnt <= #TCQ calib_po_coarse_tap_cnt[3*byte_cnt_r+:3];
calib_byte_po_stg2_cnt <= #TCQ calib_po_stage2_tap_cnt[6*byte_cnt_r+:6];
calib_byte_po_stg3_cnt <= #TCQ calib_po_stage3_tap_cnt[6*byte_cnt_r+:6];
calib_byte_pi_stg2_cnt <= #TCQ calib_pi_stage2_tap_cnt[6*byte_cnt_r+:6];
calib_byte_idelay_cnt <= #TCQ calib_idelay_tap_cnt[5*byte_cnt_r+:5];
end
end
// Phaser_Out, Phaser_In, and IDELAY inc/dec counters
always @(posedge clk) begin
if (rst) begin
po_c_inc_cnt <= #TCQ 'd0;
po_stg2_inc_cnt <= #TCQ 'd0;
po_stg2_dec_cnt <= #TCQ 'd0;
pi_stg2_inc_cnt <= #TCQ 'd0;
pi_stg2_dec_cnt <= #TCQ 'd0;
idelay_inc_cnt <= #TCQ 'd0;
end else if (skip_state_r == READ_PO_PI_COUNTER_VAL) begin
// IDELAY tap count setting
idelay_inc_cnt <= #TCQ calib_byte_idelay_cnt;
// Phaser_Out coarse tap setting
if (po_counter_read_val[8:6] == 'd0) begin
coarse_dec_err <= #TCQ 1'b0;
po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt;
end else if (po_counter_read_val[8:6] < calib_byte_po_c_cnt) begin
coarse_dec_err <= #TCQ 1'b0;
po_c_inc_cnt <= #TCQ calib_byte_po_c_cnt - po_counter_read_val[8:6];
end else begin
// Phaser_Out coarse taps cannot be decremented
coarse_dec_err <= #TCQ 1'b1;
po_c_inc_cnt <= #TCQ 'd0;
end
// Phaser_Out stage2 tap count setting when po_sel_stg23_r=0
if (po_counter_read_val[5:0] == 'd0) begin
po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt;
po_stg2_dec_cnt <= #TCQ 'd0;
end else if (po_counter_read_val[5:0] > calib_byte_po_stg2_cnt) begin
po_stg2_inc_cnt <= #TCQ 'd0;
po_stg2_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg2_cnt;
end else if (po_counter_read_val[5:0] < calib_byte_po_stg2_cnt) begin
po_stg2_inc_cnt <= #TCQ calib_byte_po_stg2_cnt - po_counter_read_val[5:0];
po_stg2_dec_cnt <= #TCQ 'd0;
end else if (po_counter_read_val[5:0] == calib_byte_po_stg2_cnt) begin
po_stg2_inc_cnt <= #TCQ 'd0;
po_stg2_dec_cnt <= #TCQ 'd0;
end
//Phaser_In stgae2 tap count setting
if (pi_counter_read_val == 'd0) begin
pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt;
pi_stg2_dec_cnt <= #TCQ 'd0;
end else if (pi_counter_read_val > calib_byte_pi_stg2_cnt) begin
pi_stg2_inc_cnt <= #TCQ 'd0;
pi_stg2_dec_cnt <= #TCQ pi_counter_read_val - calib_byte_pi_stg2_cnt;
end else if (pi_counter_read_val < calib_byte_pi_stg2_cnt) begin
pi_stg2_inc_cnt <= #TCQ calib_byte_pi_stg2_cnt - pi_counter_read_val;
pi_stg2_dec_cnt <= #TCQ 'd0;
end else if (pi_counter_read_val == calib_byte_pi_stg2_cnt) begin
pi_stg2_inc_cnt <= #TCQ 'd0;
pi_stg2_dec_cnt <= #TCQ 'd0;
end
end else begin
if (skip_state_r == IDELAY_TAP_INC)
idelay_inc_cnt <= #TCQ idelay_inc_cnt - 1;
if (skip_state_r == PO_COARSE_INC)
po_c_inc_cnt <= #TCQ po_c_inc_cnt - 1;
if (skip_state_r == PO_STG2_INC)
po_stg2_inc_cnt <= #TCQ po_stg2_inc_cnt - 1;
if (skip_state_r == PO_STG2_DEC)
po_stg2_dec_cnt <= #TCQ po_stg2_dec_cnt - 1;
if (skip_state_r == PI_STG2_INC)
pi_stg2_inc_cnt <= #TCQ pi_stg2_inc_cnt - 1;
if (skip_state_r == PI_STG2_DEC)
pi_stg2_dec_cnt <= #TCQ pi_stg2_dec_cnt - 1;
end
end
// Phaser_Out stage 3 tap count setting when po_sel_stg23_r=1
always @(posedge clk) begin
if (rst) begin
po_stg3_inc_cnt <= #TCQ 'd0;
po_stg3_dec_cnt <= #TCQ 'd0;
end else if ((skip_state_r == WAIT_STG3_SEL) && wait_cnt_done && po_stg3_cnt_load_r) begin
if (po_counter_read_val[5:0] == 'd0) begin
po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt;
po_stg3_dec_cnt <= #TCQ 'd0;
end else if (po_counter_read_val[5:0] > calib_byte_po_stg3_cnt) begin
po_stg3_inc_cnt <= #TCQ 'd0;
po_stg3_dec_cnt <= #TCQ po_counter_read_val[5:0] - calib_byte_po_stg3_cnt;
end else if (po_counter_read_val[5:0] < calib_byte_po_stg3_cnt) begin
po_stg3_inc_cnt <= #TCQ calib_byte_po_stg3_cnt - po_counter_read_val[5:0];
po_stg3_dec_cnt <= #TCQ 'd0;
end else if (po_counter_read_val[5:0] == calib_byte_po_stg3_cnt) begin
po_stg3_inc_cnt <= #TCQ 'd0;
po_stg3_dec_cnt <= #TCQ 'd0;
end
end else begin
if (skip_state_r == PO_STG3_INC)
po_stg3_inc_cnt <= #TCQ po_stg3_inc_cnt - 1;
if (skip_state_r == PO_STG3_DEC)
po_stg3_dec_cnt <= #TCQ po_stg3_dec_cnt - 1;
end
end
always @(posedge clk) begin
if (rst) begin
skip_state_r <= #TCQ IDLE;
byte_cnt_r <= #TCQ 'd0;
tap_adj_done_r <= #TCQ 1'b0;
po_sel_stg23_r <= #TCQ 1'b0;
po_f_en_r <= #TCQ 1'b0;
po_f_incdec_r <= #TCQ 1'b0;
po_c_en_r <= #TCQ 1'b0;
po_c_inc_r <= #TCQ 1'b0;
pi_f_en_r <= #TCQ 1'b0;
pi_f_incdec_r <= #TCQ 1'b0;
idelay_ce_r <= #TCQ 1'b0;
idelay_inc_r <= #TCQ 1'b0;
po_stg3_cnt_load_r <= #TCQ 1'b0;
po_c_inc_active_r <= #TCQ 1'b0;
po_stg3_inc_active_r <= #TCQ 1'b0;
po_stg3_dec_active_r <= #TCQ 1'b0;
po_stg2_inc_active_r <= #TCQ 1'b0;
po_stg2_dec_active_r <= #TCQ 1'b0;
pi_stg2_inc_active_r <= #TCQ 1'b0;
pi_stg2_dec_active_r <= #TCQ 1'b0;
idelay_inc_active_r <= #TCQ 1'b0;
end else begin
skip_state_r <= #TCQ skip_next_state;
byte_cnt_r <= #TCQ byte_cnt;
tap_adj_done_r <= #TCQ tap_adj_done;
po_sel_stg23_r <= #TCQ po_sel_stg23;
po_f_en_r <= #TCQ po_f_en;
po_f_incdec_r <= #TCQ po_f_incdec;
po_c_en_r <= #TCQ po_c_en;
po_c_inc_r <= #TCQ po_c_inc;
pi_f_en_r <= #TCQ pi_f_en;
pi_f_incdec_r <= #TCQ pi_f_incdec;
idelay_ce_r <= #TCQ idelay_ce;
idelay_inc_r <= #TCQ idelay_inc;
po_stg3_cnt_load_r <= #TCQ po_stg3_cnt_load;
po_c_inc_active_r <= #TCQ po_c_inc_active;
po_stg3_inc_active_r <= #TCQ po_stg3_inc_active;
po_stg3_dec_active_r <= #TCQ po_stg3_dec_active;
po_stg2_inc_active_r <= #TCQ po_stg2_inc_active;
po_stg2_dec_active_r <= #TCQ po_stg2_dec_active;
pi_stg2_inc_active_r <= #TCQ pi_stg2_inc_active;
pi_stg2_dec_active_r <= #TCQ pi_stg2_dec_active;
idelay_inc_active_r <= #TCQ idelay_inc_active;
end
end
// State Machine
always @(*) begin
skip_next_state = skip_state_r;
byte_cnt = byte_cnt_r;
tap_adj_done = tap_adj_done_r;
po_sel_stg23 = po_sel_stg23_r;
po_f_en = po_f_en_r;
po_f_incdec = po_f_incdec_r;
po_c_en = po_c_en_r;
po_c_inc = po_c_inc_r;
pi_f_en = pi_f_en_r;
pi_f_incdec = pi_f_incdec_r;
idelay_ce = idelay_ce_r;
idelay_inc = idelay_inc_r;
po_stg3_cnt_load = po_stg3_cnt_load_r;
po_c_inc_active = po_c_inc_active_r;
po_stg3_inc_active = po_stg3_inc_active_r;
po_stg3_dec_active = po_stg3_dec_active_r;
po_stg2_inc_active = po_stg2_inc_active_r;
po_stg2_dec_active = po_stg2_dec_active_r;
pi_stg2_inc_active = pi_stg2_inc_active_r;
pi_stg2_dec_active = pi_stg2_dec_active_r;
idelay_inc_active = idelay_inc_active_r;
case(skip_state_r)
IDLE: begin
// Begin tap adjustment on the rising edge of calib_tap_inc_start
// This logic assumes that load_done is asserted before calib_tap_inc_start
// If this is not the case this logic will have to change
if (calib_tap_inc_start && ~calib_tap_inc_start_r && load_done) begin
skip_next_state = READ_PO_PI_COUNTER_VAL;
end
end
READ_PO_PI_COUNTER_VAL: begin
skip_next_state = CALC_INC_DEC_CNT_VAL;
end
CALC_INC_DEC_CNT_VAL: begin
skip_next_state = WAIT_STG3_SEL;
po_sel_stg23 = 1'b1;
po_stg3_cnt_load = 1'b1;
end
WAIT_STG3_SEL: begin
if (wait_cnt_done) begin
if (po_stg3_cnt_load)
skip_next_state = PO_STG3_SEL;
else
skip_next_state = PO_COARSE_CNT_CHECK;
end
end
PO_COARSE_CNT_CHECK: begin
if (po_c_inc_cnt > 'd0) begin
po_c_inc_active = 1'b1;
skip_next_state = PO_COARSE_INC;
end else begin
po_c_inc_active = 1'b0;
skip_next_state = PO_STG2_DEC_CNT_CHECK;
end
end
PO_COARSE_INC: begin
po_c_en = 1'b1;
po_c_inc = 1'b1;
skip_next_state = WAIT_TAP_INC_DEC;
end
PO_STG3_SEL: begin
po_stg3_cnt_load = 1'b0;
if (po_stg3_inc_cnt > 'd0) begin
po_stg3_inc_active = 1'b1;
skip_next_state = PO_STG3_INC;
end else if (po_stg3_dec_cnt > 'd0) begin
po_stg3_dec_active = 1'b1;
skip_next_state = PO_STG3_DEC;
end else begin
po_sel_stg23 = 1'b0;
skip_next_state = WAIT_STG3_SEL;
end
end
PO_STG3_INC_CNT_CHECK: begin
if (po_stg3_inc_cnt > 'd0) begin
po_stg3_inc_active = 1'b1;
skip_next_state = PO_STG3_INC;
end else begin
po_stg3_inc_active = 1'b0;
po_sel_stg23 = 1'b0;
skip_next_state = WAIT_STG3_SEL;
end
end
PO_STG3_INC: begin
po_f_en = 1'b1;
po_f_incdec = 1'b1;
skip_next_state = WAIT_TAP_INC_DEC;
end
PO_STG3_DEC_CNT_CHECK: begin
if (po_stg3_dec_cnt > 'd0) begin
po_stg3_dec_active = 1'b1;
skip_next_state = PO_STG3_DEC;
end else begin
po_stg3_dec_active = 1'b0;
po_sel_stg23 = 1'b0;
skip_next_state = WAIT_STG3_SEL;
end
end
PO_STG3_DEC: begin
po_f_en = 1'b1;
po_f_incdec = 1'b0;
skip_next_state = WAIT_TAP_INC_DEC;
end
PO_STG2_DEC_CNT_CHECK: begin
if (po_stg2_dec_cnt > 'd0) begin
po_stg2_dec_active = 1'b1;
skip_next_state = PO_STG2_DEC;
end else if (po_stg2_inc_cnt > 'd0) begin
po_stg2_dec_active = 1'b0;
skip_next_state = PO_STG2_INC_CNT_CHECK;
end else begin
po_stg2_dec_active = 1'b0;
skip_next_state = PI_STG2_DEC_CNT_CHECK;
end
end
PO_STG2_DEC: begin
po_f_en = 1'b1;
po_f_incdec = 1'b0;
skip_next_state = WAIT_TAP_INC_DEC;
end
PO_STG2_INC_CNT_CHECK: begin
if (po_stg2_inc_cnt > 'd0) begin
po_stg2_inc_active = 1'b1;
skip_next_state = PO_STG2_INC;
end else begin
po_stg2_inc_active = 1'b0;
skip_next_state = PI_STG2_DEC_CNT_CHECK;
end
end
PO_STG2_INC: begin
po_f_en = 1'b1;
po_f_incdec = 1'b1;
skip_next_state = WAIT_TAP_INC_DEC;
end
PI_STG2_DEC_CNT_CHECK: begin
if (pi_stg2_dec_cnt > 'd0) begin
pi_stg2_dec_active = 1'b1;
skip_next_state = PI_STG2_DEC;
end else if (pi_stg2_inc_cnt > 'd0) begin
pi_stg2_dec_active = 1'b0;
skip_next_state = PI_STG2_INC_CNT_CHECK;
end else begin
pi_stg2_dec_active = 1'b0;
skip_next_state = IDELAY_CNT_CHECK;
end
end
PI_STG2_DEC: begin
pi_f_en = 1'b1;
pi_f_incdec = 1'b0;
skip_next_state = WAIT_TAP_INC_DEC;
end
PI_STG2_INC_CNT_CHECK: begin
if (pi_stg2_inc_cnt > 'd0) begin
pi_stg2_inc_active = 1'b1;
skip_next_state = PI_STG2_INC;
end else begin
pi_stg2_inc_active = 1'b0;
skip_next_state = IDELAY_CNT_CHECK;
end
end
PI_STG2_INC: begin
pi_f_en = 1'b1;
pi_f_incdec = 1'b1;
skip_next_state = WAIT_TAP_INC_DEC;
end
IDELAY_CNT_CHECK: begin
if (idelay_inc_cnt > 'd0) begin
idelay_inc_active = 1'b1;
skip_next_state = IDELAY_TAP_INC;
end else begin
idelay_inc_active = 1'b0;
skip_next_state = NEXT_BYTE;
end
end
IDELAY_TAP_INC: begin
idelay_ce = 1'b1;
idelay_inc = 1'b1;
skip_next_state = WAIT_TAP_INC_DEC;
end
WAIT_TAP_INC_DEC: begin
po_c_en = 1'b0;
po_c_inc = 1'b0;
po_f_en = 1'b0;
po_f_incdec = 1'b0;
pi_f_en = 1'b0;
pi_f_incdec = 1'b0;
idelay_ce = 1'b0;
idelay_inc = 1'b0;
if (wait_cnt_done) begin
if (po_c_inc_active_r)
skip_next_state = PO_COARSE_CNT_CHECK;
else if (po_stg3_inc_active_r)
skip_next_state = PO_STG3_INC_CNT_CHECK;
else if (po_stg3_dec_active_r)
skip_next_state = PO_STG3_DEC_CNT_CHECK;
else if (po_stg2_dec_active_r)
skip_next_state = PO_STG2_DEC_CNT_CHECK;
else if (po_stg2_inc_active_r)
skip_next_state = PO_STG2_INC_CNT_CHECK;
else if (pi_stg2_dec_active_r)
skip_next_state = PI_STG2_DEC_CNT_CHECK;
else if (pi_stg2_inc_active_r)
skip_next_state = PI_STG2_INC_CNT_CHECK;
else if (idelay_inc_active_r)
skip_next_state = IDELAY_CNT_CHECK;
end
end
NEXT_BYTE: begin
if (byte_cnt_r >= DQS_WIDTH-1) begin
skip_next_state = PO_PI_TAP_ADJ_DONE;
end else begin
byte_cnt = byte_cnt + 1;
skip_next_state = WAIT_PO_PI_COUNTER_VAL;
end
end
WAIT_PO_PI_COUNTER_VAL: begin
if (wait_cnt_done)
skip_next_state = READ_PO_PI_COUNTER_VAL;
end
PO_PI_TAP_ADJ_DONE: begin
tap_adj_done = 1'b1;
end
default: begin
skip_next_state = IDLE;
end
endcase
end
//Debug
assign dbg_skip_cal[4:0] = skip_state_r;
assign dbg_skip_cal[7:5] = po_c_inc_cnt;
assign dbg_skip_cal[13:8] = po_stg3_inc_cnt;
assign dbg_skip_cal[19:14] = po_stg3_dec_cnt;
assign dbg_skip_cal[25:20] = po_stg2_inc_cnt;
assign dbg_skip_cal[31:26] = po_stg2_dec_cnt;
assign dbg_skip_cal[37:32] = pi_stg2_inc_cnt;
assign dbg_skip_cal[43:38] = pi_stg2_dec_cnt;
assign dbg_skip_cal[48:44] = idelay_inc_cnt;
assign dbg_skip_cal[54:49] = byte_cnt_r;
assign dbg_skip_cal[55] = po_c_inc_active;
assign dbg_skip_cal[56] = po_stg3_inc_active;
assign dbg_skip_cal[57] = po_stg3_dec_active;
assign dbg_skip_cal[58] = po_stg2_inc_active;
assign dbg_skip_cal[59] = po_stg2_dec_active;
assign dbg_skip_cal[60] = pi_stg2_inc_active;
assign dbg_skip_cal[61] = pi_stg2_dec_active;
assign dbg_skip_cal[62] = idelay_inc_active;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_cc.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 20 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out characterization and control. Logic to interface with
// Chipscope and control. Intended to support real time observation. Largely
// not generated for production implementations.
//
// Also generates debug bus. Concept is a dynamic portion that can be used
// to examine the POC while it is operating, and a logging portion that
// stores per lane results.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_cc #
(parameter TCQ = 100,
parameter CCENABLE = 0,
parameter LANE_CNT_WIDTH = 2,
parameter PCT_SAMPS_SOLID = 95,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter SMWIDTH = 2,
parameter TAPCNTRWIDTH = 7)
(/*AUTOARG*/
// Outputs
samples, samps_solid_thresh, poc_error, dbg_poc,
// Inputs
psen, clk, rst, ktap_at_right_edge, ktap_at_left_edge,
mmcm_lbclk_edge_aligned, mmcm_edge_detect_done, fall_lead_right,
fall_trail_right, rise_lead_right, rise_trail_right, fall_lead_left,
fall_trail_left, rise_lead_left, rise_trail_left, fall_lead_center,
fall_trail_center, rise_lead_center, rise_trail_center, lane,
mmcm_edge_detect_rdy, poc_backup, sm, tap, run, run_end,
run_polarity, run_too_small, samp_cntr, samps_hi, samps_hi_held,
samps_zero, samps_one, run_ends, diff, left, right, window_center,
edge_center
);
// Remember SAMPLES is whole number counting. Zero corresponds to one sample.
localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01;
output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
input psen;
input clk, rst;
input ktap_at_right_edge, ktap_at_left_edge;
input mmcm_lbclk_edge_aligned;
wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned;
input mmcm_edge_detect_done;
reg mmcm_edge_detect_done_r;
always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done;
wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r;
reg [6:0] aligned_cnt_r;
wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done};
always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns;
reg poc_error_r;
wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r);
always @(posedge clk) poc_error_r <= #TCQ poc_error_ns;
output poc_error;
assign poc_error = poc_error_r;
input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right;
input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left;
input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center;
generate if (CCENABLE == 0) begin : no_characterization
assign samples = SAMPLES[SAMPCNTRWIDTH:0];
assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0];
end else begin : characterization
end endgenerate
reg [1023:0] dbg_poc_r;
output [1023:0] dbg_poc;
assign dbg_poc = dbg_poc_r;
input [LANE_CNT_WIDTH-1:0] lane;
input mmcm_edge_detect_rdy;
input poc_backup;
input [SMWIDTH-1:0] sm;
input [TAPCNTRWIDTH-1:0] tap;
input [TAPCNTRWIDTH-1:0] run;
input run_end;
input run_polarity;
input run_too_small;
input [SAMPCNTRWIDTH-1:0] samp_cntr;
input [SAMPCNTRWIDTH:0] samps_hi;
input [SAMPCNTRWIDTH:0] samps_hi_held;
input samps_zero, samps_one;
input [1:0] run_ends;
input [TAPCNTRWIDTH+1:0] diff;
always @(*) begin
dbg_poc_r[99:0] = 'b0;
dbg_poc_r[1023:900] = 'b0;
dbg_poc_r[0] = mmcm_edge_detect_rdy;
dbg_poc_r[1] = mmcm_edge_detect_done;
dbg_poc_r[2] = ktap_at_right_edge;
dbg_poc_r[3] = ktap_at_left_edge;
dbg_poc_r[4] = mmcm_lbclk_edge_aligned;
dbg_poc_r[5] = poc_backup;
dbg_poc_r[6+:SMWIDTH] = sm;
dbg_poc_r[10+:TAPCNTRWIDTH] = tap;
dbg_poc_r[20+:TAPCNTRWIDTH] = run;
dbg_poc_r[30] = run_end;
dbg_poc_r[31] = run_polarity;
dbg_poc_r[32] = run_too_small;
dbg_poc_r[33+:SAMPCNTRWIDTH] = samp_cntr;
dbg_poc_r[49+:SAMPCNTRWIDTH+1] = samps_hi;
dbg_poc_r[66+:SAMPCNTRWIDTH+1] = samps_hi_held;
dbg_poc_r[83] = samps_zero;
dbg_poc_r[84] = samps_one;
dbg_poc_r[86:85] = run_ends;
dbg_poc_r[87+:TAPCNTRWIDTH+2] = diff;
end // always @ (*)
input [TAPCNTRWIDTH-1:0] left, right;
input [TAPCNTRWIDTH:0] window_center, edge_center;
reg [899:100] dbg_poc_ns;
always @(posedge clk) dbg_poc_r[899:100] <= #TCQ dbg_poc_ns;
always @(*) begin
if (rst) dbg_poc_ns = 'b0;
else begin
dbg_poc_ns = dbg_poc_r[899:100];
if (mmcm_edge_detect_rdy && lane < 8) begin
dbg_poc_ns[(lane+1)*100] = poc_backup;
dbg_poc_ns[(lane+1)*100+1] = dbg_poc_ns[(lane+1)*100+1] || run_too_small;
dbg_poc_ns[(lane+1)*100+10+:TAPCNTRWIDTH] = left;
dbg_poc_ns[(lane+1)*100+20+:TAPCNTRWIDTH] = right;
dbg_poc_ns[(lane+1)*100+30+:TAPCNTRWIDTH+1] = window_center;
dbg_poc_ns[(lane+1)*100+41+:TAPCNTRWIDTH+1] = edge_center;
end
end
end
endmodule // mig_7series_v4_2_poc_cc
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Fri 24 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration edge store.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_edge_store #
(parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
fall_lead, fall_trail, rise_lead, rise_trail,
// Inputs
clk, run_polarity, run_end, select0, select1, tap, run
);
input clk;
input run_polarity;
input run_end;
input select0;
input select1;
input [TAPCNTRWIDTH-1:0] tap;
input [TAPCNTRWIDTH-1:0] run;
wire [TAPCNTRWIDTH:0] trailing_edge = run > tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run
: tap - run;
wire run_end_this = run_end && select0 && select1;
reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r;
output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail;
assign fall_lead = fall_lead_r;
assign fall_trail = fall_trail_r;
assign rise_lead = rise_lead_r;
assign rise_trail = rise_trail_r;
wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r;
wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
: rise_trail_r;
wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r;
wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0]
: fall_trail_r;
always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns;
always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns;
always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns;
always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns;
endmodule // mig_7series_v4_2_poc_edge_store
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_meta.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser output calibration meta controller.
//
// Compute center of the window set up with with the ktap_left,
// ktap_right dance (hereafter "the window"). Also compute center of the
// edge (hereafter "the edge") to be aligned in the center
// of this window.
//
// Following the ktap_left/right dance, the to be centered edge is
// always left at the right edge of the window
// if SCANFROMRIGHT == 1, and the left edge otherwise.
//
// An assumption is the rise(0) case has a window wider than the noise on the
// edge. The noise case with the possibly narrow window
// will always be shifted by 90. And the fall(180) case is shifted by
// 90 twice. Hence when we start, we can assume the center of the
// edge is to the right/left of the the window center.
//
// The actual hardware does not necessarily monotonically appear to
// move the window centers. Because of noise, it is possible for the
// centered edge to move opposite the expected direction with a tap increment.
//
// This problem is solved by computing the absolute difference between
// the centers and the circular distance between the centers. These will
// be the same until the difference transits through zero. Then the circular
// difference will jump to almost the value of TAPSPERKCLK.
//
// The window center computation is done at 1/2 tap increments to maintain
// resolution through the divide by 2 for centering.
//
// There is a corner case of when the shift is greater than 180 degress. In
// this case the absolute difference and the circular difference will be
// unequal at the beginning of the alignment. This is solved by latching
// if they are equal at the end of each cycle. The completion must see
// that they were equal in the previous cycle, but are not equal in this cycle.
//
// Since the phaser out steps are of unknown size, it is possible to overshoot
// the center. The previous difference is recorded and if its less than the current
// difference, poc_backup is driven high.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_meta #
(parameter SCANFROMRIGHT = 0,
parameter TCQ = 100,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
run_ends, mmcm_edge_detect_done, edge_center, left, right,
window_center, diff, poc_backup, mmcm_lbclk_edge_aligned,
// Inputs
rst, clk, mmcm_edge_detect_rdy, run_too_small, run, run_end,
run_polarity, rise_lead_right, rise_trail_left, rise_lead_center,
rise_trail_center, rise_trail_right, rise_lead_left, ninety_offsets,
use_noise_window, ktap_at_right_edge, ktap_at_left_edge
);
localparam NINETY = TAPSPERKCLK/4;
function [TAPCNTRWIDTH-1:0] offset (input [TAPCNTRWIDTH-1:0] a,
input [1:0] b,
input integer base);
integer offset_ii;
begin
offset_ii = (a + b * NINETY) < base
? (a + b * NINETY)
: (a + b * NINETY - base);
offset = offset_ii[TAPCNTRWIDTH-1:0];
end
endfunction // offset
function [TAPCNTRWIDTH-1:0] mod_sub (input [TAPCNTRWIDTH-1:0] a,
input [TAPCNTRWIDTH-1:0] b,
input integer base);
begin
mod_sub = (a>=b) ? a-b : a+base-b;
end
endfunction // mod_sub
function [TAPCNTRWIDTH:0] center (input [TAPCNTRWIDTH-1:0] left,
input [TAPCNTRWIDTH-1:0] diff,
input integer base);
integer center_ii;
begin
center_ii = ({left, 1'b0} + diff < base * 2)
? {left, 1'b0} + diff + 32'h0
: {left, 1'b0} + diff - base * 2;
center = center_ii[TAPCNTRWIDTH:0];
end
endfunction // center
input rst;
input clk;
input mmcm_edge_detect_rdy;
reg [1:0] run_ends_r;
input run_too_small;
reg run_too_small_r1, run_too_small_r2, run_too_small_r3;
always @ (posedge clk) run_too_small_r1 <= #TCQ run_too_small & (run_ends_r == 'd1); //align with run_end_r1;
always @ (posedge clk) run_too_small_r2 <= #TCQ run_too_small_r1;
always @ (posedge clk) run_too_small_r3 <= #TCQ run_too_small_r2;
wire reset_run_ends = rst || ~mmcm_edge_detect_rdy || run_too_small_r3 ;
// This input used only for the SVA.
input [TAPCNTRWIDTH-1:0] run;
input run_end;
reg run_end_r, run_end_r1, run_end_r2, run_end_r3;
always @(posedge clk) run_end_r <= #TCQ run_end;
always @(posedge clk) run_end_r1 <= #TCQ run_end_r;
always @(posedge clk) run_end_r2 <= #TCQ run_end_r1;
always @(posedge clk) run_end_r3 <= #TCQ run_end_r2;
input run_polarity;
reg run_polarity_held_ns, run_polarity_held_r;
always @(posedge clk) run_polarity_held_r <= #TCQ run_polarity_held_ns;
always @(*) run_polarity_held_ns = run_end ? run_polarity : run_polarity_held_r;
reg [1:0] run_ends_ns;
always @(posedge clk) run_ends_r <= #TCQ run_ends_ns;
always @(*) begin
run_ends_ns = run_ends_r;
if (reset_run_ends) run_ends_ns = 2'b0;
else case (run_ends_r)
2'b00 : run_ends_ns = run_ends_r + {1'b0, run_end_r3 && run_polarity_held_r};
2'b01, 2'b10 : run_ends_ns = run_ends_r + {1'b0, run_end_r3};
endcase // case (run_ends_r)
end // always @ begin
output [1:0] run_ends;
assign run_ends = run_ends_r;
reg done_r;
wire done_ns = mmcm_edge_detect_rdy && &run_ends_r;
always @(posedge clk) done_r <= #TCQ done_ns;
output mmcm_edge_detect_done;
assign mmcm_edge_detect_done = done_r;
input [TAPCNTRWIDTH-1:0] rise_lead_right;
input [TAPCNTRWIDTH-1:0] rise_trail_left;
input [TAPCNTRWIDTH-1:0] rise_lead_center;
input [TAPCNTRWIDTH-1:0] rise_trail_center;
input [TAPCNTRWIDTH-1:0] rise_trail_right;
input [TAPCNTRWIDTH-1:0] rise_lead_left;
input [1:0] ninety_offsets;
wire [1:0] offsets = SCANFROMRIGHT == 1 ? ninety_offsets : 2'b00 - ninety_offsets;
wire [TAPCNTRWIDTH-1:0] rise_lead_center_offset_ns = offset(rise_lead_center, offsets, TAPSPERKCLK);
wire [TAPCNTRWIDTH-1:0] rise_trail_center_offset_ns = offset(rise_trail_center, offsets, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] rise_lead_center_offset_r, rise_trail_center_offset_r;
always @(posedge clk) rise_lead_center_offset_r <= #TCQ rise_lead_center_offset_ns;
always @(posedge clk) rise_trail_center_offset_r <= #TCQ rise_trail_center_offset_ns;
wire [TAPCNTRWIDTH-1:0] edge_diff_ns = mod_sub(rise_trail_center_offset_r, rise_lead_center_offset_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] edge_diff_r;
always @(posedge clk) edge_diff_r <= #TCQ edge_diff_ns;
wire [TAPCNTRWIDTH:0] edge_center_ns = center(rise_lead_center_offset_r, edge_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] edge_center_r;
always @(posedge clk) edge_center_r <= #TCQ edge_center_ns;
output [TAPCNTRWIDTH:0] edge_center;
assign edge_center = edge_center_r;
input use_noise_window;
output [TAPCNTRWIDTH-1:0] left, right;
assign left = use_noise_window ? rise_lead_left : rise_trail_left;
assign right = use_noise_window ? rise_trail_right : rise_lead_right;
wire [TAPCNTRWIDTH-1:0] center_diff_ns = mod_sub(right, left, TAPSPERKCLK);
reg [TAPCNTRWIDTH-1:0] center_diff_r;
always @(posedge clk) center_diff_r <= #TCQ center_diff_ns;
wire [TAPCNTRWIDTH:0] window_center_ns = center(left, center_diff_r, TAPSPERKCLK);
reg [TAPCNTRWIDTH:0] window_center_r;
always @(posedge clk) window_center_r <= #TCQ window_center_ns;
output [TAPCNTRWIDTH:0] window_center;
assign window_center = window_center_r;
localparam TAPSPERKCLKX2 = TAPSPERKCLK * 2;
wire [TAPCNTRWIDTH+1:0] left_center = {1'b0, SCANFROMRIGHT == 1 ? window_center_r : edge_center_r};
wire [TAPCNTRWIDTH+1:0] right_center = {1'b0, SCANFROMRIGHT == 1 ? edge_center_r : window_center_r};
wire [TAPCNTRWIDTH+1:0] diff_ns = right_center >= left_center
? right_center - left_center
: right_center + TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - left_center;
reg [TAPCNTRWIDTH+1:0] diff_r;
always @(posedge clk) diff_r <= #TCQ diff_ns;
output [TAPCNTRWIDTH+1:0] diff;
assign diff = diff_r;
wire [TAPCNTRWIDTH+1:0] abs_diff = diff_r > TAPSPERKCLKX2[TAPCNTRWIDTH+1:0]/2
? TAPSPERKCLKX2[TAPCNTRWIDTH+1:0] - diff_r
: diff_r;
reg [TAPCNTRWIDTH+1:0] prev_ns, prev_r;
always @(posedge clk) prev_r <= #TCQ prev_ns;
always @(*) prev_ns = done_ns ? diff_r : prev_r;
input ktap_at_right_edge;
input ktap_at_left_edge;
wire centering = !(ktap_at_right_edge || ktap_at_left_edge);
wire diffs_eq = abs_diff == diff_r;
reg diffs_eq_ns, diffs_eq_r;
always @(*) diffs_eq_ns = centering && ((done_r && done_ns) ? diffs_eq : diffs_eq_r);
always @(posedge clk) diffs_eq_r <= #TCQ diffs_eq_ns;
reg edge_aligned_r;
reg prev_valid_ns, prev_valid_r;
always @(posedge clk) prev_valid_r <= #TCQ prev_valid_ns;
always @(*) prev_valid_ns = (~rst && ~ktap_at_right_edge && ~ktap_at_left_edge && ~edge_aligned_r) && prev_valid_r | done_ns;
wire indicate_alignment = ~rst && centering && done_ns;
wire edge_aligned_ns = indicate_alignment && (~|diff_r || ~diffs_eq & diffs_eq_r);
always @(posedge clk) edge_aligned_r <= #TCQ edge_aligned_ns;
reg poc_backup_r;
wire poc_backup_ns = edge_aligned_ns && abs_diff > prev_r;
always @(posedge clk) poc_backup_r <= #TCQ poc_backup_ns;
output poc_backup;
assign poc_backup = poc_backup_r;
output mmcm_lbclk_edge_aligned;
assign mmcm_lbclk_edge_aligned = edge_aligned_r;
endmodule // mig_7series_v4_2_poc_meta
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_pd.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
// prevents any noise that could happen when the phase shift clock is very
// nearly aligned to the fabric clock.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_pd #
(parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SIM_CAL_OPTION = "NONE",
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
pd_out,
// Inputs
iddr_rst, clk, kclk, mmcm_ps_clk
);
input iddr_rst;
input clk;
input kclk;
input mmcm_ps_clk;
wire q1;
IDDR #
(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
u_phase_detector
(.Q1 (q1),
.Q2 (),
.C (mmcm_ps_clk),
.CE (1'b1),
.D (kclk),
.R (iddr_rst),
.S (1'b0));
// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
reg pos_edge_samp;
generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
always @(posedge clk) pos_edge_samp <= #TCQ q1;
end else begin : eXes
reg q1_delayed;
reg rising_clk_seen;
always @(posedge mmcm_ps_clk) begin
rising_clk_seen <= 1'b0;
q1_delayed <= 1'bx;
end
always @(posedge clk) begin
rising_clk_seen = 1'b1;
if (rising_clk_seen) q1_delayed <= q1;
end
always @(posedge clk) begin
pos_edge_samp <= q1_delayed;
end
end endgenerate
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
output pd_out;
assign pd_out = pd_out_r;
endmodule // mic_7series_v4_0_poc_pd
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_tap_base.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: All your taps are belong to us.
//
//In general, this block should be able to start up with a random initialization of
//the various counters. But its probably easier, more normative and quicker time to solution
//to just initialize to zero with rst.
//
// Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For
// each MMCM tap it samples the phase detector output a programmable number of times.
// When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM
// tap begins.
//
// Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround
// for a bug in the MMCM where its output may have noise for a period following
// the PSEN.
//
// Samples are taken every other fabric clock. This is because the MMCM phase shift
// clock operates at half the fabric clock. The reason for this is unknown.
//
// At the end of the sampling period, a filtering step is implemented. samps_solid_thresh
// is the minumum number of samples that must be seen to declare a solid zero or one. If
// neithr the one and zero samples cross this threshold, then the sampple is declared fuzz.
//
// A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample
// is observed.
//
// A "run" counter is maintained. If the current sample is fuzz, or opposite polarity
// from a previous sample, then the run counter is reset. If the current sample is the
// same polarity run_polarity, then the run counter is incremented.
//
// If a run_polarity reversal or fuzz is observed and the run counter is not zero
// then the run_end strobe is pulsed.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_tap_base #
(parameter MMCM_SAMP_WAIT = 10,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter TCQ = 100,
parameter SAMPCNTRWIDTH = 8,
parameter SMWIDTH = 2,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
psincdec, psen, run, run_end, run_too_small, run_polarity,
samp_cntr, samps_hi, samps_hi_held, tap, sm, samps_zero, samps_one,
// Inputs
pd_out, clk, samples, samps_solid_thresh, psdone, rst,
poc_sample_pd
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input pd_out;
input clk;
input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
input psdone;
input rst;
localparam ONE = 1;
localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT);
reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r;
always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns;
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pd_out;
wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out;
output psincdec;
assign psincdec = 1'b1;
output psen;
reg psen_int;
assign psen = psen_int;
reg [TAPCNTRWIDTH-1:0] run_r;
reg [TAPCNTRWIDTH-1:0] run_ns;
always @(posedge clk) run_r <= #TCQ run_ns;
output [TAPCNTRWIDTH-1:0] run;
assign run = run_r;
output run_end;
reg run_end_int;
assign run_end = run_end_int;
output run_too_small;
reg run_too_small_r, run_too_small_ns;
always @(*) run_too_small_ns = run_end && (run < TAPSPERKCLK/4);
always @(posedge clk) run_too_small_r <= #TCQ run_too_small_ns;
assign run_too_small = run_too_small_r;
reg run_polarity_r;
reg run_polarity_ns;
always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns;
output run_polarity;
assign run_polarity = run_polarity_r;
reg [SAMPCNTRWIDTH-1:0] samp_cntr_r;
reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns;
always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns;
output [SAMPCNTRWIDTH-1:0] samp_cntr;
assign samp_cntr = samp_cntr_r;
reg [SAMPCNTRWIDTH:0] samps_hi_r;
reg [SAMPCNTRWIDTH:0] samps_hi_ns;
always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns;
output [SAMPCNTRWIDTH:0] samps_hi;
assign samps_hi = samps_hi_r;
reg [SAMPCNTRWIDTH:0] samps_hi_held_r;
reg [SAMPCNTRWIDTH:0] samps_hi_held_ns;
always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns;
output [SAMPCNTRWIDTH:0] samps_hi_held;
assign samps_hi_held = samps_hi_held_r;
reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r;
always @(posedge clk) tap_r <= #TCQ tap_ns;
output [TAPCNTRWIDTH-1:0] tap;
assign tap = tap_r;
reg [SMWIDTH-1:0] sm_ns;
reg [SMWIDTH-1:0] sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
output [SMWIDTH-1:0] sm;
assign sm = sm_r;
reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r;
always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns;
always @(posedge clk) samps_one_r <= #TCQ samps_one_ns;
output samps_zero, samps_one;
assign samps_zero = samps_zero_r;
assign samps_one = samps_one_r;
// Interesting corner case... what if both samps_zero and samps_one are
// hi? Could happen for small sample counts and reasonable values of
// PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment
// consistently breaks tie with samps_one_r.
wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r;
always @(*) begin
samps_zero_ns = samps_zero_r;
samps_one_ns = samps_one_r;
samps_zero_ns = samps_lo >= samps_solid_thresh;
samps_one_ns = samps_hi_r >= samps_solid_thresh;
end // always @ begin
wire new_polarity = run_polarity_ns ^ run_polarity_r;
input poc_sample_pd;
always @(*) begin
if (rst == 1'b1) begin
// RESET next states
psen_int = 1'b0;
sm_ns = /*AUTOLINK("SAMPLE")*/2'd0;
run_polarity_ns = 1'b0;
run_ns = {TAPCNTRWIDTH{1'b0}};
run_end_int = 1'b0;
samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};
samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};
tap_ns = {TAPCNTRWIDTH{1'b0}};
samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0];
samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}};
end else begin
// Default next states;
psen_int = 1'b0;
sm_ns = sm_r;
run_polarity_ns = run_polarity_r;
run_ns = run_r;
run_end_int = 1'b0;
samp_cntr_ns = samp_cntr_r;
samps_hi_ns = samps_hi_r;
tap_ns = tap_r;
samp_wait_ns = samp_wait_r;
if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0];
samps_hi_held_ns = samps_hi_held_r;
// State based actions and next states.
case (sm_r)
/*AL("SAMPLE")*/2'd0: begin
if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin
if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0];
if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1;
samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel};
samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0];
end
end
/*AL("COMPUTE")*/2'd1:begin
sm_ns = /*AK("PSEN")*/2'd2;
end
/*AL("PSEN")*/2'd2:begin
sm_ns = /*AK("PSDONE_WAIT")*/2'd3;
psen_int = 1'b1;
samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};
samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};
samps_hi_held_ns = samps_hi_r;
tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0])
? tap_r + ONE[TAPCNTRWIDTH-1:0]
: {TAPCNTRWIDTH{1'b0}};
if (run_polarity_r) begin
if (samps_zero_r) run_polarity_ns = 1'b0;
end else begin
if (samps_one_r) run_polarity_ns = 1'b1;
end
if (new_polarity) begin
run_ns ={TAPCNTRWIDTH{1'b0}};
run_end_int = 1'b1;
end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0];
end
/*AL("PSDONE_WAIT")*/2'd3:begin
samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0];
if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0;
end
endcase // case (sm_r)
end // else: !if(rst == 1'b1)
end // always @ (*)
endmodule // mig_7series_v4_2_poc_tap_base
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// verilog-autolabel-prefix: "2'd"
// End:
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_2_poc_top.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out calibration top.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_2_poc_top #
(parameter LANE_CNT_WIDTH = 2,
parameter MMCM_SAMP_WAIT = 10,
parameter PCT_SAMPS_SOLID = 95,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter TCQ = 100,
parameter CCENABLE = 0,
parameter SCANFROMRIGHT = 0,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK =112)
(/*AUTOARG*/
// Outputs
psincdec, poc_error, dbg_poc, psen, rise_lead_right,
rise_trail_right, mmcm_edge_detect_done, mmcm_lbclk_edge_aligned,
poc_backup,
// Inputs
use_noise_window, rst, psdone, poc_sample_pd, pd_out,
ninety_offsets, mmcm_edge_detect_rdy, lane, ktap_at_right_edge,
ktap_at_left_edge, clk
);
localparam SMWIDTH = 2;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v, ...
input ktap_at_left_edge; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ...
input ktap_at_right_edge; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ...
input [LANE_CNT_WIDTH-1:0] lane; // To u_poc_cc of mig_7series_v4_2_poc_cc.v
input mmcm_edge_detect_rdy; // To u_poc_meta of mig_7series_v4_2_poc_meta.v, ...
input [1:0] ninety_offsets; // To u_poc_meta of mig_7series_v4_2_poc_meta.v
input pd_out; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
input poc_sample_pd; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
input psdone; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
input rst; // To u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v, ...
input use_noise_window; // To u_poc_meta of mig_7series_v4_2_poc_meta.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [1023:0] dbg_poc; // From u_poc_cc of mig_7series_v4_2_poc_cc.v
output poc_error; // From u_poc_cc of mig_7series_v4_2_poc_cc.v
output psincdec; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
// End of automatics
/*AUTOwire*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [TAPCNTRWIDTH+1:0] diff; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
wire [TAPCNTRWIDTH:0] edge_center; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
wire [TAPCNTRWIDTH-1:0] fall_lead_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_lead_right; // From u_edge_right of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] fall_trail_right; // From u_edge_right of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] left; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
wire [TAPCNTRWIDTH-1:0] right; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
wire [TAPCNTRWIDTH-1:0] rise_lead_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_lead_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_center; // From u_edge_center of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] rise_trail_left; // From u_edge_left of mig_7series_v4_2_poc_edge_store.v
wire [TAPCNTRWIDTH-1:0] run; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire run_end; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [1:0] run_ends; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
wire run_polarity; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire run_too_small; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [SAMPCNTRWIDTH-1:0] samp_cntr; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samples; // From u_poc_cc of mig_7series_v4_2_poc_cc.v
wire [SAMPCNTRWIDTH:0] samps_hi; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samps_hi_held; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire samps_one; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [SAMPCNTRWIDTH:0] samps_solid_thresh; // From u_poc_cc of mig_7series_v4_2_poc_cc.v
wire samps_zero; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [SMWIDTH-1:0] sm; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [TAPCNTRWIDTH-1:0] tap; // From u_poc_tap_base of mig_7series_v4_2_poc_tap_base.v
wire [TAPCNTRWIDTH:0] window_center; // From u_poc_meta of mig_7series_v4_2_poc_meta.v
// End of automatics
output psen;
output [TAPCNTRWIDTH-1:0] rise_lead_right;
output [TAPCNTRWIDTH-1:0] rise_trail_right;
output mmcm_edge_detect_done;
output mmcm_lbclk_edge_aligned;
output poc_backup;
mig_7series_v4_2_poc_tap_base #
(/*AUTOINSTPARAM*/
// Parameters
.MMCM_SAMP_WAIT (MMCM_SAMP_WAIT),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SMWIDTH (SMWIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_tap_base
(/*AUTOINST*/
// Outputs
.psen (psen),
.psincdec (psincdec),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]),
.samps_hi (samps_hi[SAMPCNTRWIDTH:0]),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.samps_one (samps_one),
.samps_zero (samps_zero),
.sm (sm[SMWIDTH-1:0]),
.tap (tap[TAPCNTRWIDTH-1:0]),
// Inputs
.clk (clk),
.pd_out (pd_out),
.poc_sample_pd (poc_sample_pd),
.psdone (psdone),
.rst (rst),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]));
mig_7series_v4_2_poc_meta #
(/*AUTOINSTPARAM*/
// Parameters
.SCANFROMRIGHT (SCANFROMRIGHT),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_poc_meta
(/*AUTOINST*/
// Outputs
.diff (diff[TAPCNTRWIDTH+1:0]),
.edge_center (edge_center[TAPCNTRWIDTH:0]),
.left (left[TAPCNTRWIDTH-1:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
.right (right[TAPCNTRWIDTH-1:0]),
.run_ends (run_ends[1:0]),
.window_center (window_center[TAPCNTRWIDTH:0]),
// Inputs
.clk (clk),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.ninety_offsets (ninety_offsets[1:0]),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.use_noise_window (use_noise_window));
/*mig_7series_v4_2_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (ktap_at_@_edge),
.select1 (1'b1),)*/
mig_7series_v4_2_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_right
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_right[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_right[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_right_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v4_2_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_left
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_left[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_left[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (ktap_at_left_edge), // Templated
.select1 (1'b1), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
wire not_ktap_at_right_edge = ~ktap_at_right_edge;
wire not_ktap_at_left_edge = ~ktap_at_left_edge;
/*mig_7series_v4_2_poc_edge_store AUTO_TEMPLATE "edge_\(.*\)$" (
.\(.*\)lead (\1lead_@@"vl-bits"),
.\(.*\)trail (\1trail_@@"vl-bits"),
.select0 (not_ktap_at_right_edge),
.select1 (not_ktap_at_left_edge),)*/
mig_7series_v4_2_poc_edge_store #
(/*AUTOINSTPARAM*/
// Parameters
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TAPSPERKCLK (TAPSPERKCLK),
.TCQ (TCQ))
u_edge_center
(/*AUTOINST*/
// Outputs
.fall_lead (fall_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.fall_trail (fall_trail_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_lead (rise_lead_center[TAPCNTRWIDTH-1:0]), // Templated
.rise_trail (rise_trail_center[TAPCNTRWIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_polarity (run_polarity),
.select0 (not_ktap_at_right_edge), // Templated
.select1 (not_ktap_at_left_edge), // Templated
.tap (tap[TAPCNTRWIDTH-1:0]));
mig_7series_v4_2_poc_cc #
(/*AUTOINSTPARAM*/
// Parameters
.CCENABLE (CCENABLE),
.LANE_CNT_WIDTH (LANE_CNT_WIDTH),
.PCT_SAMPS_SOLID (PCT_SAMPS_SOLID),
.SAMPCNTRWIDTH (SAMPCNTRWIDTH),
.SAMPLES (SAMPLES),
.SMWIDTH (SMWIDTH),
.TAPCNTRWIDTH (TAPCNTRWIDTH),
.TCQ (TCQ))
u_poc_cc
(/*AUTOINST*/
// Outputs
.dbg_poc (dbg_poc[1023:0]),
.poc_error (poc_error),
.samples (samples[SAMPCNTRWIDTH:0]),
.samps_solid_thresh (samps_solid_thresh[SAMPCNTRWIDTH:0]),
// Inputs
.clk (clk),
.diff (diff[TAPCNTRWIDTH+1:0]),
.edge_center (edge_center[TAPCNTRWIDTH:0]),
.fall_lead_center (fall_lead_center[TAPCNTRWIDTH-1:0]),
.fall_lead_left (fall_lead_left[TAPCNTRWIDTH-1:0]),
.fall_lead_right (fall_lead_right[TAPCNTRWIDTH-1:0]),
.fall_trail_center (fall_trail_center[TAPCNTRWIDTH-1:0]),
.fall_trail_left (fall_trail_left[TAPCNTRWIDTH-1:0]),
.fall_trail_right (fall_trail_right[TAPCNTRWIDTH-1:0]),
.ktap_at_left_edge (ktap_at_left_edge),
.ktap_at_right_edge (ktap_at_right_edge),
.lane (lane[LANE_CNT_WIDTH-1:0]),
.left (left[TAPCNTRWIDTH-1:0]),
.mmcm_edge_detect_done (mmcm_edge_detect_done),
.mmcm_edge_detect_rdy (mmcm_edge_detect_rdy),
.mmcm_lbclk_edge_aligned (mmcm_lbclk_edge_aligned),
.poc_backup (poc_backup),
.psen (psen),
.right (right[TAPCNTRWIDTH-1:0]),
.rise_lead_center (rise_lead_center[TAPCNTRWIDTH-1:0]),
.rise_lead_left (rise_lead_left[TAPCNTRWIDTH-1:0]),
.rise_lead_right (rise_lead_right[TAPCNTRWIDTH-1:0]),
.rise_trail_center (rise_trail_center[TAPCNTRWIDTH-1:0]),
.rise_trail_left (rise_trail_left[TAPCNTRWIDTH-1:0]),
.rise_trail_right (rise_trail_right[TAPCNTRWIDTH-1:0]),
.rst (rst),
.run (run[TAPCNTRWIDTH-1:0]),
.run_end (run_end),
.run_ends (run_ends[1:0]),
.run_polarity (run_polarity),
.run_too_small (run_too_small),
.samp_cntr (samp_cntr[SAMPCNTRWIDTH-1:0]),
.samps_hi (samps_hi[SAMPCNTRWIDTH:0]),
.samps_hi_held (samps_hi_held[SAMPCNTRWIDTH:0]),
.samps_one (samps_one),
.samps_zero (samps_zero),
.sm (sm[SMWIDTH-1:0]),
.tap (tap[TAPCNTRWIDTH-1:0]),
.window_center (window_center[TAPCNTRWIDTH:0]));
endmodule // mig_7series_v4_2_poc_top
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_cmd.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
// User interface command port.
module mig_7series_v4_2_ui_cmd #
(
parameter TCQ = 100,
parameter ADDR_WIDTH = 33,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter RANKS = 4,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
rd_accepted, wr_accepted, data_buf_addr,
// Inputs
rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
);
input rst;
input clk;
input accept_ns;
input rd_buf_full;
input wr_req_16;
wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
reg app_rdy_r = 1'b0 /* synthesis syn_maxfan = 10 */;
always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
output wire app_rdy;
assign app_rdy = app_rdy_r;
input [ADDR_WIDTH-1:0] app_addr;
input [2:0] app_cmd;
input app_sz;
input app_hi_pri;
input app_en;
reg [ADDR_WIDTH-1:0] app_addr_r1 = {ADDR_WIDTH{1'b0}};
reg [ADDR_WIDTH-1:0] app_addr_r2 = {ADDR_WIDTH{1'b0}};
reg [2:0] app_cmd_r1;
reg [2:0] app_cmd_r2;
reg app_sz_r1;
reg app_sz_r2;
reg app_hi_pri_r1;
reg app_hi_pri_r2;
reg app_en_r1;
reg app_en_r2;
wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r && app_en ? app_addr : app_addr_r1;
wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
always @(posedge clk) begin
if (rst) begin
app_addr_r1 <= #TCQ {ADDR_WIDTH{1'b0}};
app_addr_r2 <= #TCQ {ADDR_WIDTH{1'b0}};
end else begin
app_addr_r1 <= #TCQ app_addr_ns1;
app_addr_r2 <= #TCQ app_addr_ns2;
end
app_cmd_r1 <= #TCQ app_cmd_ns1;
app_cmd_r2 <= #TCQ app_cmd_ns2;
app_sz_r1 <= #TCQ app_sz_ns1;
app_sz_r2 <= #TCQ app_sz_ns2;
app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
app_en_r1 <= #TCQ app_en_ns1;
app_en_r2 <= #TCQ app_en_ns2;
end // always @ (posedge clk)
wire use_addr_lcl = app_en_r2 && app_rdy_r;
output wire use_addr;
assign use_addr = use_addr_lcl;
output wire [RANK_WIDTH-1:0] rank;
output wire [BANK_WIDTH-1:0] bank;
output wire [ROW_WIDTH-1:0] row;
output wire [COL_WIDTH-1:0] col;
output wire size;
output wire [2:0] cmd;
output wire hi_priority;
/* assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];*/
generate
begin
if (MEM_ADDR_ORDER == "TG_TEST")
begin
assign col[4:0] = app_rdy_r
? app_addr_r1[0+:5]
: app_addr_r2[0+:5];
if (RANKS==1)
begin
assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+:2]
: app_addr_r2[5+3+BANK_WIDTH+:2];
assign col[COL_WIDTH-3:5] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7]
: app_addr_r2[5+3+BANK_WIDTH+2+2+:COL_WIDTH-7];
end
else
begin
assign col[COL_WIDTH-1:COL_WIDTH-2] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+:2]
: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+:2];
assign col[COL_WIDTH-3:5] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7]
: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+:COL_WIDTH-7];
end
assign row[2:0] = app_rdy_r
? app_addr_r1[5+:3]
: app_addr_r2[5+:3];
if (RANKS==1)
begin
assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+2+:2]
: app_addr_r2[5+3+BANK_WIDTH+2+:2];
assign row[ROW_WIDTH-3:3] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
: app_addr_r2[5+3+BANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
end
else
begin
assign row[ROW_WIDTH-1:ROW_WIDTH-2] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+:2]
: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+:2];
assign row[ROW_WIDTH-3:3] = app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5]
: app_addr_r2[5+3+BANK_WIDTH+RANK_WIDTH+2+2+COL_WIDTH-7+:ROW_WIDTH-5];
end
assign bank = app_rdy_r
? app_addr_r1[5+3+:BANK_WIDTH]
: app_addr_r2[5+3+:BANK_WIDTH];
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[5+3+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[5+3+BANK_WIDTH+:RANK_WIDTH];
end
else if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
begin
assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+:BANK_WIDTH];
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
end
else
begin
assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
end
end
endgenerate
/* assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];*/
assign size = app_rdy_r
? app_sz_r1
: app_sz_r2;
assign cmd = app_rdy_r
? app_cmd_r1
: app_cmd_r2;
assign hi_priority = app_rdy_r
? app_hi_pri_r1
: app_hi_pri_r2;
wire request_accepted = use_addr_lcl && app_rdy_r;
wire rd = app_cmd_r2[1:0] == 2'b01;
wire wr = app_cmd_r2[1:0] == 2'b00;
wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
wire write = wr || wr_bytes;
output wire rd_accepted;
assign rd_accepted = request_accepted && rd;
output wire wr_accepted;
assign wr_accepted = request_accepted && write;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
output wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
endmodule // ui_cmd
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_rd_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface read buffer. Re orders read data returned from the
// memory controller back to the request order.
//
// Consists of a large buffer for the data, a status RAM and two counters.
//
// The large buffer is implemented with distributed RAM in 6 bit wide,
// 1 read, 1 write mode. The status RAM is implemented with a distributed
// RAM configured as 2 bits wide 1 read/write, 1 read mode.
//
// As read requests are received from the application, the data_buf_addr
// counter supplies the data_buf_addr sent into the memory controller.
// With each read request, the counter is incremented, eventually rolling
// over. This mechanism labels each read request with an incrementing number.
//
// When the memory controller returns read data, it echos the original
// data_buf_addr with the read data.
//
// The status RAM is indexed with the same address as the data buffer
// RAM. Each word of the data buffer RAM has an associated status bit
// and "end" bit. Requests of size 1 return a data burst on two consecutive
// states. Requests of size zero return with a single assertion of rd_data_en.
//
// Upon returning data, the status and end bits are updated for each
// corresponding location in the status RAM indexed by the data_buf_addr
// echoed on the rd_data_addr field.
//
// The other side of the status and data RAMs is indexed by the rd_buf_indx.
// The rd_buf_indx constantly monitors the status bit it is currently
// pointing to. When the status becomes set to the proper state (more on
// this later) read data is returned to the application, and the rd_buf_indx
// is incremented.
//
// At rst the rd_buf_indx is initialized to zero. Data will not have been
// returned from the memory controller yet, so there is nothing to return
// to the application. Evenutally, read requests will be made, and the
// memory controller will return the corresponding data. The memory
// controller may not return this data in the request order. In which
// case, the status bit at location zero, will not indicate
// the data for request zero is ready. Eventually, the memory controller
// will return data for request zero. The data is forwarded on to the
// application, and rd_buf_indx is incremented to point to the next status
// bits and data in the buffers. The status bit will be examined, and if
// data is valid, this data will be returned as well. This process
// continues until the status bit indexed by rd_buf_indx indicates data
// is not ready. This may be because the rd_data_buf
// is empty, or that some data was returned out of order. Since rd_buf_indx
// always increments sequentially, data is always returned to the application
// in request order.
//
// Some further discussion of the status bit is in order. The rd_data_buf
// is a circular buffer. The status bit is a single bit. Distributed RAM
// supports only a single write port. The write port is consumed by
// memory controller read data updates. If a simple '1' were used to
// indicate the status, when rd_data_indx rolled over it would immediately
// encounter a one for a request that may not be ready.
//
// This problem is solved by causing read data returns to flip the
// status bit, and adding hi order bit beyond the size required to
// index the rd_data_buf. Data is considered ready when the status bit
// and this hi order bit are equal.
//
// The status RAM needs to be initialized to zero after reset. This is
// accomplished by cycling through all rd_buf_indx valus and writing a
// zero to the status bits directly following deassertion of reset. This
// mechanism is used for similar purposes
// for the wr_data_buf.
//
// When ORDERING == "STRICT", read data reordering is unnecessary. For thi
// case, most of the logic in the block is not generated.
`timescale 1 ps / 1 ps
// User interface read data.
module mig_7series_v4_2_ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,
app_ecc_single_err,
// Inputs
rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,
rd_data, ecc_multiple, ecc_single, rd_accepted
);
input rst;
input clk;
output wire ram_init_done_r;
output wire [3:0] ram_init_addr;
// rd_buf_indx points to the status and data storage rams for
// reading data out to the app.
reg [5:0] rd_buf_indx_r;
reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */;
assign ram_init_done_r = ram_init_done_r_lcl;
wire app_rd_data_valid_ns;
wire single_data;
reg [5:0] rd_buf_indx_ns;
generate begin : rd_buf_indx
wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;
// Loop through all status write addresses once after rst. Initializes
// the status and pointer RAMs.
wire ram_init_done_ns =
~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));
always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;
always @(/*AS*/rd_buf_indx_r or rst or single_data
or upd_rd_buf_indx) begin
rd_buf_indx_ns = rd_buf_indx_r;
if (rst) rd_buf_indx_ns = 6'b0;
else if (upd_rd_buf_indx) rd_buf_indx_ns =
// need to use every slot of RAMB32 if all address bits are used
rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data);
end
always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;
end
endgenerate
assign ram_init_addr = rd_buf_indx_r[3:0];
input rd_data_en;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input rd_data_offset;
input rd_data_end;
input [APP_DATA_WIDTH-1:0] rd_data;
output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */;
output reg app_rd_data_end;
output reg [APP_DATA_WIDTH-1:0] app_rd_data;
input [(2*nCK_PER_CLK)-1:0] ecc_multiple;
input [(2*nCK_PER_CLK)-1:0] ecc_single;
reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;
reg [2*nCK_PER_CLK-1:0] app_ecc_single_err_r = 'b0;
output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;
output wire [2*nCK_PER_CLK-1:0] app_ecc_single_err;
assign app_ecc_multiple_err = app_ecc_multiple_err_r;
assign app_ecc_single_err = app_ecc_single_err_r;
input rd_accepted;
output wire rd_buf_full;
output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
// Compute dimensions of read data buffer. Depending on width of
// DQ bus and DRAM CK
// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
// single write, single read, 6 bit wide mode.
localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);
localparam REMAINDER = RD_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
if (ORDERING == "STRICT") begin : strict_mode
assign app_rd_data_valid_ns = 1'b0;
assign single_data = 1'b0;
assign rd_buf_full = 1'b0;
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns =
rst
? 0
: rd_data_buf_addr_r_lcl + rd_accepted;
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
assign rd_data_buf_addr_r = rd_data_buf_addr_ns;
// app_* signals required to be registered.
if (ECC == "OFF") begin : ecc_off
always @(/*AS*/rd_data) app_rd_data = rd_data;
always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;
always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;
end
else begin : ecc_on
always @(posedge clk) app_rd_data <= #TCQ rd_data;
always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;
always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;
always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;
always @(posedge clk) app_ecc_single_err_r <= #TCQ ecc_single;
end
end
else begin : not_strict_mode
wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */;
// In configurations where read data is returned in a single fabric cycle
// the offset is always zero and we can use the bit to get a deeper
// FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH
// is set to use them all, discard the offset. Otherwise, include the
// offset.
wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ?
rd_data_addr :
{rd_data_addr, rd_data_offset};
wire [1:0] rd_status;
// Instantiate status RAM. One bit for status and one for "end".
begin : status_ram
// Turns out read to write back status is a timing path. Update
// the status in the ram on the state following the read. Bypass
// the write data into the status read path.
wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl
? rd_buf_wr_addr
: rd_buf_indx_r[4:0];
reg [4:0] status_ram_wr_addr_r;
always @(posedge clk) status_ram_wr_addr_r <=
#TCQ status_ram_wr_addr_ns;
wire [1:0] wr_status;
// Not guaranteed to write second status bit. If it is written, always
// copy in the first status bit.
reg wr_status_r1;
always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];
wire [1:0] status_ram_wr_data_ns =
ram_init_done_r_lcl
? {rd_data_end, ~(rd_data_offset
? wr_status_r1
: wr_status[0])}
: 2'b0;
reg [1:0] status_ram_wr_data_r;
always @(posedge clk) status_ram_wr_data_r <=
#TCQ status_ram_wr_data_ns;
reg rd_buf_we_r1;
always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_status),
.DOB(),
.DOC(wr_status),
.DOD(),
.DIA(status_ram_wr_data_r),
.DIB(2'b0),
.DIC(status_ram_wr_data_r),
.DID(status_ram_wr_data_r),
.ADDRA(rd_buf_indx_r[4:0]),
.ADDRB(5'b0),
.ADDRC(status_ram_wr_addr_ns),
.ADDRD(status_ram_wr_addr_r),
.WE(rd_buf_we_r1),
.WCLK(clk)
);
end // block: status_ram
wire [RAM_WIDTH-1:0] rd_buf_out_data;
begin : rd_buf
wire [RAM_WIDTH-1:0] rd_buf_in_data;
if (REMAINDER == 0)
if (ECC == "OFF")
assign rd_buf_in_data = rd_data;
else
assign rd_buf_in_data = {ecc_single, ecc_multiple, rd_data};
else
if (ECC == "OFF")
assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};
else
assign rd_buf_in_data =
{{6-REMAINDER{1'b0}}, ecc_single, ecc_multiple, rd_data};
// Dedicated copy for driving distributed RAM.
(* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */;
always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_buf_out_data[((i*6)+4)+:2]),
.DOB(rd_buf_out_data[((i*6)+2)+:2]),
.DOC(rd_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(rd_buf_in_data[((i*6)+4)+:2]),
.DIB(rd_buf_in_data[((i*6)+2)+:2]),
.DIC(rd_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_buf_indx_copy_r[4:0]),
.ADDRB(rd_buf_indx_copy_r[4:0]),
.ADDRC(rd_buf_indx_copy_r[4:0]),
.ADDRD(rd_buf_wr_addr),
.WE(rd_buf_we),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]);
wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */;
assign app_rd_data_valid_ns =
ram_init_done_r_lcl && (bypass || rd_data_rdy);
wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1];
always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns;
always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns;
assign single_data =
app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0];
wire [APP_DATA_WIDTH-1:0] app_rd_data_ns =
bypass
? rd_data
: rd_buf_out_data[APP_DATA_WIDTH-1:0];
always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns;
if (ECC != "OFF") begin : assign_app_ecc_multiple
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err_ns =
bypass
? ecc_multiple
: rd_buf_out_data[APP_DATA_WIDTH+:(2*nCK_PER_CLK)];
always @(posedge clk) app_ecc_multiple_err_r <=
#TCQ app_ecc_multiple_err_ns;
end
if (ECC != "OFF") begin : assign_app_ecc_single
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err_ns =
bypass
? ecc_single
: rd_buf_out_data[(APP_DATA_WIDTH+(2*nCK_PER_CLK))+:(2*nCK_PER_CLK)];
always @(posedge clk) app_ecc_single_err_r <=
#TCQ app_ecc_single_err_ns;
end
//Added to fix timing. The signal app_rd_data_valid has
//a very high fanout. So making a dedicated copy for usage
//with the occ_cnt counter.
(* equivalent_register_removal = "no" *)
reg app_rd_data_valid_copy;
always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns;
// Keep track of how many entries in the queue hold data.
wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version
//of the signals in ordered to fix timing
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r;
wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1;
wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1;
begin : occupied_counter
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns;
always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin
occ_cnt_ns = occ_cnt_r;
if (rst) occ_cnt_ns = 0;
else case ({rd_accepted, free_rd_buf})
2'b01 : occ_cnt_ns = occ_minus_one;
2'b10 : occ_cnt_ns = occ_plus_one;
endcase // case ({wr_data_end, new_rd_data})
end
always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH];
`ifdef MC_SVA
rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full));
rd_data_buffer_inc_dec_15: cover property (@(posedge clk)
(~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf)));
rd_data_underflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f))));
rd_data_overflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11))));
`endif
end // block: occupied_counter
// Generate the data_buf_address written into the memory controller
// for reads. Increment with each accepted read, and rollover at 0xf.
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl;
begin : data_buf_addr
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns;
always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin
rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl;
if (rst) rd_data_buf_addr_ns = 0;
else if (rd_accepted) rd_data_buf_addr_ns =
rd_data_buf_addr_r_lcl + 1;
end
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
end // block: data_buf_addr
end // block: not_strict_mode
endgenerate
endmodule // ui_rd_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack, app_ecc_single_err,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack, ecc_single
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [2*nCK_PER_CLK-1:0] ecc_single; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [2*nCK_PER_CLK-1:0] app_ecc_single_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v4_2_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v4_2_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v4_2_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.app_ecc_single_err (app_ecc_single_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v4_2_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:(2*nCK_PER_CLK)];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2021.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
|
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="xlnx_mig_7_ddr3_synth_1" LaunchDir="/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>
|
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="monir" Host="ubuntu" Pid="47613" HostCore="4" HostMemory="16273612">
</Process>
</ProcessHandle>
|
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="xlnx_mig_7_ddr3_synth_1" LaunchPart="xc7k325tffg900-2" LaunchTime="1663647219">
<File Type="VDS-TIMING-PB" Name="xlnx_mig_7_ddr3_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="xlnx_mig_7_ddr3_timing_summary_synth.rpt"/>
<File Type="RDS-RDS" Name="xlnx_mig_7_ddr3.vds"/>
<File Type="REPORTS-TCL" Name="xlnx_mig_7_ddr3_reports.tcl"/>
<File Type="PA-TCL" Name="xlnx_mig_7_ddr3.tcl"/>
<File Type="RDS-DCP" Name="xlnx_mig_7_ddr3.dcp"/>
<File Type="RDS-PROPCONSTRS" Name="xlnx_mig_7_ddr3_drc_synth.rpt"/>
<File Type="RDS-UTIL" Name="xlnx_mig_7_ddr3_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="xlnx_mig_7_ddr3_utilization_synth.pb"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_mig_7_ddr3">
<File Path="$PSRCDIR/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_mig_7_ddr3"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlnx_mig_7_ddr3">
<File Path="$PSRCDIR/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlnx_mig_7_ddr3"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2021">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
|
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
vivado -log xlnx_mig_7_ddr3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl
|
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
|
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
|
version:1
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3734326466346336326531663433323062636262633433636666633762333163:506172656e742050412070726f6a656374204944:00
eof:1116495055
|
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;";
} else {
PathVal = "/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64;/home/monir/Software/Vivado/2021.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log xlnx_mig_7_ddr3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
|
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
*** Running vivado
with args -log xlnx_mig_7_ddr3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source xlnx_mig_7_ddr3.tcl -notrace
Command: synth_design -top xlnx_mig_7_ddr3 -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 47714
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2866.703 ; gain = 0.000 ; free physical = 3961 ; free virtual = 11487
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3.v:70]
INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3_mig' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:75]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69]
Parameter TCQ bound to: 100 - type: integer
Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string
Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer
Parameter tTEMPSAMPLE bound to: 10000000 - type: integer
INFO: [Synth 8-6157] synthesizing module 'XADC' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:110147]
Parameter INIT_40 bound to: 16'b0001000000000000
Parameter INIT_41 bound to: 16'b0010111111111111
Parameter INIT_42 bound to: 16'b0000100000000000
Parameter INIT_48 bound to: 16'b0000000100000001
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000100000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter SIM_DEVICE bound to: 7SERIES - type: string
INFO: [Synth 8-6155] done synthesizing module 'XADC' (1#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:110147]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80]
Parameter TCQ bound to: 100 - type: integer
Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string
Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string
Parameter REFCLK_TYPE bound to: USE_SYSTEM_CLOCK - type: string
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter SYS_RST_PORT bound to: FALSE - type: string
Parameter RST_ACT_LOW bound to: 1 - type: integer
Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string
Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer
Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: TRUE - type: string
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
Parameter BANDWIDTH bound to: HIGH - type: string
Parameter CLKFBOUT_MULT_F bound to: 6.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 4.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter COMPENSATION bound to: INTERNAL - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.000000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (3#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (4#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57300]
INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (5#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57300]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68]
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter DIFF_TERM_SYSCLK bound to: FALSE - type: string
INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55702]
Parameter DIFF_TERM bound to: FALSE - type: string
Parameter IBUF_LOW_PWR bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (7#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55702]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78]
Parameter TCQ bound to: 100 - type: integer
Parameter CLKIN_PERIOD bound to: 5000 - type: integer
Parameter nCK_PER_CLK bound to: 4 - type: integer
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter CLKFBOUT_MULT bound to: 8 - type: integer
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
Parameter MMCM_VCO bound to: 800 - type: integer
Parameter MMCM_MULT_F bound to: 4 - type: integer
Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter RST_ACT_LOW bound to: 1 - type: integer
Parameter tCK bound to: 1250 - type: integer
Parameter MEM_TYPE bound to: DDR3 - type: string
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
Parameter BANDWIDTH bound to: HIGH - type: string
Parameter CLKFBOUT_MULT_F bound to: 4.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter COMPENSATION bound to: BUF_IN - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.000000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (8#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 8 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double
Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double
Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT4_DIVIDE bound to: 4 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
Parameter COMPENSATION bound to: INTERNAL - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.010000 - type: double
Parameter REF_JITTER2 bound to: 0.010000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (9#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
INFO: [Synth 8-6157] synthesizing module 'BUFH' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1319]
INFO: [Synth 8-6155] done synthesizing module 'BUFH' (10#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1319]
WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140]
WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141]
WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142]
WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143]
WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (11#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:72]
Parameter TCQ bound to: 100 - type: integer
Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string
Parameter PAYLOAD_WIDTH bound to: 32 - type: integer
Parameter ADDR_CMD_MODE bound to: 1T - type: string
Parameter AL bound to: 0 - type: string
Parameter BANK_WIDTH bound to: 3 - type: integer
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
Parameter BURST_MODE bound to: 8 - type: string
Parameter BURST_TYPE bound to: SEQ - type: string
Parameter CA_MIRROR bound to: OFF - type: string
Parameter CK_WIDTH bound to: 1 - type: integer
Parameter CL bound to: 11 - type: integer
Parameter COL_WIDTH bound to: 10 - type: integer
Parameter CMD_PIPE_PLUS1 bound to: ON - type: string
Parameter CS_WIDTH bound to: 1 - type: integer
Parameter CKE_WIDTH bound to: 1 - type: integer
Parameter CWL bound to: 8 - type: integer
Parameter DATA_WIDTH bound to: 32 - type: integer
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
Parameter DM_WIDTH bound to: 4 - type: integer
Parameter DQ_CNT_WIDTH bound to: 5 - type: integer
Parameter DQ_WIDTH bound to: 32 - type: integer
Parameter DQS_CNT_WIDTH bound to: 2 - type: integer
Parameter DQS_WIDTH bound to: 4 - type: integer
Parameter DRAM_TYPE bound to: DDR3 - type: string
Parameter DRAM_WIDTH bound to: 8 - type: integer
Parameter ECC bound to: OFF - type: string
Parameter ECC_WIDTH bound to: 0 - type: integer
Parameter ECC_TEST bound to: OFF - type: string
Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer
Parameter MASTER_PHY_CTL bound to: 1 - type: integer
Parameter nAL bound to: 0 - type: integer
Parameter nBANK_MACHS bound to: 4 - type: integer
Parameter nCK_PER_CLK bound to: 4 - type: integer
Parameter nCS_PER_RANK bound to: 1 - type: integer
Parameter ORDERING bound to: NORM - type: string
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
Parameter BANK_TYPE bound to: HP_IO - type: string
Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string
Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string
Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string
Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string
Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer
Parameter OUTPUT_DRV bound to: HIGH - type: string
Parameter REG_CTRL bound to: OFF - type: string
Parameter RTT_NOM bound to: 40 - type: string
Parameter RTT_WR bound to: OFF - type: string
Parameter STARVE_LIMIT bound to: 2 - type: integer
Parameter tCK bound to: 1250 - type: integer
Parameter tCKE bound to: 5000 - type: integer
Parameter tFAW bound to: 35000 - type: integer
Parameter tPRDI bound to: 1000000 - type: integer
Parameter tRAS bound to: 34000 - type: integer
Parameter tRCD bound to: 13910 - type: integer
Parameter tREFI bound to: 7800000 - type: integer
Parameter tRFC bound to: 260000 - type: integer
Parameter tRP bound to: 13910 - type: integer
Parameter tRRD bound to: 6000 - type: integer
Parameter tRTP bound to: 7500 - type: integer
Parameter tWTR bound to: 7500 - type: integer
Parameter tZQI bound to: 128000000 - type: integer
Parameter tZQCS bound to: 64 - type: integer
Parameter USER_REFRESH bound to: OFF - type: string
Parameter TEMP_MON_EN bound to: ON - type: string
Parameter WRLVL bound to: ON - type: string
Parameter DEBUG_PORT bound to: OFF - type: string
Parameter CAL_WIDTH bound to: HALF - type: string
Parameter RANK_WIDTH bound to: 1 - type: integer
Parameter RANKS bound to: 1 - type: integer
Parameter ODT_WIDTH bound to: 1 - type: integer
Parameter ROW_WIDTH bound to: 15 - type: integer
Parameter ADDR_WIDTH bound to: 29 - type: integer
Parameter APP_MASK_WIDTH bound to: 32 - type: integer
Parameter APP_DATA_WIDTH bound to: 256 - type: integer
Parameter BYTE_LANES_B0 bound to: 4'b1111
Parameter BYTE_LANES_B1 bound to: 4'b1111
Parameter BYTE_LANES_B2 bound to: 4'b0000
Parameter BYTE_LANES_B3 bound to: 4'b0000
Parameter BYTE_LANES_B4 bound to: 4'b0000
Parameter DATA_CTL_B0 bound to: 4'b1111
Parameter DATA_CTL_B1 bound to: 4'b0000
Parameter DATA_CTL_B2 bound to: 4'b0000
Parameter DATA_CTL_B3 bound to: 4'b0000
Parameter DATA_CTL_B4 bound to: 4'b0000
Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111
Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011
Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000
Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011
Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100
Parameter CAS_MAP bound to: 12'b000100100010
Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000
Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
Parameter CKE_ODT_AUX bound to: FALSE - type: string
Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
Parameter PARITY_MAP bound to: 12'b000000000000
Parameter RAS_MAP bound to: 12'b000100100011
Parameter WE_MAP bound to: 12'b000100000001
Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter SLOT_0_CONFIG bound to: 8'b00000001
Parameter SLOT_1_CONFIG bound to: 8'b00000000
Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string
Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000
Parameter CALIB_COL_ADD bound to: 12'b000000000000
Parameter CALIB_BA_ADD bound to: 3'b000
Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string
Parameter REFCLK_FREQ bound to: 200.000000 - type: double
Parameter USE_CS_PORT bound to: 1 - type: integer
Parameter USE_DM_PORT bound to: 1 - type: integer
Parameter USE_ODT_PORT bound to: 1 - type: integer
Parameter IDELAY_ADJ bound to: ON - type: string
Parameter FINE_PER_BIT bound to: ON - type: string
Parameter CENTER_COMP_MODE bound to: ON - type: string
Parameter PI_VAL_ADJ bound to: ON - type: string
Parameter SKIP_CALIB bound to: FALSE - type: string
Parameter TAPSPERKCLK bound to: 56 - type: integer
Parameter C_S_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 30 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer
Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string
Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000
Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000
Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer
Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer
Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer
Parameter FPGA_VOLT_TYPE bound to: N - type: string
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79]
INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106149]
INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (12#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106149]
WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509]
WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (13#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72]
WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (14#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181]
WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (14#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (15#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (16#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74]
WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (17#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (18#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (19#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (22#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75]
WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680]
WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681]
WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (24#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (25#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72]
WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670]
WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88]
INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:98066]
INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (26#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:98066]
WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (27#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (28#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71221]
INFO: [Synth 8-6155] done synthesizing module 'OBUF' (29#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71221]
INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71572]
INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (30#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71572]
INFO: [Synth 8-6157] synthesizing module 'IOBUF_DCIEN' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:60054]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF_DCIEN' (31#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:60054]
INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59893]
INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' (32#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59893]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_pd' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70]
INFO: [Synth 8-6157] synthesizing module 'IDDR' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57178]
INFO: [Synth 8-6155] done synthesizing module 'IDDR' (33#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57178]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_pd' (34#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (35#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (35#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462]
WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (36#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (36#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89083]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (37#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89083]
INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59667]
INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (38#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59667]
INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (39#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (40#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6157] synthesizing module 'IDELAYE2_FINEDELAY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57355]
INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2_FINEDELAY' (41#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57355]
INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62115]
INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (42#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62115]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (43#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (43#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6157] synthesizing module 'ODDR' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:74749]
INFO: [Synth 8-6155] done synthesizing module 'ODDR' (44#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:74749]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (45#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1344]
INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (47#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1344]
INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (48#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557]
INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89295]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (49#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89295]
WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737]
WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738]
WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71235]
INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (51#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71235]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL__parameterized0' (51#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557]
WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737]
WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738]
WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (52#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70]
WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671]
WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679]
WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579]
WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579]
WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731]
WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (53#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797]
WARNING: [Synth 8-5856] 3D RAM wl_corse_cnt_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM wl_dqs_tap_count_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790]
WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791]
WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[2] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[3] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[2] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[3] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (54#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68]
WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (55#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69]
WARNING: [Synth 8-6014] Unused sequential element oclkdelay_calib_done_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:268]
WARNING: [Synth 8-6014] Unused sequential element cmplx_stg3_left_lim_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:394]
WARNING: [Synth 8-6014] Unused sequential element cmplx_stg3_right_lim_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:409]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' (56#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_tap_base' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99]
WARNING: [Synth 8-6014] Unused sequential element pd_out_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:138]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_tap_base' (57#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_meta' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:193]
WARNING: [Synth 8-6014] Unused sequential element prev_valid_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:281]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_meta' (58#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_edge_store' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_edge_store' (59#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_cc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75]
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_cc' (60#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_top' (61#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_mux' (62#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v:72]
WARNING: [Synth 8-6014] Unused sequential element second_half_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:170]
WARNING: [Synth 8-3936] Found unconnected internal register 'word_shifted_reg' and it is trimmed from '32' to '8' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:190]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_data' (63#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:120]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_samp' (64#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v:109]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:184]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_edge' (65#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:91]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_cntlr' (66#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v:82]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:420]
WARNING: [Synth 8-6014] Unused sequential element phy_rddata_en_3_second_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:359]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_po_cntlr' (67#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:105]
WARNING: [Synth 8-3848] Net dbg_oclkdelay_rd_data in module/entity mig_7series_v4_2_ddr_phy_oclkdelay_cal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:207]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' (68#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69]
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v:691]
WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v:131]
WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746]
WARNING: [Synth 8-5856] 3D RAM dlyval_dq_reg_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM idelay_tap_cnt_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM rdlvl_dqs_tap_cnt_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691]
WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940]
WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941]
WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044]
WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696]
WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697]
WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:1152]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203]
WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273]
WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228]
WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230]
WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232]
WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276]
WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367]
WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130]
WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155]
WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673]
WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662]
WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_calib_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:183]
WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315]
WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555]
WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500]
WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:753]
WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:755]
WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:757]
WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:759]
WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:762]
WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:765]
WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:767]
WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:770]
WARNING: [Synth 8-3848] Net device_temp_i in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:783]
WARNING: [Synth 8-3848] Net clk_ref_p in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:779]
WARNING: [Synth 8-3848] Net clk_ref_n in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:780]
WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load
WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized8 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized8 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized10 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized10 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized9 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized9 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized7 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized7 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_modified in module mig_7series_v4_2_ddr_r_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_r_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AUSER[0] in module mig_7series_v4_2_ddr_a_upsizer__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_w_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AUSER[0] in module mig_7series_v4_2_ddr_a_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3006.703 ; gain = 140.000 ; free physical = 3986 ; free virtual = 11534
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3018.578 ; gain = 151.875 ; free physical = 3935 ; free virtual = 11515
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3018.578 ; gain = 151.875 ; free physical = 3935 ; free virtual = 11515
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3021.547 ; gain = 0.000 ; free physical = 3894 ; free virtual = 11467
INFO: [Netlist 29-17] Analyzing 442 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc]
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:544]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:551]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_mig_7_ddr3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_mig_7_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3157.219 ; gain = 0.000 ; free physical = 3723 ; free virtual = 11281
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 159 instances were transformed.
IBUFGDS => IBUFDS: 1 instance
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 96 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3160.188 ; gain = 2.969 ; free physical = 3723 ; free virtual = 11282
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 3160.188 ; gain = 293.484 ; free physical = 3954 ; free virtual = 11534
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT_IDLE | 0001 | 000
REQUEST_READ_TEMP | 1000 | 001
WAIT_FOR_READ | 0100 | 010
READ | 0010 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
WL_IDLE | 01110 | 00000
WL_INIT | 10010 | 00001
WL_INIT_FINE_INC | 01100 | 00010
WL_INIT_FINE_INC_WAIT1 | 01000 | 00011
WL_INIT_FINE_INC_WAIT | 01001 | 00100
WL_INIT_FINE_DEC | 11001 | 00101
WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001
WL_INIT_FINE_DEC_WAIT | 11000 | 00110
WL_WAIT | 00110 | 01000
WL_EDGE_CHECK | 11011 | 01001
WL_DQS_CNT | 10100 | 01011
WL_FINE_DEC | 00000 | 01110
WL_FINE_DEC_WAIT1 | 00001 | 11010
WL_FINE_DEC_WAIT | 10001 | 01111
WL_CORSE_DEC | 10110 | 10100
WL_CORSE_DEC_WAIT | 11010 | 10101
WL_CORSE_DEC_WAIT1 | 10101 | 10110
WL_2RANK_DQS_CNT | 00010 | 01101
WL_DQS_CHECK | 00011 | 01010
WL_FINE_INC | 01101 | 00111
WL_FINE_INC_WAIT | 10011 | 10111
WL_2RANK_FINAL_TAP | 01111 | 11000
WL_CORSE_INC | 01011 | 10000
WL_CORSE_INC_WAIT_TMP | 10000 | 11011
WL_CORSE_INC_WAIT | 01010 | 10001
WL_CORSE_INC_WAIT1 | 00111 | 10010
WL_CORSE_INC_WAIT2 | 00101 | 10011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_poc_tap_base'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 000 | 000
iSTATE5 | 001 | 001
iSTATE0 | 010 | 010
iSTATE1 | 011 | 011
iSTATE2 | 100 | 100
iSTATE3 | 101 | 101
iSTATE4 | 110 | 110
iSTATE6 | 111 | 111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_ocd_cntlr'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FINE_ADJ_IDLE | 0000 | 0000
RST_WAIT | 0001 | 0011
FINE_ADJ_DONE | 0010 | 1111
RST_POSTWAIT | 0011 | 0001
RST_POSTWAIT1 | 0100 | 0010
FINE_ADJ_INIT | 0101 | 0100
FINE_INC | 0110 | 0101
FINE_INC_WAIT | 0111 | 0110
FINE_INC_PREWAIT | 1000 | 0111
DETECT_PREWAIT | 1001 | 1000
DETECT_DQSFOUND | 1010 | 1001
FINE_DEC | 1011 | 1011
FINE_DEC_WAIT | 1100 | 1100
FINE_DEC_PREWAIT | 1101 | 1101
FINAL_WAIT | 1110 | 1110
PRECH_WAIT | 1111 | 1010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
CAL1_IDLE | 000000000000000000000000000000000100 | 000000
CAL1_NEW_DQS_WAIT | 000000000000000000000100000000000000 | 000001
CAL1_STORE_FIRST_WAIT | 000000000000000000100000000000000000 | 000010
CAL1_PAT_DETECT | 000000000000001000000000000000000000 | 000011
CAL1_DQ_IDEL_TAP_INC | 000000000000000000000000000000100000 | 000100
CAL1_DQ_IDEL_TAP_INC_WAIT | 000000000000000000000000000001000000 | 000101
CAL1_MPR_PAT_DETECT | 000000000000000000000000100000000000 | 011111
CAL1_VALID_WAIT | 100000000000000000000000000000000000 | 011110
CAL1_DETECT_EDGE | 000100000000000000000000000000000000 | 001000
CAL1_CALC_IDEL | 000000100000000000000000000000000000 | 001011
CAL1_CENTER_WAIT | 000000000000000000000000000000001000 | 100010
CAL1_IDEL_DEC_CPT | 000000000000000000000000000000010000 | 001100
CAL1_DQ_IDEL_TAP_DEC | 000000000000000000010000000000000000 | 000110
CAL1_DQ_IDEL_TAP_DEC_WAIT | 001000000000000000000000000000000000 | 000111
CAL1_NEXT_DQS | 000000000000000000000000000010000000 | 001110
CAL1_REGL_LOAD | 000000000000000000000000000100000000 | 011011
CAL1_DONE | 000000000000000000000000000000000001 | 001111
iSTATE | 000000000000000000000000000000000010 | 111111
CAL1_NEW_DQS_PREWAIT | 000000000000000000000000001000000000 | 100000
CAL1_MPR_NEW_DQS_WAIT | 000000000000000000000000010000000000 | 011101
CAL1_IDEL_DEC_CPT_WAIT | 000000000000000000001000000000000000 | 001101
CAL1_RD_STOP_FOR_PI_INC | 000000000000000000000001000000000000 | 100001
CAL1_IDEL_INC_CPT | 000000000000000000000010000000000000 | 001001
CAL1_IDEL_INC_CPT_WAIT | 000010000000000000000000000000000000 | 001010
CAL1_RDLVL_ERR | 000000000000010000000000000000000000 | 011100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
IDLE | 00000000001 | 00000000001
INIT | 00000000010 | 00000000010
NEUTRAL | 00001000000 | 00001000000
ONE_DEC | 00010000000 | 00010000000
TWO_DEC | 00100000000 | 00100000000
THREE_DEC | 01000000000 | 01000000000
FOUR_DEC | 10000000000 | 10000000000
ONE_INC | 00000100000 | 00000100000
TWO_INC | 00000010000 | 00000010000
THREE_INC | 00000001000 | 00000001000
FOUR_INC | 00000000100 | 00000000100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
ZERO | 11 | 10
ONE | 01 | 11
TWO | 00 | 01
iSTATE | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:06 ; elapsed = 00:01:28 . Memory (MB): peak = 3164.105 ; gain = 297.402 ; free physical = 166 ; free virtual = 6807
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
3 Input 32 Bit Adders := 5
2 Input 30 Bit Adders := 2
3 Input 18 Bit Adders := 1
2 Input 18 Bit Adders := 1
2 Input 17 Bit Adders := 1
2 Input 13 Bit Adders := 1
2 Input 12 Bit Adders := 16
2 Input 11 Bit Adders := 2
2 Input 10 Bit Adders := 10
2 Input 9 Bit Adders := 4
2 Input 8 Bit Adders := 16
3 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 11
3 Input 7 Bit Adders := 4
2 Input 6 Bit Adders := 60
3 Input 6 Bit Adders := 34
4 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 51
2 Input 4 Bit Adders := 40
2 Input 3 Bit Adders := 34
3 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 57
3 Input 2 Bit Adders := 3
4 Input 2 Bit Adders := 5
5 Input 2 Bit Adders := 1
8 Input 2 Bit Adders := 1
2 Input 1 Bit Adders := 4
3 Input 1 Bit Adders := 1
4 Input 1 Bit Adders := 1
5 Input 1 Bit Adders := 1
6 Input 1 Bit Adders := 1
7 Input 1 Bit Adders := 1
8 Input 1 Bit Adders := 1
9 Input 1 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 22
+---Registers :
288 Bit Registers := 1
265 Bit Registers := 2
256 Bit Registers := 6
160 Bit Registers := 1
88 Bit Registers := 1
80 Bit Registers := 4
66 Bit Registers := 2
64 Bit Registers := 4
60 Bit Registers := 1
32 Bit Registers := 8
30 Bit Registers := 11
29 Bit Registers := 2
24 Bit Registers := 10
18 Bit Registers := 2
17 Bit Registers := 1
16 Bit Registers := 9
15 Bit Registers := 11
14 Bit Registers := 1
13 Bit Registers := 1
12 Bit Registers := 32
11 Bit Registers := 2
10 Bit Registers := 8
9 Bit Registers := 20
8 Bit Registers := 41
7 Bit Registers := 9
6 Bit Registers := 162
5 Bit Registers := 63
4 Bit Registers := 106
3 Bit Registers := 80
2 Bit Registers := 85
1 Bit Registers := 2040
+---ROMs :
ROMs := 1
+---Muxes :
4 Input 800 Bit Muxes := 2
2 Input 800 Bit Muxes := 1
2 Input 265 Bit Muxes := 1
2 Input 256 Bit Muxes := 11
4 Input 256 Bit Muxes := 1
2 Input 255 Bit Muxes := 1
2 Input 80 Bit Muxes := 12
2 Input 64 Bit Muxes := 2
4 Input 64 Bit Muxes := 2
2 Input 60 Bit Muxes := 1
2 Input 41 Bit Muxes := 2
24 Input 36 Bit Muxes := 1
2 Input 36 Bit Muxes := 23
2 Input 32 Bit Muxes := 9
2 Input 30 Bit Muxes := 40
4 Input 30 Bit Muxes := 8
2 Input 29 Bit Muxes := 1
2 Input 24 Bit Muxes := 26
10 Input 24 Bit Muxes := 2
2 Input 22 Bit Muxes := 8
4 Input 18 Bit Muxes := 1
4 Input 17 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
3 Input 15 Bit Muxes := 1
2 Input 15 Bit Muxes := 8
4 Input 15 Bit Muxes := 1
8 Input 15 Bit Muxes := 1
2 Input 14 Bit Muxes := 1
15 Input 14 Bit Muxes := 1
3 Input 13 Bit Muxes := 2
2 Input 12 Bit Muxes := 3
3 Input 12 Bit Muxes := 2
7 Input 11 Bit Muxes := 1
6 Input 11 Bit Muxes := 1
5 Input 11 Bit Muxes := 1
12 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 1
2 Input 10 Bit Muxes := 8
3 Input 10 Bit Muxes := 1
4 Input 10 Bit Muxes := 1
4 Input 9 Bit Muxes := 11
2 Input 9 Bit Muxes := 36
2 Input 8 Bit Muxes := 137
5 Input 8 Bit Muxes := 1
6 Input 8 Bit Muxes := 1
4 Input 8 Bit Muxes := 1
8 Input 8 Bit Muxes := 2
2 Input 7 Bit Muxes := 72
3 Input 7 Bit Muxes := 2
4 Input 7 Bit Muxes := 4
5 Input 7 Bit Muxes := 3
2 Input 6 Bit Muxes := 154
4 Input 6 Bit Muxes := 19
3 Input 6 Bit Muxes := 4
5 Input 6 Bit Muxes := 2
23 Input 6 Bit Muxes := 6
25 Input 6 Bit Muxes := 5
16 Input 6 Bit Muxes := 1
27 Input 6 Bit Muxes := 6
2 Input 5 Bit Muxes := 49
8 Input 5 Bit Muxes := 9
4 Input 5 Bit Muxes := 4
5 Input 5 Bit Muxes := 2
3 Input 5 Bit Muxes := 7
25 Input 5 Bit Muxes := 1
27 Input 5 Bit Muxes := 1
58 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 87
7 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
3 Input 4 Bit Muxes := 3
8 Input 4 Bit Muxes := 1
5 Input 4 Bit Muxes := 1
32 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 106
4 Input 3 Bit Muxes := 15
10 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 2
9 Input 3 Bit Muxes := 2
8 Input 3 Bit Muxes := 2
23 Input 3 Bit Muxes := 1
25 Input 3 Bit Muxes := 1
27 Input 3 Bit Muxes := 11
2 Input 2 Bit Muxes := 100
3 Input 2 Bit Muxes := 13
8 Input 2 Bit Muxes := 9
4 Input 2 Bit Muxes := 5
5 Input 2 Bit Muxes := 2
10 Input 2 Bit Muxes := 2
23 Input 2 Bit Muxes := 6
25 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 929
3 Input 1 Bit Muxes := 39
4 Input 1 Bit Muxes := 172
8 Input 1 Bit Muxes := 19
10 Input 1 Bit Muxes := 39
15 Input 1 Bit Muxes := 28
23 Input 1 Bit Muxes := 33
7 Input 1 Bit Muxes := 1
25 Input 1 Bit Muxes := 30
5 Input 1 Bit Muxes := 1
16 Input 1 Bit Muxes := 21
27 Input 1 Bit Muxes := 35
12 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731]
WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232]
WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230]
WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[34]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[17].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[18].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[19].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[17].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[18].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[19].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[39].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:03:31 ; elapsed = 00:04:07 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 566 ; free virtual = 6492
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------------------------------+-------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------------------------+-------------+---------------+----------------+
|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT |
|mig_7series_v4_2_ddr_phy_prbs_rdlvl | dec_cnt_reg | 4096x6 | Block RAM |
|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT |
+------------------------------------+-------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 557 of /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:557]
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:36 ; elapsed = 00:04:12 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 476 ; free virtual = 6404
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:03:41 ; elapsed = 00:04:18 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 428 ; free virtual = 6378
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/dec_cnt_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:03:51 ; elapsed = 00:04:27 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 473 ; free virtual = 6407
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:03:55 ; elapsed = 00:04:31 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 487 ; free virtual = 6410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:03:55 ; elapsed = 00:04:32 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 487 ; free virtual = 6410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:58 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6411
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:03:58 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6409
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6409
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6419
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r3_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r3_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 |
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Dynamic Shift Register Report:
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | memory_reg[7] | 6 | 6 | 6 | 0 | 0 | 0 | 0 |
|dsrl__1 | memory_reg[31] | 257 | 257 | 0 | 257 | 0 | 0 | 0 |
|dsrl__2 | memory_reg[29] | 9 | 9 | 0 | 9 | 0 | 0 | 0 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----------------------+------+
| |Cell |Count |
+------+-----------------------+------+
|1 |AND2B1L | 12|
|2 |BUFG | 5|
|3 |BUFH | 1|
|4 |BUFIO | 2|
|5 |CARRY4 | 298|
|6 |IDDR | 4|
|7 |IDELAYCTRL | 2|
|8 |IDELAYE2_FINEDELAY | 32|
|9 |IN_FIFO | 4|
|10 |ISERDESE2 | 32|
|11 |LUT1 | 489|
|12 |LUT2 | 977|
|13 |LUT3 | 2283|
|14 |LUT4 | 1664|
|15 |LUT5 | 2339|
|16 |LUT6 | 3394|
|18 |MMCME2_ADV | 2|
|19 |MUXCY | 147|
|20 |MUXF7 | 17|
|21 |ODDR | 9|
|22 |OR2L | 2|
|23 |OSERDESE2 | 64|
|26 |OUT_FIFO | 8|
|28 |PHASER_IN_PHY | 4|
|29 |PHASER_OUT_PHY | 8|
|31 |PHASER_REF | 2|
|32 |PHY_CONTROL | 2|
|33 |PLLE2_ADV | 1|
|34 |RAM32M | 211|
|35 |RAM32X1D | 8|
|36 |RAMB36E1 | 1|
|37 |SRL16E | 25|
|38 |SRLC32E | 339|
|39 |XADC | 1|
|40 |XORCY | 62|
|41 |FDCE | 3|
|42 |FDPE | 96|
|43 |FDRE | 8184|
|44 |FDSE | 326|
|45 |IBUFGDS | 1|
|46 |IOBUFDS_DIFF_OUT_DCIEN | 4|
|47 |IOBUF_DCIEN | 32|
|48 |OBUF | 25|
|49 |OBUFDS | 1|
|50 |OBUFT | 4|
+------+-----------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6419
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 13 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:03:56 ; elapsed = 00:04:28 . Memory (MB): peak = 3394.809 ; gain = 386.496 ; free physical = 5315 ; free virtual = 11249
Synthesis Optimization Complete : Time (s): cpu = 00:04:05 ; elapsed = 00:04:37 . Memory (MB): peak = 3394.809 ; gain = 528.105 ; free physical = 5315 ; free virtual = 11249
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3394.809 ; gain = 0.000 ; free physical = 5309 ; free virtual = 11236
INFO: [Netlist 29-17] Analyzing 857 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3398.902 ; gain = 0.000 ; free physical = 5247 ; free virtual = 11174
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 328 instances were transformed.
(MUXCY,XORCY) => CARRY4: 45 instances
IBUFGDS => IBUFDS: 1 instance
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 211 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 8 instances
Synth Design complete, checksum: e3b7087
INFO: [Common 17-83] Releasing license: Synthesis
255 Infos, 346 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:04:13 ; elapsed = 00:04:45 . Memory (MB): peak = 3398.902 ; gain = 540.203 ; free physical = 5467 ; free virtual = 11394
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_mig_7_ddr3, cache-ID = f78e6da1d25e1c78
INFO: [Coretcl 2-1174] Renamed 215 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:18:54 2022...
|
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin
else
PATH=/home/monir/Software/Vivado/2021.2/ids_lite/ISE/bin/lin64:/home/monir/Software/Vivado/2021.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log xlnx_mig_7_ddr3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:13:41 2022
# Process ID: 47654
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1
# Command line: vivado -log xlnx_mig_7_ddr3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 800.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_mig_7_ddr3.tcl -notrace
|
#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "xlnx_mig_7_ddr3_synth_1" START { ROLLUP_AUTO }
set_param project.vivado.isBlockSynthRun true
set_msg_config -msgmgr_mode ooc_run
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7k325tffg900-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.cache/wt [current_project]
set_property parent.project_path /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property board_part digilentinc.com:genesys2:part0:1.1 [current_project]
set_property ip_output_repo /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_ip -quiet /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.srcs/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.xci
set_property used_in_implementation false [get_files -all /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
set_param ips.enableIPCacheLiteLoad 1
OPTRACE "Configure IP Cache" START { }
set cacheID [config_ip_cache -export -no_bom -dir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1 -new_name xlnx_mig_7_ddr3 -ip [get_ips xlnx_mig_7_ddr3]]
OPTRACE "Configure IP Cache" END { }
if { $cacheID == "" } {
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top xlnx_mig_7_ddr3 -part xc7k325tffg900-2 -mode out_of_context
OPTRACE "synth_design" END { }
OPTRACE "Write IP Cache" START { }
#---------------------------------------------------------
# Generate Checkpoint/Stub/Simulation Files For IP Cache
#---------------------------------------------------------
# disable binary constraint mode for IPCache checkpoints
set_param constraints.enableBinaryConstraints false
catch {
write_checkpoint -force -noxdef -rename_prefix xlnx_mig_7_ddr3_ xlnx_mig_7_ddr3.dcp
set ipCachedFiles {}
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_mig_7_ddr3_stub.v
lappend ipCachedFiles xlnx_mig_7_ddr3_stub.v
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_mig_7_ddr3_stub.vhdl
lappend ipCachedFiles xlnx_mig_7_ddr3_stub.vhdl
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_mig_7_ddr3_sim_netlist.v
lappend ipCachedFiles xlnx_mig_7_ddr3_sim_netlist.v
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ xlnx_mig_7_ddr3_sim_netlist.vhdl
lappend ipCachedFiles xlnx_mig_7_ddr3_sim_netlist.vhdl
set TIME_taken [expr [clock seconds] - $TIME_start]
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
config_ip_cache -add -dcp xlnx_mig_7_ddr3.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips xlnx_mig_7_ddr3]
}
OPTRACE "Write IP Cache" END { }
}
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
rename_ref -prefix_all xlnx_mig_7_ddr3_
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef xlnx_mig_7_ddr3.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "xlnx_mig_7_ddr3_synth_1_synth_report_utilization_0" "report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb"
OPTRACE "synth reports" END { }
if { [catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
write_verilog -force -mode synth_stub /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode synth_stub /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
write_verilog -force -mode funcsim /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
write_vhdl -force -mode funcsim /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
} else {
if { [catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.dcp
} _RESULT ] } {
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3_stub.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3_stub.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3_sim_netlist.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_sim_netlist.v
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
if { [catch {
file rename -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3_sim_netlist.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_sim_netlist.vhdl
} _RESULT ] } {
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
}
}; # end if cacheID
if {[file isdir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.ip_user_files/ip/xlnx_mig_7_ddr3]} {
catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.v /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.ip_user_files/ip/xlnx_mig_7_ddr3
}
}
if {[file isdir /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.ip_user_files/ip/xlnx_mig_7_ddr3]} {
catch {
file copy -force /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3_stub.vhdl /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.ip_user_files/ip/xlnx_mig_7_ddr3
}
}
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "xlnx_mig_7_ddr3_synth_1" END { }
|
#-----------------------------------------------------------
# Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue Sep 20 00:13:41 2022
# Process ID: 47654
# Current directory: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1
# Command line: vivado -log xlnx_mig_7_ddr3.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source xlnx_mig_7_ddr3.tcl
# Log file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.vds
# Journal file: /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/vivado.jou
# Running On: ubuntu, OS: Linux, CPU Frequency: 800.000 MHz, CPU Physical cores: 4, Host memory: 16664 MB
#-----------------------------------------------------------
source xlnx_mig_7_ddr3.tcl -notrace
Command: synth_design -top xlnx_mig_7_ddr3 -part xc7k325tffg900-2 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Device 21-403] Loading part xc7k325tffg900-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 47714
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2866.703 ; gain = 0.000 ; free physical = 3961 ; free virtual = 11487
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3.v:70]
INFO: [Synth 8-6157] synthesizing module 'xlnx_mig_7_ddr3_mig' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:75]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_tempmon' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69]
Parameter TCQ bound to: 100 - type: integer
Parameter TEMP_MON_CONTROL bound to: INTERNAL - type: string
Parameter XADC_CLK_PERIOD bound to: 5000 - type: integer
Parameter tTEMPSAMPLE bound to: 10000000 - type: integer
INFO: [Synth 8-6157] synthesizing module 'XADC' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:110147]
Parameter INIT_40 bound to: 16'b0001000000000000
Parameter INIT_41 bound to: 16'b0010111111111111
Parameter INIT_42 bound to: 16'b0000100000000000
Parameter INIT_48 bound to: 16'b0000000100000001
Parameter INIT_49 bound to: 16'b0000000000000000
Parameter INIT_4A bound to: 16'b0000000100000000
Parameter INIT_4B bound to: 16'b0000000000000000
Parameter INIT_4C bound to: 16'b0000000000000000
Parameter INIT_4D bound to: 16'b0000000000000000
Parameter INIT_4E bound to: 16'b0000000000000000
Parameter INIT_4F bound to: 16'b0000000000000000
Parameter INIT_50 bound to: 16'b1011010111101101
Parameter INIT_51 bound to: 16'b0101011111100100
Parameter INIT_52 bound to: 16'b1010000101000111
Parameter INIT_53 bound to: 16'b1100101000110011
Parameter INIT_54 bound to: 16'b1010100100111010
Parameter INIT_55 bound to: 16'b0101001011000110
Parameter INIT_56 bound to: 16'b1001010101010101
Parameter INIT_57 bound to: 16'b1010111001001110
Parameter INIT_58 bound to: 16'b0101100110011001
Parameter INIT_5C bound to: 16'b0101000100010001
Parameter SIM_DEVICE bound to: 7SERIES - type: string
INFO: [Synth 8-6155] done synthesizing module 'XADC' (1#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:110147]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_tempmon' (2#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_tempmon.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_iodelay_ctrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80]
Parameter TCQ bound to: 100 - type: integer
Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string
Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string
Parameter REFCLK_TYPE bound to: USE_SYSTEM_CLOCK - type: string
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter SYS_RST_PORT bound to: FALSE - type: string
Parameter RST_ACT_LOW bound to: 1 - type: integer
Parameter DIFF_TERM_REFCLK bound to: TRUE - type: string
Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer
Parameter REF_CLK_MMCM_IODELAY_CTRL bound to: TRUE - type: string
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
Parameter BANDWIDTH bound to: HIGH - type: string
Parameter CLKFBOUT_MULT_F bound to: 6.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 4.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT1_DIVIDE bound to: 3 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter COMPENSATION bound to: INTERNAL - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.000000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (3#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (4#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1083]
INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57300]
INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (5#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57300]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_iodelay_ctrl' (6#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_iodelay_ctrl.v:80]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_clk_ibuf' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68]
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter DIFF_TERM_SYSCLK bound to: FALSE - type: string
INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55702]
Parameter DIFF_TERM bound to: FALSE - type: string
Parameter IBUF_LOW_PWR bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (7#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:55702]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_clk_ibuf' (8#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_clk_ibuf.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_infrastructure' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78]
Parameter TCQ bound to: 100 - type: integer
Parameter CLKIN_PERIOD bound to: 5000 - type: integer
Parameter nCK_PER_CLK bound to: 4 - type: integer
Parameter SYSCLK_TYPE bound to: DIFFERENTIAL - type: string
Parameter CLKFBOUT_MULT bound to: 8 - type: integer
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
Parameter MMCM_VCO bound to: 800 - type: integer
Parameter MMCM_MULT_F bound to: 4 - type: integer
Parameter MMCM_DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter RST_ACT_LOW bound to: 1 - type: integer
Parameter tCK bound to: 1250 - type: integer
Parameter MEM_TYPE bound to: DDR3 - type: string
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
Parameter BANDWIDTH bound to: HIGH - type: string
Parameter CLKFBOUT_MULT_F bound to: 4.000000 - type: double
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT0_USE_FINE_PS bound to: TRUE - type: string
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
Parameter COMPENSATION bound to: BUF_IN - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.000000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV__parameterized0' (8#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:63510]
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
Parameter CLKFBOUT_MULT bound to: 8 - type: integer
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double
Parameter CLKOUT0_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT0_PHASE bound to: 337.500000 - type: double
Parameter CLKOUT1_DIVIDE bound to: 2 - type: integer
Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT2_DIVIDE bound to: 32 - type: integer
Parameter CLKOUT2_DUTY_CYCLE bound to: 0.062500 - type: double
Parameter CLKOUT2_PHASE bound to: 9.843750 - type: double
Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer
Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double
Parameter CLKOUT4_DIVIDE bound to: 4 - type: integer
Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT4_PHASE bound to: 168.750000 - type: double
Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double
Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double
Parameter COMPENSATION bound to: INTERNAL - type: string
Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
Parameter REF_JITTER1 bound to: 0.010000 - type: double
Parameter REF_JITTER2 bound to: 0.010000 - type: double
Parameter STARTUP_WAIT bound to: FALSE - type: string
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (9#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89397]
INFO: [Synth 8-6157] synthesizing module 'BUFH' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1319]
INFO: [Synth 8-6155] done synthesizing module 'BUFH' (10#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1319]
WARNING: [Synth 8-3848] Net ui_addn_clk_0 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:140]
WARNING: [Synth 8-3848] Net ui_addn_clk_1 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:141]
WARNING: [Synth 8-3848] Net ui_addn_clk_2 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:142]
WARNING: [Synth 8-3848] Net ui_addn_clk_3 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:143]
WARNING: [Synth 8-3848] Net ui_addn_clk_4 in module/entity mig_7series_v4_2_infrastructure does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:144]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_infrastructure' (11#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/clocking/mig_7series_v4_2_infrastructure.v:78]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_memc_ui_top_axi' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:72]
Parameter TCQ bound to: 100 - type: integer
Parameter DDR3_VDD_OP_VOLT bound to: 150 - type: string
Parameter PAYLOAD_WIDTH bound to: 32 - type: integer
Parameter ADDR_CMD_MODE bound to: 1T - type: string
Parameter AL bound to: 0 - type: string
Parameter BANK_WIDTH bound to: 3 - type: integer
Parameter BM_CNT_WIDTH bound to: 2 - type: integer
Parameter BURST_MODE bound to: 8 - type: string
Parameter BURST_TYPE bound to: SEQ - type: string
Parameter CA_MIRROR bound to: OFF - type: string
Parameter CK_WIDTH bound to: 1 - type: integer
Parameter CL bound to: 11 - type: integer
Parameter COL_WIDTH bound to: 10 - type: integer
Parameter CMD_PIPE_PLUS1 bound to: ON - type: string
Parameter CS_WIDTH bound to: 1 - type: integer
Parameter CKE_WIDTH bound to: 1 - type: integer
Parameter CWL bound to: 8 - type: integer
Parameter DATA_WIDTH bound to: 32 - type: integer
Parameter DATA_BUF_ADDR_WIDTH bound to: 5 - type: integer
Parameter DM_WIDTH bound to: 4 - type: integer
Parameter DQ_CNT_WIDTH bound to: 5 - type: integer
Parameter DQ_WIDTH bound to: 32 - type: integer
Parameter DQS_CNT_WIDTH bound to: 2 - type: integer
Parameter DQS_WIDTH bound to: 4 - type: integer
Parameter DRAM_TYPE bound to: DDR3 - type: string
Parameter DRAM_WIDTH bound to: 8 - type: integer
Parameter ECC bound to: OFF - type: string
Parameter ECC_WIDTH bound to: 0 - type: integer
Parameter ECC_TEST bound to: OFF - type: string
Parameter MC_ERR_ADDR_WIDTH bound to: 29 - type: integer
Parameter MASTER_PHY_CTL bound to: 1 - type: integer
Parameter nAL bound to: 0 - type: integer
Parameter nBANK_MACHS bound to: 4 - type: integer
Parameter nCK_PER_CLK bound to: 4 - type: integer
Parameter nCS_PER_RANK bound to: 1 - type: integer
Parameter ORDERING bound to: NORM - type: string
Parameter IBUF_LPWR_MODE bound to: OFF - type: string
Parameter BANK_TYPE bound to: HP_IO - type: string
Parameter DATA_IO_PRIM_TYPE bound to: HP_LP - type: string
Parameter DATA_IO_IDLE_PWRDWN bound to: ON - type: string
Parameter IODELAY_GRP0 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG0 - type: string
Parameter IODELAY_GRP1 bound to: XLNX_MIG_7_DDR3_IODELAY_MIG1 - type: string
Parameter FPGA_SPEED_GRADE bound to: 2 - type: integer
Parameter OUTPUT_DRV bound to: HIGH - type: string
Parameter REG_CTRL bound to: OFF - type: string
Parameter RTT_NOM bound to: 40 - type: string
Parameter RTT_WR bound to: OFF - type: string
Parameter STARVE_LIMIT bound to: 2 - type: integer
Parameter tCK bound to: 1250 - type: integer
Parameter tCKE bound to: 5000 - type: integer
Parameter tFAW bound to: 35000 - type: integer
Parameter tPRDI bound to: 1000000 - type: integer
Parameter tRAS bound to: 34000 - type: integer
Parameter tRCD bound to: 13910 - type: integer
Parameter tREFI bound to: 7800000 - type: integer
Parameter tRFC bound to: 260000 - type: integer
Parameter tRP bound to: 13910 - type: integer
Parameter tRRD bound to: 6000 - type: integer
Parameter tRTP bound to: 7500 - type: integer
Parameter tWTR bound to: 7500 - type: integer
Parameter tZQI bound to: 128000000 - type: integer
Parameter tZQCS bound to: 64 - type: integer
Parameter USER_REFRESH bound to: OFF - type: string
Parameter TEMP_MON_EN bound to: ON - type: string
Parameter WRLVL bound to: ON - type: string
Parameter DEBUG_PORT bound to: OFF - type: string
Parameter CAL_WIDTH bound to: HALF - type: string
Parameter RANK_WIDTH bound to: 1 - type: integer
Parameter RANKS bound to: 1 - type: integer
Parameter ODT_WIDTH bound to: 1 - type: integer
Parameter ROW_WIDTH bound to: 15 - type: integer
Parameter ADDR_WIDTH bound to: 29 - type: integer
Parameter APP_MASK_WIDTH bound to: 32 - type: integer
Parameter APP_DATA_WIDTH bound to: 256 - type: integer
Parameter BYTE_LANES_B0 bound to: 4'b1111
Parameter BYTE_LANES_B1 bound to: 4'b1111
Parameter BYTE_LANES_B2 bound to: 4'b0000
Parameter BYTE_LANES_B3 bound to: 4'b0000
Parameter BYTE_LANES_B4 bound to: 4'b0000
Parameter DATA_CTL_B0 bound to: 4'b1111
Parameter DATA_CTL_B1 bound to: 4'b0000
Parameter DATA_CTL_B2 bound to: 4'b0000
Parameter DATA_CTL_B3 bound to: 4'b0000
Parameter DATA_CTL_B4 bound to: 4'b0000
Parameter PHY_0_BITLANES bound to: 48'b001111111110001111111110001111111110001011111111
Parameter PHY_1_BITLANES bound to: 48'b001111111110111111111100110000010000000000000011
Parameter PHY_2_BITLANES bound to: 48'b000000000000000000000000000000000000000000000000
Parameter CK_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011
Parameter ADDR_MAP bound to: 192'b000000000000000100010100000100111001000100111000000100110111000100110110000100110101000100110100000100110011000100110010000100110001000100100101000100101000000100100111000100100110000100101011
Parameter BANK_MAP bound to: 36'b000100101010000100101001000100100100
Parameter CAS_MAP bound to: 12'b000100100010
Parameter CKE_ODT_BYTE_MAP bound to: 8'b00000000
Parameter CKE_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011011
Parameter ODT_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011010
Parameter CKE_ODT_AUX bound to: FALSE - type: string
Parameter CS_MAP bound to: 120'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
Parameter PARITY_MAP bound to: 12'b000000000000
Parameter RAS_MAP bound to: 12'b000100100011
Parameter WE_MAP bound to: 12'b000100000001
Parameter DQS_BYTE_MAP bound to: 144'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001000000011
Parameter DATA0_MAP bound to: 96'b000000110001000000110010000000110011000000110100000000110101000000110110000000110111000000111000
Parameter DATA1_MAP bound to: 96'b000000100001000000100010000000100011000000100100000000100101000000100110000000100111000000101000
Parameter DATA2_MAP bound to: 96'b000000010001000000010010000000010011000000010100000000010101000000010110000000010111000000011000
Parameter DATA3_MAP bound to: 96'b000000000000000000000001000000000010000000000011000000000100000000000101000000000110000000000111
Parameter DATA4_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA5_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA6_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA7_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA8_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA9_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA10_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA11_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA12_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA13_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA14_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA15_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA16_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter DATA17_MAP bound to: 96'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter MASK0_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000001001000000011001000000101001000000111001
Parameter MASK1_MAP bound to: 108'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
Parameter SLOT_0_CONFIG bound to: 8'b00000001
Parameter SLOT_1_CONFIG bound to: 8'b00000000
Parameter MEM_ADDR_ORDER bound to: BANK_ROW_COLUMN - type: string
Parameter CALIB_ROW_ADD bound to: 16'b0000000000000000
Parameter CALIB_COL_ADD bound to: 12'b000000000000
Parameter CALIB_BA_ADD bound to: 3'b000
Parameter SIM_BYPASS_INIT_CAL bound to: OFF - type: string
Parameter REFCLK_FREQ bound to: 200.000000 - type: double
Parameter USE_CS_PORT bound to: 1 - type: integer
Parameter USE_DM_PORT bound to: 1 - type: integer
Parameter USE_ODT_PORT bound to: 1 - type: integer
Parameter IDELAY_ADJ bound to: ON - type: string
Parameter FINE_PER_BIT bound to: ON - type: string
Parameter CENTER_COMP_MODE bound to: ON - type: string
Parameter PI_VAL_ADJ bound to: ON - type: string
Parameter SKIP_CALIB bound to: FALSE - type: string
Parameter TAPSPERKCLK bound to: 56 - type: integer
Parameter C_S_AXI_ID_WIDTH bound to: 6 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 30 - type: integer
Parameter C_S_AXI_DATA_WIDTH bound to: 64 - type: integer
Parameter C_S_AXI_SUPPORTS_NARROW_BURST bound to: 0 - type: integer
Parameter C_RD_WR_ARB_ALGORITHM bound to: RD_PRI_REG - type: string
Parameter C_S_AXI_REG_EN0 bound to: 20'b00000000000000000000
Parameter C_S_AXI_REG_EN1 bound to: 20'b00000000000000000000
Parameter C_S_AXI_CTRL_ADDR_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_CTRL_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_BASEADDR bound to: 0 - type: integer
Parameter C_ECC_ONOFF_RESET_VALUE bound to: 1 - type: integer
Parameter C_ECC_CE_COUNTER_WIDTH bound to: 8 - type: integer
Parameter FPGA_VOLT_TYPE bound to: N - type: string
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mem_intfc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_mem_intfc.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_mc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_cntrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79]
INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106149]
INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (12#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:106149]
WARNING: [Synth 8-567] referenced signal 'periodic_rd_generation.periodic_rd_timer_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:509]
WARNING: [Synth 8-6014] Unused sequential element periodic_rd_generation.read_this_rank_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:487]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_cntrl' (13#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_cntrl.v:79]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_rank_common' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72]
WARNING: [Synth 8-567] referenced signal 'zq_cntrl.zq_tick' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:172]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '6' to '5' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '6' to '4' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb' (14#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-6014] Unused sequential element last_master_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:181]
WARNING: [Synth 8-3848] Net channel[0].inh_group in module/entity mig_7series_v4_2_round_robin_arb__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:153]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized0' (14#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_common' (15#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_common.v:72]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_rank_mach' (16#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_rank_mach.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_compare' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74]
WARNING: [Synth 8-3936] Found unconnected internal register 'col_addr_template_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:251]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_compare' (17#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_compare.v:74]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state' (18#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue' (19#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized0' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized1' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_state__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_state.v:141]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_queue__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_queue.v:174]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_cntrl__parameterized2' (20#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_cntrl.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_bank_common' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_common' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_common.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_mux' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_row_col' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_req_reg' and it is trimmed from '8' to '7' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:145]
WARNING: [Synth 8-3936] Found unconnected internal register 'dbl_last_master_ns_reg' and it is trimmed from '8' to '6' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:143]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_round_robin_arb__parameterized1' (21#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_round_robin_arb.v:121]
WARNING: [Synth 8-6014] Unused sequential element sent_row_or_maint_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:357]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_row_col' (22#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_row_col.v:83]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_arb_select' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75]
WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:680]
WARNING: [Synth 8-6014] Unused sequential element mc_aux_out_r_2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:681]
WARNING: [Synth 8-3848] Net col_mux.col_row_r in module/entity mig_7series_v4_2_arb_select does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:390]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_select' (23#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_select.v:75]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_arb_mux' (24#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_arb_mux.v:69]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_bank_mach' (25#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_bank_mach.v:72]
WARNING: [Synth 8-7071] port 'idle' of module 'mig_7series_v4_2_bank_mach' is unconnected for instance 'bank_mach0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670]
WARNING: [Synth 8-7023] instance 'bank_mach0' of module 'mig_7series_v4_2_bank_mach' has 74 connections declared, but only 73 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:670]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_col_mach' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88]
INFO: [Synth 8-6157] synthesizing module 'RAM32M' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:98066]
INFO: [Synth 8-6155] done synthesizing module 'RAM32M' (26#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:98066]
WARNING: [Synth 8-3936] Found unconnected internal register 'read_fifo.fifo_out_data_r_reg' and it is trimmed from '12' to '8' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:396]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_col_mach' (27#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_col_mach.v:88]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_mc' (28#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/controller/mig_7series_v4_2_mc.v:73]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-6157] synthesizing module 'OBUF' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71221]
INFO: [Synth 8-6155] done synthesizing module 'OBUF' (29#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71221]
INFO: [Synth 8-6157] synthesizing module 'OBUFT' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71572]
INFO: [Synth 8-6155] done synthesizing module 'OBUFT' (30#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71572]
INFO: [Synth 8-6157] synthesizing module 'IOBUF_DCIEN' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:60054]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF_DCIEN' (31#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:60054]
INFO: [Synth 8-6157] synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59893]
INFO: [Synth 8-6155] done synthesizing module 'IOBUFDS_DIFF_OUT_DCIEN' (32#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59893]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_pd' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70]
INFO: [Synth 8-6157] synthesizing module 'IDDR' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57178]
INFO: [Synth 8-6155] done synthesizing module 'IDDR' (33#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57178]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_pd' (34#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_pd.v:70]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7071] port 'IBUFDISABLE' of module 'IOBUFDS_DIFF_OUT_DCIEN' is unconnected for instance 'u_iobuf_dqs' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
WARNING: [Synth 8-7023] instance 'u_iobuf_dqs' of module 'IOBUFDS_DIFF_OUT_DCIEN' has 9 connections declared, but only 8 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1261]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo' (35#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_0' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1428]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized0' (35#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_1' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1445]
WARNING: [Synth 8-7071] port 'afull' of module 'mig_7series_v4_2_ddr_of_pre_fifo' is unconnected for instance 'phy_ctl_pre_fifo_2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462]
WARNING: [Synth 8-7023] instance 'phy_ctl_pre_fifo_2' of module 'mig_7series_v4_2_ddr_of_pre_fifo' has 8 connections declared, but only 7 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1462]
WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:110]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_if_post_fifo' (36#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_if_post_fifo.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_of_pre_fifo__parameterized1' (36#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-6157] synthesizing module 'PHASER_IN_PHY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89083]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_IN_PHY' (37#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89083]
INFO: [Synth 8-6157] synthesizing module 'IN_FIFO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59667]
INFO: [Synth 8-6155] done synthesizing module 'IN_FIFO' (38#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:59667]
INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY' (39#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO' (40#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6157] synthesizing module 'IDELAYE2_FINEDELAY' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57355]
INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2_FINEDELAY' (41#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:57355]
INFO: [Synth 8-6157] synthesizing module 'ISERDESE2' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62115]
INFO: [Synth 8-6155] done synthesizing module 'ISERDESE2' (42#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62115]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2' (43#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized0' (43#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6157] synthesizing module 'ODDR' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:74749]
INFO: [Synth 8-6155] done synthesizing module 'ODDR' (44#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:74749]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io' (45#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized0' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized0 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized0' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized1' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
WARNING: [Synth 8-3848] Net dummy_i5 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:269]
WARNING: [Synth 8-3848] Net dummy_i6 in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:270]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized2' (46#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1344]
INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (47#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1344]
INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL' (48#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557]
INFO: [Synth 8-6157] synthesizing module 'PHASER_REF' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89295]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_REF' (49#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89295]
WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737]
WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738]
WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6155] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89220]
INFO: [Synth 8-6157] synthesizing module 'OUT_FIFO__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6155] done synthesizing module 'OUT_FIFO__parameterized0' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75471]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
INFO: [Synth 8-6157] synthesizing module 'OSERDESE2__parameterized1' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
INFO: [Synth 8-6155] done synthesizing module 'OSERDESE2__parameterized1' (50#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:75356]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized1 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized1' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized3' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized2 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized2' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized4' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized3 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized3' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized5 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized5' (50#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71235]
INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (51#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:71235]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-3848] Net oserdes_dqts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:143]
WARNING: [Synth 8-3848] Net oserdes_dqs_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:144]
WARNING: [Synth 8-3848] Net oserdes_dqsts_buf in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:145]
WARNING: [Synth 8-3848] Net iserdes_dout in module/entity mig_7series_v4_2_ddr_byte_group_io__parameterized4 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:92]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_group_io__parameterized4' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_group_io.v:69]
WARNING: [Synth 8-6014] Unused sequential element ififo_rst_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:307]
WARNING: [Synth 8-3848] Net rclk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:147]
WARNING: [Synth 8-3848] Net pi_iserdes_rst in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:193]
WARNING: [Synth 8-3848] Net pi_fine_overflow in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:195]
WARNING: [Synth 8-3848] Net pi_counter_read_val_w in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:431]
WARNING: [Synth 8-3848] Net dqs_out_of_range in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:198]
WARNING: [Synth 8-3848] Net iserdes_clk in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:275]
WARNING: [Synth 8-3848] Net iserdes_clkdiv in module/entity mig_7series_v4_2_ddr_byte_lane__parameterized6 does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:276]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_byte_lane__parameterized6' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_byte_lane.v:70]
INFO: [Synth 8-6157] synthesizing module 'PHY_CONTROL__parameterized0' [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-6155] done synthesizing module 'PHY_CONTROL__parameterized0' (51#1) [/home/monir/Software/Vivado/2021.2/scripts/rt/data/unisim_comp.v:89311]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:1557]
WARNING: [Synth 8-6014] Unused sequential element B_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:737]
WARNING: [Synth 8-6014] Unused sequential element C_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:738]
WARNING: [Synth 8-6014] Unused sequential element D_rst_primitives_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:739]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_4lanes__parameterized0' (51#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_4lanes.v:72]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy' (52#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy.v:70]
WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1671]
WARNING: [Synth 8-689] width (12) of port connection 'pi_phase_locked_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1679]
WARNING: [Synth 8-7071] port 'of_data_a_full' of module 'mig_7series_v4_2_ddr_mc_phy' is unconnected for instance 'u_ddr_mc_phy' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579]
WARNING: [Synth 8-7023] instance 'u_ddr_mc_phy' of module 'mig_7series_v4_2_ddr_mc_phy' has 89 connections declared, but only 88 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:1579]
WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '96' to '88' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731]
WARNING: [Synth 8-3848] Net phy_data_full in module/entity mig_7series_v4_2_ddr_mc_phy_wrapper does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:227]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_mc_phy_wrapper' (53#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_calib_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:82]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:797]
WARNING: [Synth 8-5856] 3D RAM wl_corse_cnt_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM wl_dqs_tap_count_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-6014] Unused sequential element fast_cal_fine_cnt_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:790]
WARNING: [Synth 8-6014] Unused sequential element fast_cal_coarse_cnt_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:791]
WARNING: [Synth 8-6014] Unused sequential element final_corse_dec_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:792]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[1] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[2] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_smallest_reg[3] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:516]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[0] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[1] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[2] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element add_largest_reg[3] was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:517]
WARNING: [Synth 8-6014] Unused sequential element dqs_wl_po_en_stg2_c_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:628]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_wrlvl' (54#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68]
WARNING: [Synth 8-6014] Unused sequential element po_en_stg2_c_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:162]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay' (55#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69]
WARNING: [Synth 8-6014] Unused sequential element oclkdelay_calib_done_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:268]
WARNING: [Synth 8-6014] Unused sequential element cmplx_stg3_left_lim_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:394]
WARNING: [Synth 8-6014] Unused sequential element cmplx_stg3_right_lim_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:409]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_lim' (56#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_lim.v:69]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_tap_base' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99]
WARNING: [Synth 8-6014] Unused sequential element pd_out_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:138]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_tap_base' (57#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_tap_base.v:99]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_meta' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:193]
WARNING: [Synth 8-6014] Unused sequential element prev_valid_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:281]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_meta' (58#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_meta.v:106]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_edge_store' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_edge_store' (59#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_edge_store.v:68]
INFO: [Synth 8-6157] synthesizing module 'mig_7series_v4_2_poc_cc' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75]
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_cc' (60#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_cc.v:75]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_poc_top' (61#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_poc_top.v:68]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_mux' (62#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_mux.v:72]
WARNING: [Synth 8-6014] Unused sequential element second_half_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:170]
WARNING: [Synth 8-3936] Found unconnected internal register 'word_shifted_reg' and it is trimmed from '32' to '8' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:190]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_data' (63#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_data.v:120]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_samp' (64#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_samp.v:109]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:184]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_edge' (65#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_edge.v:91]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_cntlr' (66#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_cntlr.v:82]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:420]
WARNING: [Synth 8-6014] Unused sequential element phy_rddata_en_3_second_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:359]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_ocd_po_cntlr' (67#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_ocd_po_cntlr.v:105]
WARNING: [Synth 8-3848] Net dbg_oclkdelay_rd_data in module/entity mig_7series_v4_2_ddr_phy_oclkdelay_cal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:207]
INFO: [Synth 8-6155] done synthesizing module 'mig_7series_v4_2_ddr_phy_oclkdelay_cal' (68#1) [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_oclkdelay_cal.v:69]
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-6014] Unused sequential element dqsfound_retry_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v:691]
WARNING: [Synth 8-3848] Net dqsfound_retry_done in module/entity mig_7series_v4_2_ddr_phy_dqs_found_cal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_dqs_found_cal.v:131]
WARNING: [Synth 8-5974] attribute "use_dsp48" has been deprecated, please use "use_dsp" instead
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2746]
WARNING: [Synth 8-5856] 3D RAM dlyval_dq_reg_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM idelay_tap_cnt_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-5856] 3D RAM rdlvl_dqs_tap_cnt_r_reg for this pattern/configuration is not supported. This will most likely be implemented in registers
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[0].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[1].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[2].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[3].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[4].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[5].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[6].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element gen_track_left_edge[7].pb_found_first_edge_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2474]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:686]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:687]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_stg1_done_int_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:688]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r1_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:689]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:690]
WARNING: [Synth 8-6014] Unused sequential element rdlvl_last_byte_done_int_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:691]
WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:940]
WARNING: [Synth 8-6014] Unused sequential element fine_dly_dec_done_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:941]
WARNING: [Synth 8-6014] Unused sequential element regl_rank_done_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:1044]
WARNING: [Synth 8-6014] Unused sequential element cal1_state_r2_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2696]
WARNING: [Synth 8-6014] Unused sequential element cal1_state_r3_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:2697]
WARNING: [Synth 8-6014] Unused sequential element cal1_cnt_cpt_timing_r_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_rdlvl.v:610]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:1152]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:563]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:564]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:565]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:558]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:559]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:560]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:561]
WARNING: [Synth 8-6014] Unused sequential element gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r4_reg was removed. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_prbs_rdlvl.v:562]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'rd_addr' is not inferred as ram due to incorrect usage [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:203]
WARNING: [Synth 8-7186] Applying attribute ram_style = "distributed" is ignored, object 'mem_out' is not inferred as ram due to incorrect usage [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_prbs_gen.v:205]
INFO: [Synth 8-226] default block is never used [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:5273]
WARNING: [Synth 8-3936] Found unconnected internal register 'rdlvl_start_dly0_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1228]
WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230]
WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '16' to '15' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232]
WARNING: [Synth 8-3848] Net calib_aux_out in module/entity mig_7series_v4_2_ddr_phy_init does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:276]
WARNING: [Synth 8-7071] port 'complex_oclk_prech_req' of module 'mig_7series_v4_2_ddr_phy_init' is unconnected for instance 'u_ddr_phy_init' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367]
WARNING: [Synth 8-7023] instance 'u_ddr_phy_init' of module 'mig_7series_v4_2_ddr_phy_init' has 131 connections declared, but only 130 given [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:1367]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:1130]
WARNING: [Synth 8-3848] Net i in module/entity mig_7series_v4_2_ddr_phy_wrcal does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_wrcal.v:155]
WARNING: [Synth 8-3848] Net dbg_skip_cal in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:673]
WARNING: [Synth 8-3848] Net coarse_dec_err in module/entity mig_7series_v4_2_ddr_calib_top does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_calib_top.v:662]
WARNING: [Synth 8-689] width (12) of port connection 'pi_dqs_found_lanes' does not match port width (8) of module 'mig_7series_v4_2_ddr_calib_top' [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_top.v:1340]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:342]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_wr_data.v:380]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:406]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_cnt_r' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.free_rd_buf' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_minus_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.occ_plus_one' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:403]
WARNING: [Synth 8-567] referenced signal 'not_strict_mode.rd_data_buf_addr_r_lcl' should be on the sensitivity list [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ui/mig_7series_v4_2_ui_rd_data.v:432]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_ddr_axic_register_slice.v:183]
WARNING: [Synth 8-3848] Net cmd_wr_bytes in module/entity mig_7series_v4_2_axi_mc_w_channel does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_w_channel.v:96]
WARNING: [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:189]
INFO: [Synth 8-155] case statement is not full and has no default [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/axi/mig_7series_v4_2_axi_mc_r_channel.v:315]
WARNING: [Synth 8-3848] Net error in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:555]
WARNING: [Synth 8-3848] Net app_correct_en_i in module/entity mig_7series_v4_2_memc_ui_top_axi does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/ip_top/mig_7series_v4_2_memc_ui_top_axi.v:500]
WARNING: [Synth 8-3848] Net s_axi_ctrl_awvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:753]
WARNING: [Synth 8-3848] Net s_axi_ctrl_awaddr in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:755]
WARNING: [Synth 8-3848] Net s_axi_ctrl_wvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:757]
WARNING: [Synth 8-3848] Net s_axi_ctrl_wdata in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:759]
WARNING: [Synth 8-3848] Net s_axi_ctrl_bready in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:762]
WARNING: [Synth 8-3848] Net s_axi_ctrl_arvalid in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:765]
WARNING: [Synth 8-3848] Net s_axi_ctrl_araddr in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:767]
WARNING: [Synth 8-3848] Net s_axi_ctrl_rready in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:770]
WARNING: [Synth 8-3848] Net device_temp_i in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:783]
WARNING: [Synth 8-3848] Net clk_ref_p in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:779]
WARNING: [Synth 8-3848] Net clk_ref_n in module/entity xlnx_mig_7_ddr3_mig does not have driver. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/xlnx_mig_7_ddr3_mig.v:780]
WARNING: [Synth 8-7129] Port mc_app_rd_last in module mig_7series_v4_2_axi_mc_r_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port arlock[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arlock[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[3] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arcache[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[2] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[1] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port arprot[0] in module mig_7series_v4_2_axi_mc_ar_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port b_resp_rdy in module mig_7series_v4_2_axi_mc_b_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awvalid in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port w_ignore_begin in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port w_ignore_end in module mig_7series_v4_2_axi_mc_w_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[7] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[6] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[5] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axlen[4] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_wrap_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[2] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[1] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axsize[0] in module mig_7series_v4_2_axi_mc_incr_cmd is either unconnected or has no load
WARNING: [Synth 8-7129] Port axburst[0] in module mig_7series_v4_2_axi_mc_cmd_translator is either unconnected or has no load
WARNING: [Synth 8-7129] Port awlock[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awlock[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[3] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awcache[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[2] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[1] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port awprot[0] in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_wr_bytes in module mig_7series_v4_2_axi_mc_aw_channel is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized8 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized8 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized10 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized10 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized9 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized9 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized7 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized7 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module mig_7series_v4_2_ddr_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AWUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_ARUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_BUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port cmd_modified in module mig_7series_v4_2_ddr_r_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port M_AXI_RUSER[0] in module mig_7series_v4_2_ddr_r_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AUSER[0] in module mig_7series_v4_2_ddr_a_upsizer__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_WUSER[0] in module mig_7series_v4_2_ddr_w_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port S_AXI_AUSER[0] in module mig_7series_v4_2_ddr_a_upsizer is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[7] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[6] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[5] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[4] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[3] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
WARNING: [Synth 8-7129] Port ecc_multiple[2] in module mig_7series_v4_2_ui_rd_data is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 3006.703 ; gain = 140.000 ; free physical = 3986 ; free virtual = 11534
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3018.578 ; gain = 151.875 ; free physical = 3935 ; free virtual = 11515
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 3018.578 ; gain = 151.875 ; free physical = 3935 ; free virtual = 11515
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3021.547 ; gain = 0.000 ; free physical = 3894 ; free virtual = 11467
INFO: [Netlist 29-17] Analyzing 442 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3_ooc.xdc]
Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:544]
WARNING: [Designutils 20-1567] Use of 'set_multicycle_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:551]
Finished Parsing XDC File [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/xlnx_mig_7_ddr3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/xlnx_mig_7_ddr3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3157.219 ; gain = 0.000 ; free physical = 3723 ; free virtual = 11281
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 159 instances were transformed.
IBUFGDS => IBUFDS: 1 instance
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 96 instances
Constraint Validation Runtime : Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.22 . Memory (MB): peak = 3160.188 ; gain = 2.969 ; free physical = 3723 ; free virtual = 11282
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 3160.188 ; gain = 293.484 ; free physical = 3954 ; free virtual = 11534
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k325tffg900-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 3164.105 ; gain = 297.402 ; free physical = 3952 ; free virtual = 11532
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_n[0]. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc, line 27).
Applied set_property IO_BUFFER_TYPE = NONE for ddr3_ck_p[0]. (constraint file /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc, line 28).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 3164.105 ; gain = 297.402 ; free physical = 3948 ; free virtual = 11529
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'xadc_supplied_temperature.tempmon_state_reg' in module 'mig_7series_v4_2_tempmon'
INFO: [Synth 8-802] inferred FSM for state register 'wl_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_wrlvl'
INFO: [Synth 8-802] inferred FSM for state register 'sm_r_reg' in module 'mig_7series_v4_2_poc_tap_base'
INFO: [Synth 8-802] inferred FSM for state register 'sm_r_reg' in module 'mig_7series_v4_2_ddr_phy_ocd_cntlr'
INFO: [Synth 8-802] inferred FSM for state register 'fine_adj_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal'
INFO: [Synth 8-802] inferred FSM for state register 'cal1_state_r_reg' in module 'mig_7series_v4_2_ddr_phy_rdlvl'
INFO: [Synth 8-802] inferred FSM for state register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'mig_7series_v4_2_axi_mc_r_channel'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
INIT_IDLE | 0001 | 000
REQUEST_READ_TEMP | 1000 | 001
WAIT_FOR_READ | 0100 | 010
READ | 0010 | 011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'xadc_supplied_temperature.tempmon_state_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_tempmon'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
WL_IDLE | 01110 | 00000
WL_INIT | 10010 | 00001
WL_INIT_FINE_INC | 01100 | 00010
WL_INIT_FINE_INC_WAIT1 | 01000 | 00011
WL_INIT_FINE_INC_WAIT | 01001 | 00100
WL_INIT_FINE_DEC | 11001 | 00101
WL_INIT_FINE_DEC_WAIT1 | 10111 | 11001
WL_INIT_FINE_DEC_WAIT | 11000 | 00110
WL_WAIT | 00110 | 01000
WL_EDGE_CHECK | 11011 | 01001
WL_DQS_CNT | 10100 | 01011
WL_FINE_DEC | 00000 | 01110
WL_FINE_DEC_WAIT1 | 00001 | 11010
WL_FINE_DEC_WAIT | 10001 | 01111
WL_CORSE_DEC | 10110 | 10100
WL_CORSE_DEC_WAIT | 11010 | 10101
WL_CORSE_DEC_WAIT1 | 10101 | 10110
WL_2RANK_DQS_CNT | 00010 | 01101
WL_DQS_CHECK | 00011 | 01010
WL_FINE_INC | 01101 | 00111
WL_FINE_INC_WAIT | 10011 | 10111
WL_2RANK_FINAL_TAP | 01111 | 11000
WL_CORSE_INC | 01011 | 10000
WL_CORSE_INC_WAIT_TMP | 10000 | 11011
WL_CORSE_INC_WAIT | 01010 | 10001
WL_CORSE_INC_WAIT1 | 00111 | 10010
WL_CORSE_INC_WAIT2 | 00101 | 10011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'wl_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_wrlvl'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 0001 | 00
iSTATE0 | 0010 | 01
iSTATE1 | 0100 | 10
iSTATE2 | 1000 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_poc_tap_base'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
iSTATE | 000 | 000
iSTATE5 | 001 | 001
iSTATE0 | 010 | 010
iSTATE1 | 011 | 011
iSTATE2 | 100 | 100
iSTATE3 | 101 | 101
iSTATE4 | 110 | 110
iSTATE6 | 111 | 111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'sm_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_ocd_cntlr'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
FINE_ADJ_IDLE | 0000 | 0000
RST_WAIT | 0001 | 0011
FINE_ADJ_DONE | 0010 | 1111
RST_POSTWAIT | 0011 | 0001
RST_POSTWAIT1 | 0100 | 0010
FINE_ADJ_INIT | 0101 | 0100
FINE_INC | 0110 | 0101
FINE_INC_WAIT | 0111 | 0110
FINE_INC_PREWAIT | 1000 | 0111
DETECT_PREWAIT | 1001 | 1000
DETECT_DQSFOUND | 1010 | 1001
FINE_DEC | 1011 | 1011
FINE_DEC_WAIT | 1100 | 1100
FINE_DEC_PREWAIT | 1101 | 1101
FINAL_WAIT | 1110 | 1110
PRECH_WAIT | 1111 | 1010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fine_adj_state_r_reg' using encoding 'sequential' in module 'mig_7series_v4_2_ddr_phy_dqs_found_cal'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
CAL1_IDLE | 000000000000000000000000000000000100 | 000000
CAL1_NEW_DQS_WAIT | 000000000000000000000100000000000000 | 000001
CAL1_STORE_FIRST_WAIT | 000000000000000000100000000000000000 | 000010
CAL1_PAT_DETECT | 000000000000001000000000000000000000 | 000011
CAL1_DQ_IDEL_TAP_INC | 000000000000000000000000000000100000 | 000100
CAL1_DQ_IDEL_TAP_INC_WAIT | 000000000000000000000000000001000000 | 000101
CAL1_MPR_PAT_DETECT | 000000000000000000000000100000000000 | 011111
CAL1_VALID_WAIT | 100000000000000000000000000000000000 | 011110
CAL1_DETECT_EDGE | 000100000000000000000000000000000000 | 001000
CAL1_CALC_IDEL | 000000100000000000000000000000000000 | 001011
CAL1_CENTER_WAIT | 000000000000000000000000000000001000 | 100010
CAL1_IDEL_DEC_CPT | 000000000000000000000000000000010000 | 001100
CAL1_DQ_IDEL_TAP_DEC | 000000000000000000010000000000000000 | 000110
CAL1_DQ_IDEL_TAP_DEC_WAIT | 001000000000000000000000000000000000 | 000111
CAL1_NEXT_DQS | 000000000000000000000000000010000000 | 001110
CAL1_REGL_LOAD | 000000000000000000000000000100000000 | 011011
CAL1_DONE | 000000000000000000000000000000000001 | 001111
iSTATE | 000000000000000000000000000000000010 | 111111
CAL1_NEW_DQS_PREWAIT | 000000000000000000000000001000000000 | 100000
CAL1_MPR_NEW_DQS_WAIT | 000000000000000000000000010000000000 | 011101
CAL1_IDEL_DEC_CPT_WAIT | 000000000000000000001000000000000000 | 001101
CAL1_RD_STOP_FOR_PI_INC | 000000000000000000000001000000000000 | 100001
CAL1_IDEL_INC_CPT | 000000000000000000000010000000000000 | 001001
CAL1_IDEL_INC_CPT_WAIT | 000010000000000000000000000000000000 | 001010
CAL1_RDLVL_ERR | 000000000000010000000000000000000000 | 011100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'cal1_state_r_reg' using encoding 'one-hot' in module 'mig_7series_v4_2_ddr_phy_rdlvl'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
*
IDLE | 00000000001 | 00000000001
INIT | 00000000010 | 00000000010
NEUTRAL | 00001000000 | 00001000000
ONE_DEC | 00010000000 | 00010000000
TWO_DEC | 00100000000 | 00100000000
THREE_DEC | 01000000000 | 01000000000
FOUR_DEC | 10000000000 | 10000000000
ONE_INC | 00000100000 | 00000100000
TWO_INC | 00000010000 | 00000010000
THREE_INC | 00000001000 | 00000001000
FOUR_INC | 00000000100 | 00000000100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'tempmon_state_reg' in module 'mig_7series_v4_2_ddr_phy_tempmon'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
ZERO | 11 | 10
ONE | 01 | 11
TWO | 00 | 01
iSTATE | 10 | 00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'mig_7series_v4_2_axi_mc_r_channel'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:06 ; elapsed = 00:01:28 . Memory (MB): peak = 3164.105 ; gain = 297.402 ; free physical = 166 ; free virtual = 6807
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 2
3 Input 32 Bit Adders := 5
2 Input 30 Bit Adders := 2
3 Input 18 Bit Adders := 1
2 Input 18 Bit Adders := 1
2 Input 17 Bit Adders := 1
2 Input 13 Bit Adders := 1
2 Input 12 Bit Adders := 16
2 Input 11 Bit Adders := 2
2 Input 10 Bit Adders := 10
2 Input 9 Bit Adders := 4
2 Input 8 Bit Adders := 16
3 Input 8 Bit Adders := 2
2 Input 7 Bit Adders := 11
3 Input 7 Bit Adders := 4
2 Input 6 Bit Adders := 60
3 Input 6 Bit Adders := 34
4 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 51
2 Input 4 Bit Adders := 40
2 Input 3 Bit Adders := 34
3 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 57
3 Input 2 Bit Adders := 3
4 Input 2 Bit Adders := 5
5 Input 2 Bit Adders := 1
8 Input 2 Bit Adders := 1
2 Input 1 Bit Adders := 4
3 Input 1 Bit Adders := 1
4 Input 1 Bit Adders := 1
5 Input 1 Bit Adders := 1
6 Input 1 Bit Adders := 1
7 Input 1 Bit Adders := 1
8 Input 1 Bit Adders := 1
9 Input 1 Bit Adders := 1
+---XORs :
2 Input 1 Bit XORs := 22
+---Registers :
288 Bit Registers := 1
265 Bit Registers := 2
256 Bit Registers := 6
160 Bit Registers := 1
88 Bit Registers := 1
80 Bit Registers := 4
66 Bit Registers := 2
64 Bit Registers := 4
60 Bit Registers := 1
32 Bit Registers := 8
30 Bit Registers := 11
29 Bit Registers := 2
24 Bit Registers := 10
18 Bit Registers := 2
17 Bit Registers := 1
16 Bit Registers := 9
15 Bit Registers := 11
14 Bit Registers := 1
13 Bit Registers := 1
12 Bit Registers := 32
11 Bit Registers := 2
10 Bit Registers := 8
9 Bit Registers := 20
8 Bit Registers := 41
7 Bit Registers := 9
6 Bit Registers := 162
5 Bit Registers := 63
4 Bit Registers := 106
3 Bit Registers := 80
2 Bit Registers := 85
1 Bit Registers := 2040
+---ROMs :
ROMs := 1
+---Muxes :
4 Input 800 Bit Muxes := 2
2 Input 800 Bit Muxes := 1
2 Input 265 Bit Muxes := 1
2 Input 256 Bit Muxes := 11
4 Input 256 Bit Muxes := 1
2 Input 255 Bit Muxes := 1
2 Input 80 Bit Muxes := 12
2 Input 64 Bit Muxes := 2
4 Input 64 Bit Muxes := 2
2 Input 60 Bit Muxes := 1
2 Input 41 Bit Muxes := 2
24 Input 36 Bit Muxes := 1
2 Input 36 Bit Muxes := 23
2 Input 32 Bit Muxes := 9
2 Input 30 Bit Muxes := 40
4 Input 30 Bit Muxes := 8
2 Input 29 Bit Muxes := 1
2 Input 24 Bit Muxes := 26
10 Input 24 Bit Muxes := 2
2 Input 22 Bit Muxes := 8
4 Input 18 Bit Muxes := 1
4 Input 17 Bit Muxes := 1
3 Input 16 Bit Muxes := 1
3 Input 15 Bit Muxes := 1
2 Input 15 Bit Muxes := 8
4 Input 15 Bit Muxes := 1
8 Input 15 Bit Muxes := 1
2 Input 14 Bit Muxes := 1
15 Input 14 Bit Muxes := 1
3 Input 13 Bit Muxes := 2
2 Input 12 Bit Muxes := 3
3 Input 12 Bit Muxes := 2
7 Input 11 Bit Muxes := 1
6 Input 11 Bit Muxes := 1
5 Input 11 Bit Muxes := 1
12 Input 11 Bit Muxes := 1
2 Input 11 Bit Muxes := 1
2 Input 10 Bit Muxes := 8
3 Input 10 Bit Muxes := 1
4 Input 10 Bit Muxes := 1
4 Input 9 Bit Muxes := 11
2 Input 9 Bit Muxes := 36
2 Input 8 Bit Muxes := 137
5 Input 8 Bit Muxes := 1
6 Input 8 Bit Muxes := 1
4 Input 8 Bit Muxes := 1
8 Input 8 Bit Muxes := 2
2 Input 7 Bit Muxes := 72
3 Input 7 Bit Muxes := 2
4 Input 7 Bit Muxes := 4
5 Input 7 Bit Muxes := 3
2 Input 6 Bit Muxes := 154
4 Input 6 Bit Muxes := 19
3 Input 6 Bit Muxes := 4
5 Input 6 Bit Muxes := 2
23 Input 6 Bit Muxes := 6
25 Input 6 Bit Muxes := 5
16 Input 6 Bit Muxes := 1
27 Input 6 Bit Muxes := 6
2 Input 5 Bit Muxes := 49
8 Input 5 Bit Muxes := 9
4 Input 5 Bit Muxes := 4
5 Input 5 Bit Muxes := 2
3 Input 5 Bit Muxes := 7
25 Input 5 Bit Muxes := 1
27 Input 5 Bit Muxes := 1
58 Input 5 Bit Muxes := 1
2 Input 4 Bit Muxes := 87
7 Input 4 Bit Muxes := 1
10 Input 4 Bit Muxes := 1
3 Input 4 Bit Muxes := 3
8 Input 4 Bit Muxes := 1
5 Input 4 Bit Muxes := 1
32 Input 4 Bit Muxes := 1
2 Input 3 Bit Muxes := 106
4 Input 3 Bit Muxes := 15
10 Input 3 Bit Muxes := 1
3 Input 3 Bit Muxes := 2
9 Input 3 Bit Muxes := 2
8 Input 3 Bit Muxes := 2
23 Input 3 Bit Muxes := 1
25 Input 3 Bit Muxes := 1
27 Input 3 Bit Muxes := 11
2 Input 2 Bit Muxes := 100
3 Input 2 Bit Muxes := 13
8 Input 2 Bit Muxes := 9
4 Input 2 Bit Muxes := 5
5 Input 2 Bit Muxes := 2
10 Input 2 Bit Muxes := 2
23 Input 2 Bit Muxes := 6
25 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 929
3 Input 1 Bit Muxes := 39
4 Input 1 Bit Muxes := 172
8 Input 1 Bit Muxes := 19
10 Input 1 Bit Muxes := 39
15 Input 1 Bit Muxes := 28
23 Input 1 Bit Muxes := 33
7 Input 1 Bit Muxes := 1
25 Input 1 Bit Muxes := 30
5 Input 1 Bit Muxes := 1
16 Input 1 Bit Muxes := 21
27 Input 1 Bit Muxes := 35
12 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 840 (col length:140)
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-3936] Found unconnected internal register 'byte_sel_data_map_reg' and it is trimmed from '88' to '4' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_mc_phy_wrapper.v:731]
WARNING: [Synth 8-3936] Found unconnected internal register 'oclkdelay_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1232]
WARNING: [Synth 8-3936] Found unconnected internal register 'wrcal_start_dly_r_reg' and it is trimmed from '15' to '14' bits. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/rtl/phy/mig_7series_v4_2_ddr_phy_init.v:1230]
WARNING: [Synth 8-3332] Sequential element (FSM_onehot_cal1_state_r_reg[34]) is unused and will be removed from module mig_7series_v4_2_ddr_phy_rdlvl.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[17].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[18].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[19].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[17].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[18].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[19].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
WARNING: [Synth 8-3332] Sequential element (USE_READ.read_addr_inst/USE_BURSTS.cmd_queue/USE_FF_OUT.USE_FPGA_OUTPUT_PIPELINE.DATA_GEN[39].FDRE_inst) is unused and will be removed from module mig_7series_v4_2_ddr_axi_upsizer.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:03:31 ; elapsed = 00:04:07 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 566 ; free virtual = 6492
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------------------------------+-------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------------------------+-------------+---------------+----------------+
|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT |
|mig_7series_v4_2_ddr_phy_prbs_rdlvl | dec_cnt_reg | 4096x6 | Block RAM |
|mig_7series_v4_2_ddr_prbs_gen | mem_out | 256x18 | LUT |
+------------------------------------+-------------+---------------+----------------+
Distributed RAM: Preliminary Mapping Report (see note below)
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
WARNING: [Synth 8-3321] set_false_path : Empty through list for constraint at line 557 of /home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc. [/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc:557]
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:36 ; elapsed = 00:04:12 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 476 ; free virtual = 6404
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:03:41 ; elapsed = 00:04:18 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 428 ; free virtual = 6378
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
|xlnx_mig_7_ddr3 | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|xlnx_mig_7_ddr3 | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_A.ddr_byte_lane_A | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_B.ddr_byte_lane_B | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_C.ddr_byte_lane_C | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied | 4 x 80 | RAM32M x 14 |
|u_ddr_mc_phyi_2/\ddr_phy_4lanes_0.u_ddr_phy_4lanes /\ddr_byte_lane_D.ddr_byte_lane_D | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg | Implied | 16 x 80 | RAM32M x 14 |
+--------------------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------+----------------------+--------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/dec_cnt_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:03:51 ; elapsed = 00:04:27 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 473 ; free virtual = 6407
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:03:55 ; elapsed = 00:04:31 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 487 ; free virtual = 6410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:03:55 ; elapsed = 00:04:32 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 487 ; free virtual = 6410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:58 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6411
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:03:58 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6409
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6409
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6419
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] | 3 | 4 | NO | NO | YES | 4 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r7_reg | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclkdelay_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_reg | 17 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[5] | 6 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_too_small_r3_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/oclk_calib.u_ddr_phy_oclkdelay_cal/u_poc/u_poc_meta/run_end_r3_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_right.u_ddr_phy_dqs_found_cal/init_dqsfound_done_r5_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r5_reg | 5 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r9_reg | 9 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r4_reg | 4 | 1 | NO | NO | YES | 1 | 0 |
|xlnx_mig_7_ddr3 | u_xlnx_mig_7_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[11] | 12 | 1 | NO | NO | YES | 1 | 0 |
+----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Dynamic Shift Register Report:
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | memory_reg[7] | 6 | 6 | 6 | 0 | 0 | 0 | 0 |
|dsrl__1 | memory_reg[31] | 257 | 257 | 0 | 257 | 0 | 0 | 0 |
|dsrl__2 | memory_reg[29] | 9 | 9 | 0 | 9 | 0 | 0 | 0 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----------------------+------+
| |Cell |Count |
+------+-----------------------+------+
|1 |AND2B1L | 12|
|2 |BUFG | 5|
|3 |BUFH | 1|
|4 |BUFIO | 2|
|5 |CARRY4 | 298|
|6 |IDDR | 4|
|7 |IDELAYCTRL | 2|
|8 |IDELAYE2_FINEDELAY | 32|
|9 |IN_FIFO | 4|
|10 |ISERDESE2 | 32|
|11 |LUT1 | 489|
|12 |LUT2 | 977|
|13 |LUT3 | 2283|
|14 |LUT4 | 1664|
|15 |LUT5 | 2339|
|16 |LUT6 | 3394|
|18 |MMCME2_ADV | 2|
|19 |MUXCY | 147|
|20 |MUXF7 | 17|
|21 |ODDR | 9|
|22 |OR2L | 2|
|23 |OSERDESE2 | 64|
|26 |OUT_FIFO | 8|
|28 |PHASER_IN_PHY | 4|
|29 |PHASER_OUT_PHY | 8|
|31 |PHASER_REF | 2|
|32 |PHY_CONTROL | 2|
|33 |PLLE2_ADV | 1|
|34 |RAM32M | 211|
|35 |RAM32X1D | 8|
|36 |RAMB36E1 | 1|
|37 |SRL16E | 25|
|38 |SRLC32E | 339|
|39 |XADC | 1|
|40 |XORCY | 62|
|41 |FDCE | 3|
|42 |FDPE | 96|
|43 |FDRE | 8184|
|44 |FDSE | 326|
|45 |IBUFGDS | 1|
|46 |IOBUFDS_DIFF_OUT_DCIEN | 4|
|47 |IOBUF_DCIEN | 32|
|48 |OBUF | 25|
|49 |OBUFDS | 1|
|50 |OBUFT | 4|
+------+-----------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:03:59 ; elapsed = 00:04:35 . Memory (MB): peak = 3390.898 ; gain = 524.195 ; free physical = 485 ; free virtual = 6419
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 13 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:03:56 ; elapsed = 00:04:28 . Memory (MB): peak = 3394.809 ; gain = 386.496 ; free physical = 5315 ; free virtual = 11249
Synthesis Optimization Complete : Time (s): cpu = 00:04:05 ; elapsed = 00:04:37 . Memory (MB): peak = 3394.809 ; gain = 528.105 ; free physical = 5315 ; free virtual = 11249
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 3394.809 ; gain = 0.000 ; free physical = 5309 ; free virtual = 11236
INFO: [Netlist 29-17] Analyzing 857 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 4 inverter(s) to 32 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3398.902 ; gain = 0.000 ; free physical = 5247 ; free virtual = 11174
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 328 instances were transformed.
(MUXCY,XORCY) => CARRY4: 45 instances
IBUFGDS => IBUFDS: 1 instance
IOBUFDS_DIFF_OUT_DCIEN => IOBUFDS_DIFF_OUT_DCIEN (IBUFDS_IBUFDISABLE_INT(x2), INV, OBUFTDS_DCIEN(x2)): 4 instances
IOBUF_DCIEN => IOBUF_DCIEN (IBUF_IBUFDISABLE, OBUFT_DCIEN): 32 instances
LUT6_2 => LUT6_2 (LUT5, LUT6): 26 instances
OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 1 instance
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 211 instances
RAM32X1D => RAM32X1D (RAMD32(x2)): 8 instances
Synth Design complete, checksum: e3b7087
INFO: [Common 17-83] Releasing license: Synthesis
255 Infos, 346 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:04:13 ; elapsed = 00:04:45 . Memory (MB): peak = 3398.902 ; gain = 540.203 ; free physical = 5467 ; free virtual = 11394
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP xlnx_mig_7_ddr3, cache-ID = f78e6da1d25e1c78
INFO: [Coretcl 2-1174] Renamed 215 cell refs.
INFO: [Common 17-1381] The checkpoint '/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.runs/xlnx_mig_7_ddr3_synth_1/xlnx_mig_7_ddr3.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep 20 00:18:54 2022...
|
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
| Date : Tue Sep 20 00:18:52 2022
| Host : ubuntu running 64-bit Ubuntu 20.04.4 LTS
| Command : report_utilization -file xlnx_mig_7_ddr3_utilization_synth.rpt -pb xlnx_mig_7_ddr3_utilization_synth.pb
| Design : xlnx_mig_7_ddr3
| Device : xc7k325tffg900-2
| Speed File : -2
| Design State : Synthesized
-------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs* | 10570 | 0 | 0 | 203800 | 5.19 |
| LUT as Logic | 9346 | 0 | 0 | 203800 | 4.59 |
| LUT as Memory | 1224 | 0 | 0 | 64000 | 1.91 |
| LUT as Distributed RAM | 860 | 0 | | | |
| LUT as Shift Register | 364 | 0 | | | |
| Slice Registers | 8623 | 2 | 0 | 407600 | 2.12 |
| Register as Flip Flop | 8609 | 2 | 0 | 407600 | 2.11 |
| Register as Latch | 0 | 0 | 0 | 407600 | 0.00 |
| Register as AND/OR | 14 | 0 | 0 | 407600 | <0.01 |
| F7 Muxes | 17 | 0 | 0 | 101900 | 0.02 |
| F8 Muxes | 0 | 0 | 0 | 50950 | 0.00 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 14 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 96 | Yes | - | Set |
| 3 | Yes | - | Reset |
| 326 | Yes | Set | - |
| 8184 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 1 | 0 | 0 | 445 | 0.22 |
| RAMB36/FIFO* | 1 | 0 | 0 | 445 | 0.22 |
| RAMB36E1 only | 1 | | | | |
| RAMB18 | 0 | 0 | 0 | 890 | 0.00 |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+-------+
| Bonded IOB | 73 | 0 | 0 | 500 | 14.60 |
| Bonded IPADs | 0 | 0 | 0 | 50 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 32 | 0.00 |
| PHY_CONTROL | 2 | 0 | 0 | 10 | 20.00 |
| PHASER_REF | 2 | 0 | 0 | 10 | 20.00 |
| OUT_FIFO | 8 | 0 | 0 | 40 | 20.00 |
| IN_FIFO | 4 | 0 | 0 | 40 | 10.00 |
| IDELAYCTRL | 2 | 0 | 0 | 10 | 20.00 |
| IBUFDS | 1 | 0 | 0 | 480 | 0.21 |
| GTXE2_COMMON | 0 | 0 | 0 | 4 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 0 | 16 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 8 | 0 | 0 | 40 | 20.00 |
| PHASER_OUT_PHY only | 8 | 0 | | | |
| PHASER_IN/PHASER_IN_PHY | 4 | 0 | 0 | 40 | 10.00 |
| PHASER_IN_PHY only | 4 | 0 | | | |
| IDELAYE2/IDELAYE2_FINEDELAY | 32 | 0 | 0 | 500 | 6.40 |
| IDELAYE2_FINEDELAY only | 32 | 0 | | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 8 | 0.00 |
| ILOGIC | 36 | 0 | 0 | 500 | 7.20 |
| ISERDES | 32 | | 0 | 500 | |
| IDDR | 4 | | | | |
| OLOGIC | 73 | 0 | 0 | 500 | 14.60 |
| OSERDES | 64 | | 0 | 500 | |
| ODDR | 9 | | | | |
+-----------------------------+------+-------+------------+-----------+-------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 5 | 0 | 0 | 32 | 15.63 |
| BUFIO | 0 | 0 | 0 | 40 | 0.00 |
| MMCME2_ADV | 2 | 0 | 0 | 10 | 20.00 |
| PLLE2_ADV | 1 | 0 | 0 | 10 | 10.00 |
| BUFMRCE | 0 | 0 | 0 | 20 | 0.00 |
| BUFHCE | 1 | 0 | 0 | 168 | 0.60 |
| BUFR | 0 | 0 | 0 | 40 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+--------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 1 | 0 | 0 | 1 | 100.00 |
+-------------+------+-------+------------+-----------+--------+
7. Primitives
-------------
+------------------------+------+---------------------+
| Ref Name | Used | Functional Category |
+------------------------+------+---------------------+
| FDRE | 8184 | Flop & Latch |
| LUT6 | 3394 | LUT |
| LUT5 | 2365 | LUT |
| LUT3 | 2283 | LUT |
| LUT4 | 1664 | LUT |
| RAMD32 | 1282 | Distributed Memory |
| LUT2 | 977 | LUT |
| LUT1 | 485 | LUT |
| RAMS32 | 422 | Distributed Memory |
| CARRY4 | 343 | CarryLogic |
| SRLC32E | 339 | Distributed Memory |
| FDSE | 326 | Flop & Latch |
| FDPE | 96 | Flop & Latch |
| OSERDESE2 | 64 | IO |
| OBUFT_DCIEN | 32 | IO |
| ISERDESE2 | 32 | IO |
| IDELAYE2_FINEDELAY | 32 | IO |
| IBUF_IBUFDISABLE | 32 | IO |
| SRL16E | 25 | Distributed Memory |
| OBUF | 25 | IO |
| MUXF7 | 17 | MuxFx |
| AND2B1L | 12 | Others |
| ODDR | 9 | IO |
| PHASER_OUT_PHY | 8 | IO |
| OUT_FIFO | 8 | IO |
| OBUFTDS_DCIEN | 8 | IO |
| IBUFDS_IBUFDISABLE_INT | 8 | IO |
| INV | 5 | LUT |
| BUFG | 5 | Clock |
| PHASER_IN_PHY | 4 | IO |
| OBUFT | 4 | IO |
| IN_FIFO | 4 | IO |
| IDDR | 4 | IO |
| FDCE | 3 | Flop & Latch |
| PHY_CONTROL | 2 | IO |
| PHASER_REF | 2 | IO |
| OR2L | 2 | Others |
| OBUFDS | 2 | IO |
| MMCME2_ADV | 2 | Clock |
| IDELAYCTRL | 2 | IO |
| XADC | 1 | Others |
| RAMB36E1 | 1 | Block Memory |
| PLLE2_ADV | 1 | Clock |
| IBUFDS | 1 | IO |
| BUFH | 1 | Clock |
+------------------------+------+---------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
|
set_property SRC_FILE_INFO {cfile:/home/monir/research/hw-testing/cva6_mod_2_v2/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc rfile:../../../xlnx_mig_7_ddr3.gen/sources_1/ip/xlnx_mig_7_ddr3/xlnx_mig_7_ddr3/user_design/constraints/xlnx_mig_7_ddr3.xdc id:1 order:EARLY} [current_design]
set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[0]}]
set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[1]}]
set_property src_info {type:XDC file:1 line:58 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[2]}]
set_property src_info {type:XDC file:1 line:64 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[3]}]
set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[4]}]
set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[5]}]
set_property src_info {type:XDC file:1 line:82 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[6]}]
set_property src_info {type:XDC file:1 line:88 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[7]}]
set_property src_info {type:XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[8]}]
set_property src_info {type:XDC file:1 line:100 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[9]}]
set_property src_info {type:XDC file:1 line:106 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[10]}]
set_property src_info {type:XDC file:1 line:112 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[11]}]
set_property src_info {type:XDC file:1 line:118 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[12]}]
set_property src_info {type:XDC file:1 line:124 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[13]}]
set_property src_info {type:XDC file:1 line:130 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[14]}]
set_property src_info {type:XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[15]}]
set_property src_info {type:XDC file:1 line:142 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[16]}]
set_property src_info {type:XDC file:1 line:148 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[17]}]
set_property src_info {type:XDC file:1 line:154 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[18]}]
set_property src_info {type:XDC file:1 line:160 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[19]}]
set_property src_info {type:XDC file:1 line:166 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[20]}]
set_property src_info {type:XDC file:1 line:172 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[21]}]
set_property src_info {type:XDC file:1 line:178 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[22]}]
set_property src_info {type:XDC file:1 line:184 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dq[23]}]
set_property src_info {type:XDC file:1 line:190 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq[24]}]
set_property src_info {type:XDC file:1 line:196 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[25]}]
set_property src_info {type:XDC file:1 line:202 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[26]}]
set_property src_info {type:XDC file:1 line:208 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[27]}]
set_property src_info {type:XDC file:1 line:214 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[28]}]
set_property src_info {type:XDC file:1 line:220 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[29]}]
set_property src_info {type:XDC file:1 line:226 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[30]}]
set_property src_info {type:XDC file:1 line:232 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[31]}]
set_property src_info {type:XDC file:1 line:238 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH9 [get_ports {ddr3_addr[14]}]
set_property src_info {type:XDC file:1 line:244 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[13]}]
set_property src_info {type:XDC file:1 line:250 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[12]}]
set_property src_info {type:XDC file:1 line:256 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[11]}]
set_property src_info {type:XDC file:1 line:262 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[10]}]
set_property src_info {type:XDC file:1 line:268 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y11 [get_ports {ddr3_addr[9]}]
set_property src_info {type:XDC file:1 line:274 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[8]}]
set_property src_info {type:XDC file:1 line:280 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[7]}]
set_property src_info {type:XDC file:1 line:286 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[6]}]
set_property src_info {type:XDC file:1 line:292 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[5]}]
set_property src_info {type:XDC file:1 line:298 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD9 [get_ports {ddr3_addr[4]}]
set_property src_info {type:XDC file:1 line:304 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[3]}]
set_property src_info {type:XDC file:1 line:310 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[2]}]
set_property src_info {type:XDC file:1 line:316 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE8 [get_ports {ddr3_addr[1]}]
set_property src_info {type:XDC file:1 line:322 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC12 [get_ports {ddr3_addr[0]}]
set_property src_info {type:XDC file:1 line:328 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]
set_property src_info {type:XDC file:1 line:334 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB10 [get_ports {ddr3_ba[1]}]
set_property src_info {type:XDC file:1 line:340 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE9 [get_ports {ddr3_ba[0]}]
set_property src_info {type:XDC file:1 line:346 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE11 [get_ports {ddr3_ras_n}]
set_property src_info {type:XDC file:1 line:352 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF11 [get_ports {ddr3_cas_n}]
set_property src_info {type:XDC file:1 line:358 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG13 [get_ports {ddr3_we_n}]
set_property src_info {type:XDC file:1 line:364 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG5 [get_ports {ddr3_reset_n}]
set_property src_info {type:XDC file:1 line:370 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ9 [get_ports {ddr3_cke[0]}]
set_property src_info {type:XDC file:1 line:376 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AK9 [get_ports {ddr3_odt[0]}]
set_property src_info {type:XDC file:1 line:382 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH12 [get_ports {ddr3_cs_n[0]}]
set_property src_info {type:XDC file:1 line:388 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[0]}]
set_property src_info {type:XDC file:1 line:394 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[1]}]
set_property src_info {type:XDC file:1 line:400 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH4 [get_ports {ddr3_dm[2]}]
set_property src_info {type:XDC file:1 line:406 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF8 [get_ports {ddr3_dm[3]}]
set_property src_info {type:XDC file:1 line:411 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD12 [get_ports {sys_clk_p}]
set_property src_info {type:XDC file:1 line:416 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD11 [get_ports {sys_clk_n}]
set_property src_info {type:XDC file:1 line:422 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[0]}]
set_property src_info {type:XDC file:1 line:428 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[0]}]
set_property src_info {type:XDC file:1 line:434 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[1]}]
set_property src_info {type:XDC file:1 line:440 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[1]}]
set_property src_info {type:XDC file:1 line:446 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[2]}]
set_property src_info {type:XDC file:1 line:452 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[2]}]
set_property src_info {type:XDC file:1 line:458 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[3]}]
set_property src_info {type:XDC file:1 line:464 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[3]}]
set_property src_info {type:XDC file:1 line:470 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB9 [get_ports {ddr3_ck_p[0]}]
set_property src_info {type:XDC file:1 line:476 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC9 [get_ports {ddr3_ck_n[0]}]
set_property src_info {type:XDC file:1 line:481 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property src_info {type:XDC file:1 line:482 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property src_info {type:XDC file:1 line:483 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property src_info {type:XDC file:1 line:484 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property src_info {type:XDC file:1 line:485 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property src_info {type:XDC file:1 line:486 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property src_info {type:XDC file:1 line:487 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property src_info {type:XDC file:1 line:488 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
set_property src_info {type:XDC file:1 line:495 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:496 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:497 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:498 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
set_property src_info {type:XDC file:1 line:504 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y7 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property src_info {type:XDC file:1 line:505 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y6 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property src_info {type:XDC file:1 line:506 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y5 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property src_info {type:XDC file:1 line:507 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y4 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property src_info {type:XDC file:1 line:508 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property src_info {type:XDC file:1 line:509 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property src_info {type:XDC file:1 line:510 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property src_info {type:XDC file:1 line:511 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
set_property src_info {type:XDC file:1 line:514 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:515 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:516 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:517 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
set_property src_info {type:XDC file:1 line:520 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property src_info {type:XDC file:1 line:521 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
set_property src_info {type:XDC file:1 line:524 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_REF_X1Y1 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]
set_property src_info {type:XDC file:1 line:525 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]
set_property src_info {type:XDC file:1 line:528 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y143 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:529 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y131 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:530 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:531 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
set_property src_info {type:XDC file:1 line:535 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC PLLE2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
set_property src_info {type:XDC file:1 line:536 export:INPUT save:INPUT read:READ} [current_design]
set_property LOC MMCME2_ADV_X1Y1 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
set_property src_info {type:XDC file:1 line:544 export:INPUT save:INPUT read:READ} [current_design]
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] -hold 5
set_property src_info {type:XDC file:1 line:551 export:INPUT save:INPUT read:READ} [current_design]
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
set_property src_info {type:XDC file:1 line:555 export:INPUT save:INPUT read:READ} [current_design]
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
set_property src_info {type:XDC file:1 line:559 export:INPUT save:INPUT read:READ} [current_design]
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
|
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>xlnx_mig_7_ddr3</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
<Version>4.1</Version>
<SystemClock>Differential</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-107</MemoryDevice>
<TimePeriod>1250</TimePeriod>
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>32</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>4</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Clock>
<Pin PADName="AD12/AD11(CC_P/N)" Bank="33" name="sys_clk_p/n" />
</System_Clock>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>6</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C1_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C2_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_DDR3.MEMORY_PART"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C3_SYS_CLK_I.ASSOCIATED_BUSIF"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_CLOCK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C4_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C5_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C6_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.C7_SYS_CLK_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_REF_I.PHASE">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.AXI_ARBITRATION_SCHEME">TDM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.BURST_LENGTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAN_DEBUG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CAS_WRITE_LATENCY">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CS_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.CUSTOM_PARTS"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_MASK_ENABLED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_PART"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEMORY_TYPE">COMPONENTS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.MEM_ADDR_MAP">ROW_COLUMN_BANK</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.SLOT">Single</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3.TIMEPERIOD_PS">1250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DDR3_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LPDDR2_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT0.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT1.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT2.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT3.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_BUSIF"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_PORT"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.ASSOCIATED_RESET"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MMCM_CLKOUT4.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.QDRIIP_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDIII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RLDII_RESET.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S0_AXI.ID_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C0_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C1_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C2_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C3_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C4_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C5_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C6_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_C_S_AXI_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ODT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDR3_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DDRX_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_FREQ_HZ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_CNT_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_DQ_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_REG_CTRL">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_ROW_WIDTH">14</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_CS_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_DM_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_USE_ODT_PORT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCK_PER_CLK">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_LPDDR2_nCS_PER_RANK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MEM_TYPE">DDR3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT0_FREQ">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT1_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT2_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT3_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_EN">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_CLKOUT4_FREQ">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_MMCM_VCO">1200.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BURST_LEN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_BW_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_QDRIIP_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDIII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DEBUG_PORT">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_NUM_DEVICES">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QK_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_QVLD_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_RLD_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDII_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_ADDR_WIDTH">29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_BANK_WIDTH">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_CMD_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_DATA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_DM_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_RLDX_nCK_PER_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_UI_EXTRA_CLOCKS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C7_USE_AXI">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.COMBINED_INTERFACE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">30</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_CTRL_MEM_SIZE">1048576</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ID_WIDTH">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_MEM_SIZE">1073741824</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_ADDR_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_BANK_WIDTH">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CKE_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CK_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_CS_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DATA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR2_DEBUG_PORT">OFF</spirit:configurableElementValue>
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ion":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_READ_THREADS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_OUTSTANDING":[{"value":"2","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"NUM_WRITE_THREADS":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PHASE":[{"value":"0.0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"float","usage":"none","is_ips_inferred":true,"is_static_object":false}],"PROTOCOL":[{"value":"AXI4","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usa
ge":"none","is_ips_inferred":true,"is_static_object":false}],"READ_WRITE_MODE":[{"value":"READ_WRITE","value_src":"default","value_permission":"user","resolve_type":"generated","format":"string","usage":"none","is_ips_inferred":true,"is_static_object":false}],"RUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"RUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"SUPPORTS_NARROW_BURST":[{"value":"1","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}],"WUSER_BITS_PER_BYTE":[{"value":"0","value_src":"default","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is
_static_object":false}],"WUSER_WIDTH":[{"value":"0","value_src":"constant","value_permission":"user","resolve_type":"generated","format":"long","usage":"none","is_ips_inferred":true,"is_static_object":false}]},"port_maps":{"ARADDR":[{"physical_name":"s_axi_araddr","physical_left":"29","physical_right":"0","logical_left":"29","logical_right":"0","port_maps_used":"none"}],"ARBURST":[{"physical_name":"s_axi_arburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"ARCACHE":[{"physical_name":"s_axi_arcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARID":[{"physical_name":"s_axi_arid","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"ARLEN":[{"physical_name":"s_axi_arlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"ARLOCK":[{"physical_name":"s_axi_ar
lock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARPROT":[{"physical_name":"s_axi_arprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARQOS":[{"physical_name":"s_axi_arqos","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"ARREADY":[{"physical_name":"s_axi_arready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"ARSIZE":[{"physical_name":"s_axi_arsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"ARVALID":[{"physical_name":"s_axi_arvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWADDR":[{"physical_name":"s_axi_awaddr","physical_left":"29","physical_right":"0","logical_left":"29","logical_right":"0","port_maps_used":"non
e"}],"AWBURST":[{"physical_name":"s_axi_awburst","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"AWCACHE":[{"physical_name":"s_axi_awcache","physical_left":"3","physical_right":"0","logical_left":"3","logical_right":"0","port_maps_used":"none"}],"AWID":[{"physical_name":"s_axi_awid","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"AWLEN":[{"physical_name":"s_axi_awlen","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"AWLOCK":[{"physical_name":"s_axi_awlock","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWPROT":[{"physical_name":"s_axi_awprot","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWQOS":[{"physical_name":"s_axi_awqos","physical_left":"3","physical_right":"0","logical_left":"3","logical
_right":"0","port_maps_used":"none"}],"AWREADY":[{"physical_name":"s_axi_awready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"AWSIZE":[{"physical_name":"s_axi_awsize","physical_left":"2","physical_right":"0","logical_left":"2","logical_right":"0","port_maps_used":"none"}],"AWVALID":[{"physical_name":"s_axi_awvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BID":[{"physical_name":"s_axi_bid","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"BREADY":[{"physical_name":"s_axi_bready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"BRESP":[{"physical_name":"s_axi_bresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"BVALID":[{"physical_name":"s_axi_bvalid","physical_left":"0","physical_right
":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RDATA":[{"physical_name":"s_axi_rdata","physical_left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"RID":[{"physical_name":"s_axi_rid","physical_left":"5","physical_right":"0","logical_left":"5","logical_right":"0","port_maps_used":"none"}],"RLAST":[{"physical_name":"s_axi_rlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RREADY":[{"physical_name":"s_axi_rready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"RRESP":[{"physical_name":"s_axi_rresp","physical_left":"1","physical_right":"0","logical_left":"1","logical_right":"0","port_maps_used":"none"}],"RVALID":[{"physical_name":"s_axi_rvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WDATA":[{"physical_name":"s_axi_wdata","physical_
left":"63","physical_right":"0","logical_left":"63","logical_right":"0","port_maps_used":"none"}],"WLAST":[{"physical_name":"s_axi_wlast","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WREADY":[{"physical_name":"s_axi_wready","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}],"WSTRB":[{"physical_name":"s_axi_wstrb","physical_left":"7","physical_right":"0","logical_left":"7","logical_right":"0","port_maps_used":"none"}],"WVALID":[{"physical_name":"s_axi_wvalid","physical_left":"0","physical_right":"0","logical_left":"0","logical_right":"0","port_maps_used":"none"}]}}},"memory_maps":{"c0_memmap":{"address_blocks":{"c0_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c0_s_axi_ctrl_memmap":{"address_blocks":{"c0_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","descriptio
n":"","usage":"register","access":"read-write"}]}},"c1_memmap":{"address_blocks":{"c1_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c1_s_axi_ctrl_memmap":{"address_blocks":{"c1_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c2_memmap":{"address_blocks":{"c2_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c2_s_axi_ctrl_memmap":{"address_blocks":{"c2_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c3_memmap":{"address_blocks":{"c3_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c3_s_axi_ctrl_memmap":{"address_blocks":{"c3_s_axi_ctrl_memaddr":[{"base_address":"0","range":
"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c4_memmap":{"address_blocks":{"c4_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c4_s_axi_ctrl_memmap":{"address_blocks":{"c4_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c5_memmap":{"address_blocks":{"c5_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c5_s_axi_ctrl_memmap":{"address_blocks":{"c5_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c6_memmap":{"address_blocks":{"c6_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c6_s_axi_ctrl_memmap":{"address_blocks":{"c6_s_axi_ctrl
_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"c7_memmap":{"address_blocks":{"c7_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"c7_s_axi_ctrl_memmap":{"address_blocks":{"c7_s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}},"memmap":{"address_blocks":{"memaddr":[{"base_address":"0","range":"1073741824","display_name":"","description":"","usage":"memory","access":"read-write"}]}},"s_axi_ctrl_memmap":{"address_blocks":{"s_axi_ctrl_memaddr":[{"base_address":"0","range":"1048576","display_name":"","description":"","usage":"register","access":"read-write"}]}}}}}"/>
</xilinx:boundaryDescriptionInfo>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
|
PROJECT:=xlnx_protocol_checker
include ../common.mk |
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set ipName xlnx_protocol_checker
create_project $ipName . -force -part $partNumber
set_property board_part $boardName [current_project]
create_ip -name axi_protocol_checker -vendor xilinx.com -library ip -version 2.0 -module_name $ipName
set_property -dict [list CONFIG.ADDR_WIDTH {64} \
CONFIG.DATA_WIDTH {64} \
CONFIG.ID_WIDTH {6} \
CONFIG.AWUSER_WIDTH {1} \
CONFIG.ARUSER_WIDTH {1} \
CONFIG.RUSER_WIDTH {1} \
CONFIG.WUSER_WIDTH {1} \
CONFIG.BUSER_WIDTH {1} \
CONFIG.MAX_AW_WAITS {1024} \
CONFIG.MAX_AR_WAITS {1024} \
CONFIG.MAX_W_WAITS {1024} \
CONFIG.MAX_R_WAITS {1024} \
CONFIG.MAX_B_WAITS {1024} \
CONFIG.MAX_CONTINUOUS_WTRANSFERS_WAITS {1024} \
CONFIG.MAX_WLAST_TO_AWVALID_WAITS {1024} \
CONFIG.MAX_WRITE_TO_BVALID_WAITS {1024} \
CONFIG.MAX_CONTINUOUS_RTRANSFERS_WAITS {1024} \
] [get_ips $ipName]
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
launch_run -jobs 8 ${ipName}_synth_1
wait_on_run ${ipName}_synth_1
|
# EditorConfig (http://editorconfig.org/)
root = true
# Default Settings
[*]
charset = utf-8
end_of_line = lf
indent_size = 4
indent_style = space
insert_final_newline = true
tab_width = 4
trim_trailing_whitespace = true
max_line_length = 100
[*.{sv,svh,v,vg}]
indent_size = 2
tab_width = 2
[Makefile]
indent_style = tab
|
gitdir: ../../.git/modules/corev_apu/fpga-support
|
# Change Log
All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/), and this project adheres to
[Semantic Versioning](http://semver.org).
## [Unreleased]
- Switch default implementation from ALTERA to XILINX
- Add simulation init options to inferable rams (none, 0, random, deadbeef)
### Added
### Fixed
## [v0.3.2] - 2018-07-24
### Updated
- This package has been moved from the internal GitLab to GitHub. The Changelog and the affected
Read-Mes and scripts have been updated accordingly.
## [v0.3.1] - 2018-07-03
### Fixed
- `AxiToAxiLitePc`:
- Fixed bug with multiple parallel transactions. The AXI interface now only accepts a new request
after the response from the previous transaction has been acknowledged.
- Return `SLVERR` on burst requests. This module does not support bursts and now consistently
responds with a Slave Error on a burst request.
## [v0.3.0] - 2017-07-11
### Added
- Set of five inferable, synchronous BRAM-based memories:
- `SyncDpRam` (dual-port)
- `SyncSpRam` (single-port)
- `SyncSpRamBeNx32` (single-port N x 32bit with byte-wise enable)
- `SyncSpRamBeNx64` (single-port N x 64bit with byte-wise enable)
- `SyncTpRam` (two-port)
## [v0.2.3] - 2017-07-11
### Fixed
- `src_files.yml`: added missing comma at the end of the `AxiToAxiLitePc` entry.
## [v0.2.2] - 2017-07-11
### Fixed
- URLs to the GitLab repository of this project now correctly point to
`pulp-restricted/fpga-support` instead of the outdated `pulp-project/fpga-support`.
## [v0.2.1] - 2017-07-11
### Fixed
- `src_files.yml`: added the missing entry for `AxiToAxiLitePc`.
## [v0.2.0] - 2017-02-10
### Added
- `AxiToAxiLitePc`: a simple AXI to AXI Lite Protocol Converter.
### Fixed
- `BramDwc`: address registering. The address can now be changed between clock edges and the output
will still correspond to the address applied at the former clock edge.
- `BramDwc`: compatibility of interface port declarations with synthesis tools. Interface ports are
now explicitly declared either as `Master` or as `Slave`, so that synthesis tools will not infer
`inout` connections.
## [v0.1.1] - 2017-02-10
### Fixed
- `BramDwc`: address registering. The address can now be changed between clock edges and the output
will still correspond to the address applied at the former clock edge.
- `BramDwc`: compatibility of interface port declarations with synthesis tools. Interface ports are
now explicitly declared either as `Master` or as `Slave`, so that synthesis tools will not infer
`inout` connections.
## v0.1.0 - 2016-11-14
### Added
- Three Block RAM (BRAM)-related modules:
- `BramPort`: the standard interface for Xilinx BRAMs,
- `TdpBramArray`: an array of Xilinx True Dual-Port BRAM cells with a standard BRAM interface, and
- `BramDwc`: a Data Width Converter from a narrow master BRAM controller to a wide slave BRAM
(array).
- `BramLogger`: a logger that writes events to a `TdpBramArray`.
- `AxiBramLogger`: a logger to keep track of events on an AXI bus. This module is build on
`BramLogger`.
[Unreleased]: https://github.com/pulp-platform/fpga-support/compare/v0.3.2...HEAD
[v0.3.2]: https://github.com/pulp-platform/fpga-support/compare/v0.3.1...v0.3.2
[v0.3.1]: https://github.com/pulp-platform/fpga-support/compare/v0.3.0...v0.3.1
[v0.3.0]: https://github.com/pulp-platform/fpga-support/compare/v0.2.3...v0.3.0
[v0.2.3]: https://github.com/pulp-platform/fpga-support/compare/v0.2.2...v0.2.3
[v0.2.2]: https://github.com/pulp-platform/fpga-support/compare/v0.2.1...v0.2.2
[v0.2.1]: https://github.com/pulp-platform/fpga-support/compare/v0.2.0...v0.2.1
[v0.2.0]: https://github.com/pulp-platform/fpga-support/compare/v0.1.0...v0.2.0
[v0.1.1]: https://github.com/pulp-platform/fpga-support/compare/v0.1.0...v0.1.1
|
# Contribution Guidelines
If you find bugs or have questions or feature requests, please discuss the issue the maintainer of
the respective IP block (see header of the source file). All developers are encouraged to
contribute small, simple patches that can be reviewed easily. If your patch is too large, break it
into logically connected, atomic units. A best-practice contribution follows this sequence:
1. Add a test to the testbench that clearly specifies the bug or feature you want to tackle. As
you have not contributed your code yet, this test must fail. Have it do so with a descriptive
reason.
2. Write the code that meets your specifications, thus causes the test to pass. The code does not
yet have to be perfect, as it will be improved later.
3. Run all tests in this repository and make sure they *all* pass. Do *not* modify any tests other
than the one you added for this contribution.
4. Reach back to the maintainer to discuss specifications and code. If your code initially caused
any other tests to fail and you had to modify existing code to get them to pass again, mention
this.
5. Refactor your code to make it clean, simple, and maintainable. Repeat steps 3 to 5 until no
refactoring is necessary anymore. Ask the maintainer to merge your contribution.
We only accept contributions that follow the formatting conventions specified by the
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chances are good that it can automatically take care of this (either out of the box or with a
plugin, see http://editorconfig.org for more information).
|
SOLDERPAD HARDWARE LICENSE version 0.51
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As this license is not currently OSI or FSF approved, the Licensor permits any
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If the Work includes a "NOTICE" text file as part of its distribution, then
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5. Submission of Contributions. Unless You explicitly state otherwise, any
Contribution intentionally submitted for inclusion in the Work by You to the
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8. Limitation of Liability. In no event and under no legal theory, whether in
tort (including negligence), contract, or otherwise, unless required by
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writing, shall any Contributor be liable to You for damages, including any
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use the Work (including but not limited to damages for loss of goodwill, work
stoppage, computer failure or malfunction, or any and all other commercial
damages or losses), even if such Contributor has been advised of the
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9. Accepting Warranty or Additional Liability. While redistributing the Work or
Derivative Works thereof, You may choose to offer, and charge a fee for,
acceptance of support, warranty, indemnity, or other liability obligations
and/or rights consistent with this License. However, in accepting such
obligations, You may act only on Your own behalf and on Your sole
responsibility, not on behalf of any other Contributor, and only if You agree
to indemnify, defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason of your
accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
|
# IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
This repository contains IP blocks that can be useful in many aspects of working with PULP on FPGA
platforms. The repository is structured as follows:
- `behav/` Behavioral Simulation and Tests; contains one subdirectory for each module.
- `rtl/` End-User RTL Code
- `synth/` Post-Synthesis Simulation and Tests; contains one subdirectory for each module.
## Usage
Many IP blocks in this repository depend on the [CfMath](https://github.com/pulp-platform/cfmath)
package. Make sure to have that package on the list of source files for elaboration. For
behavioral and post-synthesis simulations, set the `CF_MATH_PKG_PATH` environment variable to the
path where you have that package installed.
Add all files in the `rtl/` folder to the list of compilation files of your development tool (e.g.,
Xilinx Vivado). Read the documentation (header of the source file) of the block that you want to
use and use the block as described there.
## Contributing
Thank you for your intent to contribute to improving the quality and usefulness of this repository!
In the interest of making this an optimal experience for you, the maintainers, and the users, please
follow the [Contribution Guidelines](CONTRIBUTING.md)
|
fpga-support:
files: [
rtl/AxiBramLogger.sv,
rtl/AxiToAxiLitePc.sv,
rtl/BramDwc.sv,
rtl/BramLogger.sv,
rtl/BramPort.sv,
rtl/SyncDpRam.sv,
rtl/SyncSpRam.sv,
rtl/SyncSpRamBeNx32.sv,
rtl/SyncSpRamBeNx64.sv,
rtl/SyncTpRam.sv,
rtl/TdpBramArray.sv,
]
|
TARGETS = $(filter-out common/.,$(wildcard */.))
.PHONY: all ${TARGETS}
all: ${TARGETS}
${TARGETS}:
$(MAKE) -C $@
|
/work/*
/*.log
/*.out
/*.wlf
/modelsim.ini
/transcript
|
LIB = work
VER = 10.5c
VLOG_OPTS = -work $(LIB) +incdir+../common/include
ASSERT_LOG = assert.log
COMPILE_LOG = compile.log
SIMULATE_LOG = simulate.log
RUNSCRIPT_NOGUI = ./scripts/run.tcl
RUNSCRIPT_GUI = ./scripts/run_gui.tcl
# Path to the 'CfMath' package. This default path is correct when this package is used in the
# 'big.pulp' repository. Otherwise, adapt it so that 'CfMath.sv' can be found at this path.
CF_MATH_PKG_PATH ?= ../../../../../fe/ips/pkg/cfmath
PKGS = $(CF_MATH_PKG_PATH)/CfMath.sv
SRCS = $(wildcard ../common/modules/*.sv) $(wildcard ../../rtl/*.sv)
nogui: ${LIB} compile sim_nogui evaluate
gui: ${LIB} compile sim_gui
${LIB}:
@vlib-${VER} ${LIB}
compile: $(PKGS) $(SRCS) Testbench.sv
@rm -f $(COMPILE_LOG)
@vlog-${VER} $(VLOG_OPTS) $^ >> $(COMPILE_LOG); \
rc=$$?; \
if [ $$rc != 0 ]; then \
cat $(COMPILE_LOG); \
exit $$rc; \
fi
sim_nogui:
@if [ -e '$(RUNSCRIPT_NOGUI)' ]; then \
RUN_CMD="source $(RUNSCRIPT_NOGUI)"; \
else \
RUN_CMD="run"; \
fi; \
vsim-${VER} -c -do "$$RUN_CMD; quit" -assertfile $(ASSERT_LOG) $(LIB).Testbench > $(SIMULATE_LOG); \
rc=$$?; \
if [ $$rc != 0 ]; then \
cat $(SIMULATE_LOG); \
exit $$rc; \
fi
sim_gui:
@if [ -e '$(RUNSCRIPT_GUI)' ]; then \
RUN_CMD="source $(RUNSCRIPT_GUI)"; \
else \
RUN_CMD="run"; \
fi; \
vsim-${VER} -voptargs=+acc -do "$$RUN_CMD" $(LIB).Testbench
evaluate:
@if [ \"$$(wc -l $(ASSERT_LOG) | cut -d' ' -f1)\" != \"0\" ]; then \
cat $(ASSERT_LOG); \
exit 1; \
else \
echo "All assertions passed."; \
fi
clean:
@rm -rf work
@rm -f *.log *.out *.wlf
@rm -f modelsim.ini transcript
|
# BRAM Data Width Converter Behavioral Testbench
## Running Tests
This module depends on the `CfMath` package. You have to specify the path to this package when
running tests. If this module is not used as part of the `big.pulp` project, specify the correct
path to the package in `CF_MATH_PKG_PATH`, e.g.,
CF_MATH_PKG_PATH=../../../../../fe/ips/pkg/cfmath make
|
// Copyright 2016 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* BRAM Data Width Converter Testbench
*
* Current Maintainers:
* - Andreas Kurth <[email protected]>
* - Pirmin Vogel <[email protected]>
*/
`include "assertions.sv"
module Testbench
// Parameters {{{
#(
parameter CLK_PERIOD = 10ns,
parameter STIM_APPL_DELAY = 5ns,
parameter RESP_ACQ_DELAY = 2ns,
parameter STIM_PATH = "./vectors/stim.txt",
parameter EXP_RESP_PATH = "./vectors/expresp.txt"
);
// }}}
// Module-Wide Constants {{{
localparam integer ADDR_BITW = 32;
localparam integer MST_DATA_BITW = 32;
localparam integer SLV_DATA_BITW = 96;
// }}}
// Clock and Reset Generator {{{
logic Clk_C, Rst_RB, EndOfSim_S;
ClkRstGen
#(
.CLK_LOW_TIME (CLK_PERIOD/2),
.CLK_HIGH_TIME (CLK_PERIOD/2)
)
clkRstGen
(
.EndOfSim_SI (EndOfSim_S),
.Clk_CO (Clk_C),
.Rst_RBO (Rst_RB)
);
// }}}
// Instantiation of Master and Slave Interfaces to be connected {{{
BramPort
#(
.DATA_BITW(MST_DATA_BITW),
.ADDR_BITW(ADDR_BITW)
) Bram_PM ();
BramPort
#(
.DATA_BITW(SLV_DATA_BITW),
.ADDR_BITW(ADDR_BITW)
) Bram_PS ();
// }}}
// DUT Instantiation {{{
BramDwc
#(
.ADDR_BITW (ADDR_BITW),
.MST_DATA_BITW(MST_DATA_BITW),
.SLV_DATA_BITW(SLV_DATA_BITW)
) dut (
.FromMaster_PS(Bram_PM),
.ToSlave_PM (Bram_PS)
);
// }}}
// Master Driver {{{
assign Bram_PM.Clk_C = Clk_C;
assign Bram_PM.Rst_R = ~Rst_RB;
assign Bram_PM.En_S = '1;
// }}}
// Assert properties that always hold. {{{
always @ (Bram_PM.Clk_C) begin
assert (Bram_PS.Clk_C == Bram_PM.Clk_C)
else $error("Slave clock is not equal to master clock!");
assert (Bram_PS.En_S == Bram_PM.En_S)
else $error("Slave enable signal is not equal to master enable signal!");
end
always @ (Bram_PM.Rst_R) begin
assert (Bram_PS.Rst_R == Bram_PM.Rst_R)
else $error("Slave reset signal is not equal to master reset signal!");
end
// }}}
// Set simulation up. {{{
integer stim_fd, expresp_fd;
logic EndOfStim_S = 0;
logic EndOfExpResp_S = 0;
assign EndOfSim_S = EndOfStim_S && EndOfExpResp_S;
initial begin
// Open files with test vectors. {{{
stim_fd = $fopen(STIM_PATH, "r");
if (stim_fd == 0)
$fatal(1, "Failed to open stimuli file '%s'!", STIM_PATH);
expresp_fd = $fopen(EXP_RESP_PATH, "r");
if (expresp_fd == 0)
$fatal(1, "Failed to open expected responses file '%s'!", EXP_RESP_PATH);
// }}}
end
// }}}
// Apply stimuli. {{{
string stim_vec;
integer stim_read;
struct {
logic [32-1:0] Addr_S;
logic [ 4-1:0] WrEn_S;
logic [96-1:0] Rd_D;
logic [32-1:0] Wr_D;
} Stim;
integer stim_ln = 0;
always @ (posedge Clk_C) begin
if (~EndOfStim_S) begin
stim_read = 0;
while (stim_read != 4) begin
stim_ln = stim_ln + 1;
stim_read = $fgets(stim_vec, stim_fd);
stim_read = $sscanf(stim_vec, "%h %h %h %h",
Stim.Addr_S, Stim.WrEn_S, Stim.Wr_D, Stim.Rd_D);
if ($feof(stim_fd)) begin
EndOfStim_S = 1;
break;
end
end
#STIM_APPL_DELAY;
Bram_PM.Addr_S = Stim.Addr_S;
Bram_PM.WrEn_S = Stim.WrEn_S;
Bram_PM.Wr_D = Stim.Wr_D;
Bram_PS.Rd_D = Stim.Rd_D;
end
end
// }}}
// Acquire and compare expected responses. {{{
logic ExpRespAcqEn_S = 0;
string expresp_vec;
integer expresp_read;
struct {
logic [32-1:0] Addr_S;
logic [12-1:0] WrEn_S;
logic [32-1:0] Rd_D;
logic [96-1:0] Wr_D;
} ExpResp;
integer expresp_ln = 0;
always @ (posedge Clk_C) begin
if (ExpRespAcqEn_S) begin
if (~EndOfExpResp_S) begin
expresp_read = 0;
while (expresp_read != 4) begin
expresp_ln = expresp_ln + 1;
expresp_read = $fgets(expresp_vec, expresp_fd);
expresp_read = $sscanf(expresp_vec, "%h %h %h %h",
ExpResp.Addr_S, ExpResp.WrEn_S, ExpResp.Wr_D, ExpResp.Rd_D);
if ($feof(expresp_fd)) begin
EndOfExpResp_S = 1;
break;
end
end
if (~EndOfExpResp_S) begin
#RESP_ACQ_DELAY;
`assert_equal_msg(Bram_PS.Addr_S, ExpResp.Addr_S, "Addr_S", expresp_ln);
`assert_equal_msg(Bram_PS.WrEn_S, ExpResp.WrEn_S, "WrEn_S", expresp_ln);
`assert_equal_msg(Bram_PS.Wr_D, ExpResp.Wr_D, "Wr_D", expresp_ln);
`assert_equal_msg(Bram_PM.Rd_D, ExpResp.Rd_D, "Rd_D", expresp_ln);
end
end
end else begin
ExpRespAcqEn_S = 1;
end
end
// }}}
// Deactivated Tests {{{
// The following code would correctly fail fatally. The code is currently inactive to avoid
// confusion with real assertion failures.
/*
BramPort
#(
.DATA_BITW(96),
.ADDR_BITW(32)
) wideMaster ();
BramPort
#(
.DATA_BITW(32),
.ADDR_BITW(32)
) narrowSlave ();
BramDwc incorrectFromToBitwidths
(
.FromMaster_PS(wideMaster),
.ToSlave_PM (narrowSlave)
);
*/
// }}}
endmodule
// vim: nosmartindent autoindent foldmethod=marker
|
run -all
# vim: syntax=tcl
|
source ./scripts/waves.tcl
source ./scripts/run.tcl
# vim: syntax=tcl
|
quietly WaveActivateNextPane {} 0
configure wave -signalnamewidth 1
delete wave *
add wave -noupdate /Testbench/Clk_C
add wave -noupdate /Testbench/Rst_RB
add wave -noupdate /Testbench/EndOfSim_S
add wave -noupdate -expand -group Bram_PM /Testbench/Bram_PM/*
add wave -noupdate -expand -group Bram_PS /Testbench/Bram_PS/*
add wave -noupdate -expand /Testbench/ExpResp
update
# vim: syntax=tcl
|
# Bram_PS.
# Addr_S WrEn_S Wr_D
# Bram_PM. Rd_D
# sequential writes
0000 00F 111111111111111111111111 00000000
0000 0F0 222222222222222222222222 00000000
0000 F00 333333333333333333333333 00000000
0010 00F 444444444444444444444444 00000000
0010 0F0 555555555555555555555555 00000000
0010 F00 666666666666666666666666 00000000
0020 00F 777777777777777777777777 00000000
0020 0F0 888888888888888888888888 00000000
0020 F00 999999999999999999999999 00000000
# sequential reads
0000 000 000000000000000000000000 11111111
0000 000 000000000000000000000000 22222222
0000 000 000000000000000000000000 33333333
0010 000 000000000000000000000000 44444444
0010 000 000000000000000000000000 55555555
0010 000 000000000000000000000000 66666666
0020 000 000000000000000000000000 77777777
0020 000 000000000000000000000000 88888888
0020 000 000000000000000000000000 99999999
# random writes
14D0 0F0 133713371337133713371337 42424242
D7430 00F 133713371337133713371337 42424242
314FD0 F00 133713371337133713371337 42424242
# random reads
6A80 000 000000000000000000000000 12345678
2B0230 000 000000000000000000000000 12345678
213FF0 000 000000000000000000000000 12345678
|
# Bram_PM.
# Addr_S WrEn_S Wr_D
# Bram_PS. Rd_D
# sequential writes
0000 F 11111111 000000000000000000000000
0004 F 22222222 000000000000000011111111
0008 F 33333333 000000002222222211111111
000C F 44444444 000000000000000000000000
0010 F 55555555 000000000000000044444444
0014 F 66666666 000000005555555544444444
0018 F 77777777 000000000000000000000000
001C F 88888888 000000000000000077777777
0020 F 99999999 000000008888888877777777
# sequential reads
0000 0 00000000 50000BAD50000BAD11111111
0004 0 00000000 50000BAD2222222250000BAD
0008 0 00000000 3333333350000BAD50000BAD
000C 0 00000000 50000BAD50000BAD44444444
0010 0 00000000 50000BAD5555555550000BAD
0014 0 00000000 6666666650000BAD50000BAD
0018 0 00000000 50000BAD50000BAD77777777
001C 0 00000000 50000BAD8888888850000BAD
0020 0 00000000 9999999950000BAD50000BAD
# random write
0FA0 F 13371337 50000BAD4242424250000BAD
A1724 F 13371337 50000BAD50000BAD42424242
24FBE4 F 13371337 4242424250000BAD50000BAD
# random read
4FE0 0 00000000 BAAAAAAABAAAAAAA12345678
2041AC 0 00000000 12345678BAAAAAAABAAAAAAA
18EFF8 0 00000000 BAAAAAAA12345678BAAAAAAA
|
/work/*
/*.log
/*.out
/*.wlf
/modelsim.ini
/transcript
|
LIB = work
VER = 10.5c
VLOG_OPTS = -work $(LIB) +incdir+../common/include
ASSERT_LOG = assert.log
COMPILE_LOG = compile.log
SIMULATE_LOG = simulate.log
RUNSCRIPT_NOGUI = ./scripts/run.tcl
RUNSCRIPT_GUI = ./scripts/run_gui.tcl
# Path to the 'CfMath' package. This default path is correct when this package is used in the
# 'big.pulp' repository. Otherwise, adapt it so that 'CfMath.sv' can be found at this path.
CF_MATH_PKG_PATH ?= ../../../../../fe/ips/pkg/cfmath
PKGS = $(CF_MATH_PKG_PATH)/CfMath.sv
SRCS = $(wildcard ../common/modules/*.sv) $(wildcard ../../rtl/*.sv)
nogui: ${LIB} compile sim_nogui evaluate
gui: ${LIB} compile sim_gui
${LIB}:
@vlib-${VER} ${LIB}
compile: $(PKGS) $(SRCS) Testbench.sv
@rm -f $(COMPILE_LOG)
@vlog-${VER} $(VLOG_OPTS) $^ >> $(COMPILE_LOG); \
rc=$$?; \
if [ $$rc != 0 ]; then \
cat $(COMPILE_LOG); \
exit $$rc; \
fi
sim_nogui:
@if [ -e '$(RUNSCRIPT_NOGUI)' ]; then \
RUN_CMD="source $(RUNSCRIPT_NOGUI)"; \
else \
RUN_CMD="run"; \
fi; \
vsim-${VER} -c -do "$$RUN_CMD; quit" -assertfile $(ASSERT_LOG) $(LIB).Testbench > $(SIMULATE_LOG); \
rc=$$?; \
if [ $$rc != 0 ]; then \
cat $(SIMULATE_LOG); \
exit $$rc; \
fi
sim_gui:
@if [ -e '$(RUNSCRIPT_GUI)' ]; then \
RUN_CMD="source $(RUNSCRIPT_GUI)"; \
else \
RUN_CMD="run"; \
fi; \
vsim-${VER} -voptargs=+acc -do "$$RUN_CMD" $(LIB).Testbench
evaluate:
@if [ \"$$(wc -l $(ASSERT_LOG) | cut -d' ' -f1)\" != \"0\" ]; then \
cat $(ASSERT_LOG); \
exit 1; \
else \
echo "All assertions passed."; \
fi
clean:
@rm -rf work
@rm -f *.log *.out *.wlf
@rm -f modelsim.ini transcript
|
// Copyright 2016 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* Assertions for Actual/Expected Comparisons in Testbenches
*
* Current Maintainers:
* - Andreas Kurth <[email protected]>
* - Pirmin Vogel <[email protected]>
*/
`ifndef ASSERTIONS_SV
`define ASSERTIONS_SV
`define assert_equal(actual, expected) \
assert (actual == expected) \
else $error("Failed assertion: %0d == %0d", actual, expected);
`define assert_equal_msg(actual, expected, msg, ln) \
assert (actual == expected) \
else $error("Failed assertion (ExpResp LN %04d, %s): %x == %x", \
ln, msg, actual, expected);
`endif // ASSERTIONS_SV
// vim: nosmartindent autoindent
|
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