Spaces:
Runtime error
Runtime error
File size: 20,121 Bytes
b86f76f |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 |
/*
* Loongson SIMD utils
*
* Copyright (c) 2016 Loongson Technology Corporation Limited
* Copyright (c) 2016 Zhou Xiaoyong <[email protected]>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef AVUTIL_MIPS_MMIUTILS_H
#define AVUTIL_MIPS_MMIUTILS_H
#include "config.h"
#include "libavutil/mem_internal.h"
#include "libavutil/mips/asmdefs.h"
/*
* These were used to define temporary registers for MMI marcos
* however now we're using $at. They're theoretically unnecessary
* but just leave them here to avoid mess.
*/
#define DECLARE_VAR_LOW32
#define RESTRICT_ASM_LOW32
#define DECLARE_VAR_ALL64
#define RESTRICT_ASM_ALL64
#define DECLARE_VAR_ADDRT
#define RESTRICT_ASM_ADDRT
#if HAVE_LOONGSON2
#define MMI_LWX(reg, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
"lw "#reg", "#bias"($at) \n\t" \
".set at \n\t"
#define MMI_SWX(reg, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
"sw "#reg", "#bias"($at) \n\t" \
".set at \n\t"
#define MMI_LDX(reg, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
"ld "#reg", "#bias"($at) \n\t" \
".set at \n\t"
#define MMI_SDX(reg, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
"sd "#reg", "#bias"($at) \n\t" \
".set at \n\t"
#define MMI_LWC1(fp, addr, bias) \
"lwc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_ULWC1(fp, addr, bias) \
".set noat \n\t" \
"ulw $at, "#bias"("#addr") \n\t" \
"mtc1 $at, "#fp" \n\t" \
".set at \n\t"
#define MMI_LWXC1(fp, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
MMI_LWC1(fp, $at, bias) \
".set at \n\t"
#define MMI_SWC1(fp, addr, bias) \
"swc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_USWC1(fp, addr, bias) \
".set noat \n\t" \
"mfc1 $at, "#fp" \n\t" \
"usw $at, "#bias"("#addr") \n\t" \
".set at \n\t"
#define MMI_SWXC1(fp, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
MMI_SWC1(fp, $at, bias) \
".set at \n\t"
#define MMI_LDC1(fp, addr, bias) \
"ldc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_ULDC1(fp, addr, bias) \
".set noat \n\t" \
"uld $at, "#bias"("#addr") \n\t" \
"dmtc1 $at, "#fp" \n\t" \
".set at \n\t"
#define MMI_LDXC1(fp, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
MMI_LDC1(fp, $at, bias) \
".set at \n\t"
#define MMI_SDC1(fp, addr, bias) \
"sdc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_USDC1(fp, addr, bias) \
".set noat \n\t" \
"dmfc1 $at, "#fp" \n\t" \
"usd $at, "#bias"("#addr") \n\t" \
".set at \n\t"
#define MMI_SDXC1(fp, addr, stride, bias) \
".set noat \n\t" \
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
MMI_SDC1(fp, $at, bias) \
".set at \n\t"
#define MMI_LQ(reg1, reg2, addr, bias) \
"ld "#reg1", "#bias"("#addr") \n\t" \
"ld "#reg2", 8+"#bias"("#addr") \n\t"
#define MMI_SQ(reg1, reg2, addr, bias) \
"sd "#reg1", "#bias"("#addr") \n\t" \
"sd "#reg2", 8+"#bias"("#addr") \n\t"
#define MMI_LQC1(fp1, fp2, addr, bias) \
"ldc1 "#fp1", "#bias"("#addr") \n\t" \
"ldc1 "#fp2", 8+"#bias"("#addr") \n\t"
#define MMI_SQC1(fp1, fp2, addr, bias) \
"sdc1 "#fp1", "#bias"("#addr") \n\t" \
"sdc1 "#fp2", 8+"#bias"("#addr") \n\t"
#elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */
#define MMI_LWX(reg, addr, stride, bias) \
"gslwx "#reg", "#bias"("#addr", "#stride") \n\t"
#define MMI_SWX(reg, addr, stride, bias) \
"gsswx "#reg", "#bias"("#addr", "#stride") \n\t"
#define MMI_LDX(reg, addr, stride, bias) \
"gsldx "#reg", "#bias"("#addr", "#stride") \n\t"
#define MMI_SDX(reg, addr, stride, bias) \
"gssdx "#reg", "#bias"("#addr", "#stride") \n\t"
#define MMI_LWC1(fp, addr, bias) \
"lwc1 "#fp", "#bias"("#addr") \n\t"
#if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */
#define MMI_LWLRC1(fp, addr, bias, off) \
".set noat \n\t" \
"lwl $at, "#bias"+"#off"("#addr") \n\t" \
"lwr $at, "#bias"("#addr") \n\t" \
"mtc1 $at, "#fp" \n\t" \
".set at \n\t"
#else /* _MIPS_SIM != _ABIO32 */
#define DECLARE_VAR_LOW32
#define RESTRICT_ASM_LOW32
#define MMI_ULWC1(fp, addr, bias) \
"gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \
"gslwrc1 "#fp", "#bias"("#addr") \n\t"
#endif /* _MIPS_SIM != _ABIO32 */
#define MMI_LWXC1(fp, addr, stride, bias) \
"gslwxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
#define MMI_SWC1(fp, addr, bias) \
"swc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_USWC1(fp, addr, bias) \
"gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \
"gsswrc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_SWXC1(fp, addr, stride, bias) \
"gsswxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
#define MMI_LDC1(fp, addr, bias) \
"ldc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_ULDC1(fp, addr, bias) \
"gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \
"gsldrc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_LDXC1(fp, addr, stride, bias) \
"gsldxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
#define MMI_SDC1(fp, addr, bias) \
"sdc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_USDC1(fp, addr, bias) \
"gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \
"gssdrc1 "#fp", "#bias"("#addr") \n\t"
#define MMI_SDXC1(fp, addr, stride, bias) \
"gssdxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
#define MMI_LQ(reg1, reg2, addr, bias) \
"gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
#define MMI_SQ(reg1, reg2, addr, bias) \
"gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
#define MMI_LQC1(fp1, fp2, addr, bias) \
"gslqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
#define MMI_SQC1(fp1, fp2, addr, bias) \
"gssqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
#endif /* HAVE_LOONGSON2 */
/**
* Backup saved registers
* We're not using compiler's clobber list as it's not smart enough
* to take advantage of quad word load/store.
*/
#define BACKUP_REG \
LOCAL_ALIGNED_16(double, temp_backup_reg, [8]); \
if (_MIPS_SIM == _ABI64) \
__asm__ volatile ( \
MMI_SQC1($f25, $f24, %[temp], 0x00) \
MMI_SQC1($f27, $f26, %[temp], 0x10) \
MMI_SQC1($f29, $f28, %[temp], 0x20) \
MMI_SQC1($f31, $f30, %[temp], 0x30) \
: \
: [temp]"r"(temp_backup_reg) \
: "memory" \
); \
else \
__asm__ volatile ( \
MMI_SQC1($f22, $f20, %[temp], 0x10) \
MMI_SQC1($f26, $f24, %[temp], 0x10) \
MMI_SQC1($f30, $f28, %[temp], 0x20) \
: \
: [temp]"r"(temp_backup_reg) \
: "memory" \
);
/**
* recover register
*/
#define RECOVER_REG \
if (_MIPS_SIM == _ABI64) \
__asm__ volatile ( \
MMI_LQC1($f25, $f24, %[temp], 0x00) \
MMI_LQC1($f27, $f26, %[temp], 0x10) \
MMI_LQC1($f29, $f28, %[temp], 0x20) \
MMI_LQC1($f31, $f30, %[temp], 0x30) \
: \
: [temp]"r"(temp_backup_reg) \
: "memory" \
); \
else \
__asm__ volatile ( \
MMI_LQC1($f22, $f20, %[temp], 0x10) \
MMI_LQC1($f26, $f24, %[temp], 0x10) \
MMI_LQC1($f30, $f28, %[temp], 0x20) \
: \
: [temp]"r"(temp_backup_reg) \
: "memory" \
);
/**
* brief: Transpose 2X2 word packaged data.
* fr_i0, fr_i1: src
* fr_o0, fr_o1: dst
*/
#define TRANSPOSE_2W(fr_i0, fr_i1, fr_o0, fr_o1) \
"punpcklwd "#fr_o0", "#fr_i0", "#fr_i1" \n\t" \
"punpckhwd "#fr_o1", "#fr_i0", "#fr_i1" \n\t"
/**
* brief: Transpose 4X4 half word packaged data.
* fr_i0, fr_i1, fr_i2, fr_i3: src & dst
* fr_t0, fr_t1, fr_t2, fr_t3: temporary register
*/
#define TRANSPOSE_4H(fr_i0, fr_i1, fr_i2, fr_i3, \
fr_t0, fr_t1, fr_t2, fr_t3) \
"punpcklhw "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
"punpckhhw "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
"punpcklhw "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
"punpckhhw "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
"punpcklwd "#fr_i0", "#fr_t0", "#fr_t2" \n\t" \
"punpckhwd "#fr_i1", "#fr_t0", "#fr_t2" \n\t" \
"punpcklwd "#fr_i2", "#fr_t1", "#fr_t3" \n\t" \
"punpckhwd "#fr_i3", "#fr_t1", "#fr_t3" \n\t"
/**
* brief: Transpose 8x8 byte packaged data.
* fr_i0~i7: src & dst
* fr_t0~t3: temporary register
*/
#define TRANSPOSE_8B(fr_i0, fr_i1, fr_i2, fr_i3, fr_i4, fr_i5, \
fr_i6, fr_i7, fr_t0, fr_t1, fr_t2, fr_t3) \
"punpcklbh "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
"punpckhbh "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
"punpcklbh "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
"punpckhbh "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
"punpcklbh "#fr_i0", "#fr_i4", "#fr_i5" \n\t" \
"punpckhbh "#fr_i1", "#fr_i4", "#fr_i5" \n\t" \
"punpcklbh "#fr_i2", "#fr_i6", "#fr_i7" \n\t" \
"punpckhbh "#fr_i3", "#fr_i6", "#fr_i7" \n\t" \
"punpcklhw "#fr_i4", "#fr_t0", "#fr_t2" \n\t" \
"punpckhhw "#fr_i5", "#fr_t0", "#fr_t2" \n\t" \
"punpcklhw "#fr_i6", "#fr_t1", "#fr_t3" \n\t" \
"punpckhhw "#fr_i7", "#fr_t1", "#fr_t3" \n\t" \
"punpcklhw "#fr_t0", "#fr_i0", "#fr_i2" \n\t" \
"punpckhhw "#fr_t1", "#fr_i0", "#fr_i2" \n\t" \
"punpcklhw "#fr_t2", "#fr_i1", "#fr_i3" \n\t" \
"punpckhhw "#fr_t3", "#fr_i1", "#fr_i3" \n\t" \
"punpcklwd "#fr_i0", "#fr_i4", "#fr_t0" \n\t" \
"punpckhwd "#fr_i1", "#fr_i4", "#fr_t0" \n\t" \
"punpcklwd "#fr_i2", "#fr_i5", "#fr_t1" \n\t" \
"punpckhwd "#fr_i3", "#fr_i5", "#fr_t1" \n\t" \
"punpcklwd "#fr_i4", "#fr_i6", "#fr_t2" \n\t" \
"punpckhwd "#fr_i5", "#fr_i6", "#fr_t2" \n\t" \
"punpcklwd "#fr_i6", "#fr_i7", "#fr_t3" \n\t" \
"punpckhwd "#fr_i7", "#fr_i7", "#fr_t3" \n\t"
/**
* brief: Parallel SRA for 8 byte packaged data.
* fr_i0: src
* fr_i1: SRA number(SRAB number + 8)
* fr_t0, fr_t1: temporary register
* fr_d0: dst
*/
#define PSRAB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
"psrah "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
"psrah "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
/**
* brief: Parallel SRL for 8 byte packaged data.
* fr_i0: src
* fr_i1: SRL number(SRLB number + 8)
* fr_t0, fr_t1: temporary register
* fr_d0: dst
*/
#define PSRLB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
"psrlh "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
"psrlh "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
#define PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
"psrah "#fp1", "#fp1", "#shift" \n\t" \
"psrah "#fp2", "#fp2", "#shift" \n\t" \
"psrah "#fp3", "#fp3", "#shift" \n\t" \
"psrah "#fp4", "#fp4", "#shift" \n\t"
#define PSRAH_8_MMI(fp1, fp2, fp3, fp4, fp5, fp6, fp7, fp8, shift) \
PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
PSRAH_4_MMI(fp5, fp6, fp7, fp8, shift)
/**
* brief: (((value) + (1 << ((n) - 1))) >> (n))
* fr_i0: src & dst
* fr_i1: Operand number
* fr_t0, fr_t1: temporary FPR
* gr_t0: temporary GPR
*/
#define ROUND_POWER_OF_TWO_MMI(fr_i0, fr_i1, fr_t0, fr_t1, gr_t0) \
"li "#gr_t0", 0x01 \n\t" \
"dmtc1 "#gr_t0", "#fr_t0" \n\t" \
"punpcklwd "#fr_t0", "#fr_t0", "#fr_t0" \n\t" \
"psubw "#fr_t1", "#fr_i1", "#fr_t0" \n\t" \
"psllw "#fr_t1", "#fr_t0", "#fr_t1" \n\t" \
"paddw "#fr_i0", "#fr_i0", "#fr_t1" \n\t" \
"psraw "#fr_i0", "#fr_i0", "#fr_i1" \n\t"
#endif /* AVUTILS_MIPS_MMIUTILS_H */
|